CN111308813B

CN111308813B - Display panel

Info

Publication number: CN111308813B
Application number: CN202010139208.7A
Authority: CN
Inventors: 朱静
Original assignee: TCL Huaxing Photoelectric Technology Co Ltd
Current assignee: TCL Huaxing Photoelectric Technology Co Ltd
Priority date: 2020-03-03
Filing date: 2020-03-03
Publication date: 2022-04-26
Anticipated expiration: 2040-03-03
Also published as: CN111308813A

Abstract

The application discloses a display panel, which comprises a lower substrate and an upper substrate which are arranged opposite to each other and are bonded through a conductive adhesive; the upper substrate is provided with a GOA circuit; the lower substrate is formed with signal lines; in the light emitting direction of the display panel, the GOA circuit is arranged opposite to the signal line and is electrically connected with the signal line through the conductive adhesive. The GOA circuit is arranged on the upper substrate, and the GOA circuit and the signal line are arranged oppositely, so that the realization of the ultra-narrow frame is facilitated.

Description

Display panel

Technical Field

The application relates to the technical field of display, in particular to the technical field of narrow-frame display, and particularly relates to a display panel.

Background

The GOA (Gate Driver on Array) technology is beneficial to the design of the narrow frame on the Gate Driver side of the display screen and the reduction of cost, and is widely applied and researched.

In response to the market demand, large Size (Size), high resolution and super Narrow Border (ENB) become the market trend, the resolution becomes higher, the Pixel Size (Pixel Size) is reduced, the space occupied by the GOA Layout (Layout) becomes larger, and how to realize the Narrow Border becomes a difficult issue to overcome.

Fig. 1A is a schematic diagram of a side Panel (Panel) of an array substrate, in which a GOA circuit is fabricated on a left frame 100 and a right frame 300 of a display area to realize a narrow frame; the lower bezel area 400, which is located below the display area 200, is provided with a flip-chip film 410, which is connected to the panel through a fan-out 420. As shown in fig. 1B, the two side frames shown in fig. 1A are formed by three major portions, namely, a GOA Circuit 700(GOA Circuit), a common signal line 600(GOA Busline), and a common electrode signal line 500(COM), which are distributed in parallel, wherein the GOA Busline has a relatively heavy resistance-capacitance load (RC Loading) according to the usage requirement of a large Size high resolution product, and the line width design needs to be considered, so the GOA Busline also needs to occupy a relatively large frame. The liquid crystal Cell (Cell) side is composed of frame glue 800(Seal) and a liquid crystal layer 900, the Seal is cured by Ultraviolet light (UV) irradiation, so that the Seal can be cured well only by having a certain requirement on the aperture ratio of the wiring of the array substrate (TFT) side, and the special requirement of the process is limited.

Disclosure of Invention

The application provides a display panel, and the GOA circuit of setting on array substrate of solution has taken the problem in great frame space.

In a first aspect, the present application provides a display panel, which includes a lower substrate and an upper substrate that are arranged to a cell and bonded by a conductive adhesive, wherein the lower substrate is an array substrate, and a liquid crystal layer located between the lower substrate and the upper substrate; the upper substrate is provided with a GOA circuit; the lower substrate is formed with signal lines; in the light emitting direction of the display panel, the GOA circuit is arranged opposite to the signal line, and the GOA circuit is electrically connected with the signal line through the conductive adhesive.

With reference to the first aspect, in a first implementation manner of the first aspect, the display panel is provided with a display area and frame areas oppositely arranged on two sides of the display area; the GOA circuit and the signal line are both located in the frame area.

With reference to the first aspect, in a second implementation manner of the first aspect, the signal line includes a common signal line and a plurality of gate driving lines, and the common signal line and the plurality of gate driving lines are disposed in a non-overlapping manner; the common signal line is correspondingly and electrically connected with the input end of the GOA circuit, and the plurality of grid drive lines are correspondingly and electrically connected with the output end of the GOA circuit.

With reference to the first implementation manner of the first aspect, in a third implementation manner of the first aspect, in the frame region, the upper substrate is formed with a plurality of first transparent electrodes, the lower substrate is formed with a plurality of second transparent electrodes, and the first transparent electrodes are electrically connected to the second transparent electrodes through conductive paste.

With reference to the second implementation manner of the first aspect, in a fourth implementation manner of the first aspect, the upper substrate includes an upper substrate, and a first metal layer, a first gate insulating layer, a first active layer, a second metal layer, and a first insulating layer sequentially formed on the upper substrate; a plurality of first through holes are formed on the first gate insulating layer, and the second metal layer is correspondingly connected with the first metal layer through the first through holes; a plurality of second through holes are formed in the first insulating layer, and the second metal layer is correspondingly connected with the first transparent electrode through the second through holes; the first transparent electrode is electrically connected with the conductive adhesive correspondingly.

With reference to the fourth implementation manner of the first aspect, in a fifth implementation manner of the first aspect, the lower substrate includes a lower substrate, and a third metal layer, a second gate insulating layer, and a fourth metal layer sequentially formed on the lower substrate; the second grid electrode insulating layer is provided with a plurality of third through holes, and the third metal layer is electrically connected with the second transparent electrode correspondingly through the third through holes; the second transparent electrode is electrically connected with the conductive adhesive correspondingly.

With reference to the fifth implementation manner of the first aspect, in a sixth implementation manner of the first aspect, the lower substrate further includes a second active layer located between the second gate insulating layer and the fourth metal layer, a second insulating layer covering the fourth metal layer, and a third insulating layer formed on the second insulating layer; wherein the second transparent electrode is positioned on the third insulating layer; the third via hole passes through the second insulating layer and the third insulating layer.

With reference to the sixth implementation manner of the first aspect, in a seventh implementation manner of the first aspect, the fourth via hole is formed in the second insulating layer and the third insulating layer; the fourth metal layer is electrically connected with the second transparent electrode through the fourth via hole.

With reference to the fifth implementation manner of the first aspect, in an eighth implementation manner of the first aspect, the common signal line includes a plurality of clock signal lines and at least one low potential signal line; the clock signal line and the low potential signal line are arranged on the third metal layer in a staggered mode.

With reference to the eighth implementation manner of the first aspect, in a ninth implementation manner of the first aspect, the plurality of gate driving lines are disposed on the third metal layer and are offset from the clock signal lines and the low potential signal lines.

The utility model provides a display panel sets up the GOA circuit at the upper substrate, and the GOA circuit corresponds electric connection through the signal line of conducting resin and infrabasal plate to the input signal and the output signal of transmission GOA circuit, and GOA circuit and signal line set up relatively in display panel's light-emitting direction, have effectively improved the problem that the GOA circuit setting took great frame on array substrate, do benefit to and realize super narrow frame.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1A is a schematic view of a structure of an array substrate-side display panel in a conventional technical solution.

FIG. 1B is a schematic view of the structure at A-A' in FIG. 1A.

Fig. 2A is a schematic structural diagram of a display panel according to an embodiment of the present application.

FIG. 2B is a schematic view of the structure at B-B' shown in FIG. 2A.

Fig. 2C is a schematic structural diagram shown in fig. 2B.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

As shown in fig. 2A and 2B, the present embodiment provides a display panel including a lower substrate 2 and an upper substrate 1 disposed to a cell and bonded by a conductive paste 3, and a liquid crystal layer between the lower substrate 2 and the upper substrate 1; the upper substrate 1 is formed with a GOA circuit 4; the lower substrate 2 is formed with signal lines 5; in the light emitting direction of the display panel, the GOA circuit 4 is arranged opposite to the signal line 5, and the GOA circuit 4 is electrically connected with the signal line 5 through the conductive adhesive 3.

Specifically, the GOA circuit 4 is disposed on the upper substrate 1, the lower substrate 2 sends a required input signal to the GOA circuit 4 through the signal line 5, and receives and transmits an output signal of the GOA circuit 4 through the signal line 5, thereby implementing the scanning driving of the array substrate; the conductive adhesive 3 plays a role in signal transmission between the upper substrate 1 and the lower substrate 2, so that the design of a Transfer Pad (Transfer Pad) for electrical connection can be saved, and the manufacturing time is saved; and moving GOA circuit 4 from lower base plate 2 to upper substrate 1, the region that GOA circuit 4 is located can carry out the coincidence overall arrangement with the region that signal line 5 is located, has effectively improved in the prior art frame width that public electrode signal line, public signal line and GOA circuit 4 parallel distribution lead to taking up in frame area 6, is favorable to realizing super narrow frame. The corresponding arrangement of the GOA circuit 4 and the signal line 5 can be, but is not limited to, that the projection area of the GOA circuit 4 and the projection area of the signal line 5 are overlapped on a certain plane.

The conductive adhesive 3 may be formed by adding a plurality of conductive gold balls 31 into the sealant, and the conductive gold balls 31 are isolated from each other by the sealant, so that the conductive gold balls 31 are electrically isolated from each other. In some embodiments, the conductive adhesive 3 may also be formed by adding a plurality of conductive silver balls in the sealant, and the conductive silver balls are isolated from each other by the sealant, so that the conductive silver balls are electrically isolated from each other.

As shown in fig. 2A, in some embodiments, the display panel may also include a lower frame region 8, the lower frame region 8 is provided with a flip chip film 81, and the fan-shaped outgoing line 82 is connected to the display panel.

As shown in fig. 2B, in one embodiment, the display panel is provided with a display area 7, and frame areas 6 disposed at two sides of the display area 7; the GOA circuit 4 and the signal line 5 are located in the frame area 6.

Specifically, in this embodiment, the frame areas 6 on both sides of the display area 7 are respectively provided with the common signal lines, the GOA buses and the GOA circuits 4 which are distributed in parallel, so that the GOA circuits 4 of the two frame areas 6 can be correspondingly disposed on the upper substrate 1, and the frame areas 6 on both sides can be narrowed simultaneously.

In one embodiment, the signal lines 5 include a common signal line and a plurality of gate driving lines, and the common signal line and the plurality of gate driving lines are arranged in a staggered manner; the common signal line is electrically connected to the input terminal of the GOA circuit 4, and the gate driving lines are electrically connected to the output terminal of the GOA circuit 4.

Specifically, the common signal line and the gate driving line are disposed in a staggered manner, which may include, but is not limited to, that when both are located in the same film layer, both may be distributed in parallel; if the two are located in different film layers, the two can be arranged in a non-overlapping mode in different surfaces. The common signal line is used for transmitting input signals such as a clock signal (CK) and a low potential signal (VSS) to the input end of the GOA circuit 4, and the gate driving line is used for transmitting the received gate driving signal output by the GOA circuit 4 to the thin film transistor of each pixel, so as to realize scanning driving of the array substrate. The non-overlapping arrangement may be, but is not limited to, that the projection position of the common signal line does not coincide with the projection positions of the plurality of gate driving lines.

As shown in fig. 2C, in one embodiment, in the frame region 6, a plurality of first transparent electrodes are formed on the upper substrate 1, a plurality of second transparent electrodes are formed on the lower substrate 2, and the first transparent electrodes are electrically connected to the second transparent electrodes through the conductive paste 3.

Specifically, in this embodiment, the common electrode signal line of the lower substrate 2 transmits the common electrode signal to the first transparent electrode 16 corresponding to the upper substrate 1 through the conductive adhesive 3, the first transparent electrode 16 is divided into a first transmission electrode of the frame region and a common electrode of the display region, the common electrode signal corresponds to the common electrode of the display region, and the transmission electrode of the frame region and the common electrode signal are not connected and only serve as a connection function for other signal transmission; similarly, the second transparent electrode 27 is divided into the second transmission electrode in the frame area and the pixel electrode in the display area, and the second transmission electrode 27 in the frame area is only used for connecting related signal transmission, so that the design or structure of the transfer area for transmitting the signals can be saved, and the manufacturing efficiency of the whole panel is improved.

As shown in fig. 2C, in one embodiment, the upper substrate 1 includes an upper base substrate 10, and a first metal layer 11, a first gate insulating layer 12, a first active layer 13, a second metal layer 14, and a first insulating layer 15 sequentially formed on the upper base substrate 10; a plurality of first via holes 17 are formed on the first gate insulating layer 12, and the second metal layer 14 is correspondingly connected with the first metal layer 11 through the first via holes 17; a plurality of second via holes 18 are formed on the first insulating layer 15, and the second metal layer 14 is correspondingly connected with the first transparent electrode 16 through the second via holes 18; the first transparent electrode 16 is electrically connected to the conductive adhesive 3 correspondingly.

Specifically, the first metal layer 11, the first gate insulating layer 12, the first active layer 13, and the second metal layer 14 are used to form a thin film transistor array of the GOA circuit 4, and provide necessary conditions for the fabrication of the GOA circuit 4 on the upper substrate 1, and the complete fabrication process of the GOA circuit 4 can refer to the fabrication process of the GOA circuit 4 on the array substrate. The gate driving signal output by the GOA circuit 4 originates from the second metal layer 14, and is sent to the corresponding first transparent electrode 16 through the plurality of second vias 18, and then is transmitted to the corresponding conductive adhesive 3, wherein each level of gate driving signal may be, but is not limited to, using an independent transmission channel; in the same way, the common signal is from the first metal layer 11, then is connected to the second metal layer 14 through the first via 17, then is connected to the first transparent electrode 16 through the second via 18, and then is sent to the corresponding conductive adhesive 3; the transmission process of the common electrode signal is similar to the transmission path of the common signal, and is not described in detail.

As shown in fig. 2C, in one embodiment, the lower substrate 2 includes a lower substrate 20, and a third metal layer 21, a second gate insulating layer 22, and a fourth metal layer 24 sequentially formed on the lower substrate 20; the second gate insulating layer 22 is provided with a plurality of third via holes 28, and the third metal layer 21 is correspondingly electrically connected with the second transparent electrode 27 through the third via holes 28; the second transparent electrode 27 is electrically connected to the conductive adhesive 3 correspondingly.

Specifically, the gate driving line is located in the third metal layer 21, and then connected to the corresponding second transparent electrode 27 through the third via 28, and then the second transparent electrode 27 is connected to the corresponding conductive adhesive 3, so that the gate driving signal output by the GOA circuit 4 in the upper substrate 1 can be transmitted to the corresponding gate driving line; similarly, the transmission path of the common signal line in the lower substrate 2 is the same as the transmission path of the signal in the gate driving line in the lower substrate 2, and each common signal line has a separate transmission path, so that separate transmission of the corresponding signal can be realized.

As shown in fig. 2C, in one embodiment, the lower substrate 2 further includes a second active layer 23 between the second gate insulating layer 22 and the fourth metal layer 24, a second insulating layer 25 covering the fourth metal layer 24, and a third insulating layer 26 formed on the second insulating layer 25; wherein the second transparent electrode 27 is located on the third insulating layer 26; the third via 28 passes through the second insulating layer 25 and the third insulating layer 26.

As shown in fig. 2C, in one embodiment, a fourth via 29 is formed in the second insulating layer 25 and the third insulating layer 26; the fourth metal layer 24 is electrically connected to the second transparent electrode 27 through the fourth via 29.

Specifically, the transmission process of the common electrode signal on the lower substrate 2 is such that the common electrode signal may originate from, but is not limited to, the fourth metal layer 24, then the common electrode signal is connected to the fourth via 29 through a wire in the fourth metal layer 24, then is connected to the second transparent electrode 27 through the fourth via 29, and the second transparent electrode 27 is connected with the corresponding conductive paste 3, thereby completing the transmission path of the common electrode signal between the upper substrate 1 and the lower substrate 2.

As shown in fig. 2C, in one embodiment, the common signal line includes a plurality of clock signal lines and at least one low potential signal line; the clock signal line and the low potential signal line are provided in the third metal layer 21 with a shift.

Specifically, the clock signal line is to transmit the clock signal of the lower substrate 2 to the GOA circuit 4 in the upper substrate 1, and the low potential signal line is to transmit the low potential signal of the lower substrate 2 to the GOA circuit 4.

As shown in fig. 2C, in one embodiment, a plurality of gate driving lines are disposed on the third metal layer 21 and are offset from the clock signal lines and the low potential signal lines.

In one embodiment, the upper substrate 1 is further provided with a black matrix in the frame region 6, and a projection area of the GOA circuit 4 overlaps or coincides with a projection area of the black matrix, so that an influence on a design aperture ratio can be reduced.

In one embodiment, the width of one side frame region 6 of the display panel processed by the above embodiments can be reduced from 5000 micrometers in the prior art to 1500 micrometers.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The display panel provided by the embodiment of the present application is described in detail above, and a specific example is applied to illustrate the principle and the implementation manner of the present application, and the description of the embodiment is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. The display panel is characterized by comprising a lower substrate and an upper substrate which are arranged opposite to each other and bonded through a conductive adhesive, wherein the lower substrate is an array substrate, and a liquid crystal layer is positioned between the lower substrate and the upper substrate; the upper substrate is provided with a GOA circuit; the lower substrate is provided with signal lines; in the light emitting direction of the display panel, the GOA circuit is arranged opposite to the signal line, and the GOA circuit is electrically connected with the signal line through the conductive adhesive.

2. The display panel according to claim 1, wherein the display panel is provided with a display area and frame areas oppositely arranged at two sides of the display area; the GOA circuit and the signal line are both located in the frame area.

3. The display panel according to claim 2, wherein the signal lines include a common signal line and a plurality of gate driving lines, and the common signal line is disposed to be offset from the plurality of gate driving lines;

the common signal line is electrically connected with the input end of the GOA circuit correspondingly, and the grid drive lines are electrically connected with the output end of the GOA circuit correspondingly.

4. The display panel according to claim 3, wherein in the frame region, the upper substrate is formed with a plurality of first transparent electrodes, the lower substrate is formed with a plurality of second transparent electrodes, and the first transparent electrodes are electrically connected to the second transparent electrodes through the conductive paste.

5. The display panel according to claim 4, wherein the upper substrate comprises an upper substrate base plate, and a first metal layer, a first gate insulating layer, a first active layer, a second metal layer, and a first insulating layer formed on the upper substrate base plate in this order;

a plurality of first via holes are formed on the first gate insulating layer, and the second metal layer is correspondingly connected with the first metal layer through the first via holes; a plurality of second through holes are formed in the first insulating layer, and the second metal layer is correspondingly connected with the first transparent electrode through the second through holes; the first transparent electrode is electrically connected with the conductive adhesive correspondingly.

6. The display panel according to claim 5, wherein the lower substrate comprises a lower substrate base plate, and a third metal layer, a second gate insulating layer and a fourth metal layer sequentially formed on the lower substrate base plate;

the second grid electrode insulating layer is provided with a plurality of third through holes, and the third metal layer is electrically connected with the second transparent electrode correspondingly through the third through holes; the second transparent electrode is electrically connected with the conductive adhesive correspondingly.

7. The display panel according to claim 6, wherein the lower substrate further comprises a second active layer between the second gate insulating layer and the fourth metal layer, a second insulating layer covering the fourth metal layer, and a third insulating layer formed on the second insulating layer;

wherein the second transparent electrode is located on the third insulating layer; the third via hole passes through the second insulating layer and the third insulating layer.

8. The display panel according to claim 7, wherein a fourth via is formed in the second insulating layer and the third insulating layer; the fourth metal layer is electrically connected with the second transparent electrode correspondingly through the fourth via hole.

9. The display panel according to claim 6, wherein the common signal line includes a plurality of clock signal lines and at least one low potential signal line; the clock signal line and the low potential signal line are arranged on the third metal layer in a staggered mode.

10. The display panel according to claim 9, wherein the plurality of gate driving lines are disposed in the third metal layer and are offset from the clock signal lines and the low potential signal lines.