KR20180018659A - Micro-LED display without transmission - Google Patents

Abstract

A light emitting diode-based display and a method of manufacturing such a display are described herein. In particular, the devices described herein include micro-LED 190 direct radiation technology and methods for manufacturing such devices directly on LED wafers. The improved device integrates a GaN layer 110 'on the silicon substrate 120 to create a device structure that allows for back contact through silicon and separate μ LED control, while delivering the μLED to another substrate, Avoid using.

Description

Micro-LED display without transmission

This application claims the benefit of U.S. Provisional Application No. 62 / 172,393, filed June 8, 2015, The contents of which are hereby incorporated by reference in their entirety.

Light-emitting diode-based displays and methods of such displays are described herein. In particular, the devices described herein include micro LED direct emission technologies and methods of fabricating such devices directly on top of LED wafers.

Light emitting diodes ("LEDs") are semiconductor light sources that emit light when a voltage of an appropriate electromotive force is applied across the leads of a diode. Generally speaking, the LED includes a chip of semiconductor material doped with impurities that produce a p-n junction. As with other diodes, the current flows easily from the p-side, i.e. from the anode to the n- side, i.e. the cathode, but not in the opposite direction. Charge-carriers (electrons and holes) flow from the electrodes with different potentials into the junction. When electrons meet holes, they recombine through luminescent recombination and emit energy in the form of photons by a process called electroluminescence.

The wavelength of the emitted light, and thus the color of light, depends on the band gap energy of the materials forming the p-n junction. In silicon or germanium diodes, electrons and holes are recombined by non-luminescent transitions, which usually do not produce optical emission, since they are indirect bandgap materials. Materials used for LEDs have a direct transition bandgap with energy corresponding to near infrared, visible or near ultraviolet light.

LEDs have many advantages over incandescent light sources, such as lower energy consumption, longer lifetime, improved physical robustness, smaller size, and faster switching. Light emitting diodes are used in various lighting applications. However, there is a need to continue to improve in terms of the design and functionality of the LED. For example, LEDs that are powerful enough for indoor lighting are still relatively expensive and require more sophisticated current and thermal management than compact fluorescent lamp light sources of equivalent power. To that end, LED technology has been continually expanded in a number of different ways. As the demand for performance increases for smaller size LEDs, there will be a need for continued improvement in efficiency, operating speed, spectral control, and scalability. With the reduction in size, manufacturing problems associated with device isolation and global planarization continue to increase.

The aspects described herein seek to address some of the problems described by providing methods for fabricating novel ultra-high-definition structures that do not require transferring mLEDs from the source and the novel μLED device structures.

A first aspect is a silicon substrate comprising at least one via having a conductive material therein; A structured GaN layer comprising at least one independent GaN element and a void space on the silicon substrate; An optional buffer layer between the silicon substrate and the GaN layer; An optional planarization layer on the silicon substrate or the optional buffer layer to fill the void space between the at least one independent GaN element; A transparent conductor over the GaN layer and the optional planarization layer; At least one wall element forming a well on the transparent conductor; A quantum dot material located within said well; And a transparent substrate on the wall element and the well, wherein the GaN layer or optional buffer layer is exposed to the conductive material through the via.

The second aspect is a. Removing at least a portion of the GaN to produce a structured GaN layer comprising at least one independent GaN element and a void space on the silicon substrate, starting from a silicon substrate coated with a GaN layer and optionally covered with a buffer layer step; b. Removing at least a portion of the silicon substrate beneath the at least one independent GaN element to form vias exposing the GaN or selective buffer layer; c. Inserting a conductive material in the via; d. Selectively inserting a planarization material in the void space on the silicon substrate; e. Forming a transparent conductor over the GaN layer and the optional planarization layer; f. Forming at least one wall element on the transparent conductor to create at least one well; g. Disposing a quantum dot material in the well; And h. And disposing or forming a transparent substrate on the wall element and the well.

Additional features and advantages will be set forth in part in the description that follows, and in part will be obvious from the description, or may be learned by practice of the embodiments described in the claims and the accompanying drawings, Will be.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide an overview or framework for understanding.

The accompanying drawings are included to provide a further understanding and are incorporated in and constitute a part of this specification.
Figs. 1A to 1G show a process which is embodied for forming built-in μLEDs. 1A illustrates in cross-section a GaN layer 110 on a silicon substrate 120 having an optional buffer layer 115 to produce a GaN-on-Si (GaN-on-Si) The regions 110A and 110B are the optional p-type and n-type regions of the GaN, as discussed herein. 1B shows a cross-section of a GaN-on-Si wafer 100 on which GaN 110 is selectively etched to produce isolations of GaN 110 '. The silicon 120 is etched at the bottom of the remaining GaN 110 'region to create a via 125 that allows access to the underside of the GaN 110' in the step shown in FIG. 1c. These vias 125 are then wired with a conductive material 130, as shown in FIG. 1d. In FIG. 1e, a planarization layer 140 is added around each GaN (110 ') region, and then a transparent conductor 150 is coated along the entire top of the device. Figure 1F illustrates the creation of a wall element 160 on the transparent conductor. Element 165 indicates that the wall element can have a much longer vertical dimension than the other components shown. 1G illustrates the formation of red, green, and blue or blue scattering quantum wells 180 in the voids formed by the wall elements 160 and then the wall elements 160 to create the μLED display 190. Finally, Lt; RTI ID = 0.0 > 160 < / RTI > and the QD wells 180.

Before the present materials, articles, and / or methods are disclosed or described, it should be understood that the aspects described below are not limited to specific compounds, methods of synthesis, or uses and, of course, they can be varied.

In this specification, and in the claims which follow thereafter, many terms which have to be defined will be referred to as having the following meanings:

Throughout this specification, unless the context requires otherwise, the terms "comprises", or variations such as "comprises" or "includes" refer to a finished product or stage, It is to be understood that this does not exclude any other finished product or step, or group of such other finished products or steps. Quot; comprise " or "comprise ", as used herein.

As used in this specification and the appended claims, the singular forms "a" and "the " include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "one quantum dot" includes a combination of two or more such quantum dots and the like.

"Optional " or" optionally " means that the subsequently described event or circumstance may or may not occur, and the detailed description includes instances where the event or circumstance occurs, It is meant to include cases.

Ranges may be expressed herein as from "about" one particular value and / or "roughly" to another specific value. When such a range is expressed, other aspects include from that one particular value and / or to the other specified value. Similarly, if values are expressed as approximations using a preceding term such as "about ", it is to be understood that the particular value constitutes another aspect. It should also be understood that the limits of each range are independent of the relationship to other limits as well as the relationship to other limits.

The < RTI ID = 0.0 > μLED &

The suns include novel μLED devices on GaN-on-silicon structures and methods of making such devices. The μLED devices embodied herein are capable of providing a very high-definition surface of the mLED on the substrate while providing both the isolation and / or support functions of the μLED devices and the point where the silicon structure is integrated within the device It is unique in the point. The designs described herein would be unacceptable in some traditional display applications because it would not be economically feasible to use such a large amount of LED material to fabricate a single display. However, in the case of near-eye displays, such as those that may be attractive in virtual reality applications, because of the magnification required for the human eye to resolve, the enormous density of the LED material can cause the high resolution required when the display is so close to the eye to provide.

1G, the LED includes a silicon substrate 120 including vias 125 having conductive materials 130 therein, a structured GaN layer on the silicon substrate, A transparent conductor, wall elements forming wells on the transparent conductor, quantum dots in the wells, and a transparent substrate on top of the wall elements and wells.

The silicon substrate 120 comprises single crystal or polycrystalline silicon, such as a silicon wafer, and may have any orientation or crystal structure suitable for GaN 110 and / or an optional buffer layer. For example, the silicon substrate 120 may have a combination of (100), (110), or (111) directions or (in the case of polycrystalline silicon) directions. In some embodiments, the silicon substrate 120 may be doped with a small amount of dopant. The dopant may include any element suitable for the LED element 190 in any amount, but in particular includes boron, phosphorus, arsenic, oxygen, or antimony having a content of about 10 ¹³ to about 10 ¹⁶ atoms / cm ³ can do.

The vias 125 in the silicon may have any size or shape that allows the device 190 to operate properly. 1C, based on the design of the device 190, the vias 125 are generally formed such that the silicon substrate 120 properly supports the GaN material 110, But does not allow the contact to exit the GaN layer 110. This is because it minimizes the likelihood of shorting and optimizes the use of conductive materials. In some embodiments, the vias are only slightly smaller than the footprint of the GaN micro LED and can be optimized for light extraction. However, if the optional planarization layer is present and it can act as an insulator, the size of the vias 125 may exceed the size of the GaN 110 in some areas or dimensions. In some embodiments, in order to optimize the use of the substrate 120, the vias may be in the in-plane (i.e., not thickness) dimension in their shortest direction of about 1 [mu] m to about 50 [ .

Once formed, the vias are filled with a conductive material 130. The conductive material 130 may be a metal or a metal oxide, and may act as a reflector, particularly in the case of metal, to improve the light output from the device 190. The metals and metal oxide materials that can be used as the conductive material 130 may include Al, Au, Cu, Ag, Pt, and the like. In some embodiments, a mirror layer may be coated on the lower surface of the GaN prior to embedding the via with another conductor such as a copper paste. In part this is due to the absorbency of the silicon. Silicon itself is highly absorbing so that manufacturers manufacturing LEDs based on GaN-on-Si separate the GaN from the original wafer, form a mirror layer on top of GaN, and bond the other wafers.

In some embodiments, there is an optional buffer layer 115 between the silicon and GaN layers. Due to the lattice difference between the GaN 110 and the silicon 120, it may be difficult to grow GaN on the silicon. The buffer layer 115 includes a material that bridges the lattice difference by minimizing lattice mismatch between the GaN 110 and the silicon 120. The intermediate may be achieved by using a material having a crystalline or amorphous structure, which has a structure that changes or varies structurally or compositionally when transitioning from the facing surface of silicon to the facing surface of GaN. Buffer layer 115 can include, for example, the InGaN, AlGaN, Gd ₂ O _3, Ga ₂ O _3, AlN and Si ₃ N _4. The buffer layer 115, if present, may be etched away to form the via, and may remain if it is conductive. Figure 1C shows an optional buffer layer 115 etched away for clarity.

The GaN layer 110 includes GaN, and may further include dopants such as aluminum or indium. In fact, in some embodiments, the GaN layer varies compositionally as it moves away from the silicon layer or buffer layer. In some embodiments, the GaN layer is n-type in proximity to or adjacent to the silicon layer / buffer layer (region 110B in FIG. 1A), doped with silicon or oxygen, or other material that is made into n- Lt; / RTI > On the other hand, in the region on the opposite side or adjacent thereto, the GaN is doped with another material that is p-type and made into Mg or p-type (region 110A in FIG. 1A). The GaN layer is etched starting from the surface-exposed surface that is furthest from the silicon and then proceeding down toward the silicon layer and the silicon surface. The GaN layer 110 generally has a thickness on the order of about 1 micron to about 100 microns and is spaced enough to prevent cross-talk or shorting between the etched GaN elements 110, In embodiments, it can be etched to any suitable shape with about 500 nm to about 5 탆 or more.

The optional planarization layer 140 acts as an insulator to insulate the sidewalls of the GaN and, in some embodiments, can act as a reflector. The planarization layer 140 may include any insulating material that can be easily coated on the substrate and does not cause problems in operation of the device. In some embodiments, the planarization layer 140 is an optionally photopolymerizable organic or inorganic polymer. In embodiments where the planarization layer 140 also serves as a reflector, the planarization layer 140 may further comprise organic or inorganic particles such as nano- or microparticles that reflect or scatter light.

The transparent conductive material 150 is an electrically conductive and optically transparent thin film and may be a transparent conductive oxide (for example, ITO, FTO, doped ZnO), an organic or inorganic conductive polymer (for example, PEDOT, PEDOT: PSS ), A conductive transfer film, a metal grid, carbon nanotubes, nanowires, or graphene.

The quantum dot elements 180, as used herein, include nanocrystalline semiconductor materials exhibiting quantum mechanical properties. QD materials that may be used in the embodiments described herein generally include, without limitation, any of the known QD materials. The size, composition, and amount of QD elements 180 used in each well may be determined by the capabilities of the ordinary skilled artisan and may be varied for application. QD, which can be used are, for example, CdSe, CdS, ZnS, CdS _x Se _1-x / ZnS, InP / ZnS, PbS, such as core-shell comprises, or alloys QD-type core. The QD elements 180 may further comprise polymers or other carriers or support materials with the QDs in the wells. Depending on the application, the QD elements may have the same or different emission colors and may be structured or aligned to emit such colors in a particular arrangement. The QD elements 180 shown in FIG. 1G may have a repeating pattern of different colors, but may be arranged differently without affecting the embodiments described herein.

Similar to the optional planarization layer, the wall element 160 not only serves to create wells for the QD materials, but also serves to isolate the wells from each other and, in some embodiments, . The wall element 160 can include any nonconductive material that can be developed into a well-like structure, coated on the transparent conductor, and free from problems with the operation of the device. In some embodiments, the wall element 160 is an optionally photopolymerizable organic or inorganic polymer. In embodiments in which the wall element 160 also acts as a reflector or scatterer, the wall element 160 may further comprise organic or inorganic particles such as nano- or microparticles that reflect or scatter light have.

Referring again to FIG. 1G, the transparent substrate 170 may comprise a transparent glass, glass ceramic, polymer, or crystalline material that serves to encapsulate the QD elements. The transparent substrate 170 may be a thin, thin, and / or flexible material, such as a flexible glass substrate having a thickness of up to 300 microns. In some embodiments, the transparent substrate 170 may be further coated with any number of films such as anti-reflective, anti-fingerprint, antimicrobial, and the like. Optionally, one or both sides of the transparent substrate 170 may be designed to scatter light through scattering films or by a substrate having a roughened or non-planar surface.

Methods

Typical competitive approaches to micro LED displays, micro LEDs, are transferred from the source wafer to a separate display backplane. Transferring μ LEDs from the forming substrate can be a costly as well as difficult process. A disadvantage of not delivering μ LEDs is that the forming substrate can not be reused, while the transfer approach allows for potentially multiple displays from one wafer. However, some applications, such as, for example, a virtual reality head mounted display, may find that the cost of the entire wafer per display is important because of the extremely high resolution requirements for VR. These μLED designs and processes enable high-resolution μLEDs to be formed directly on the wafer without the need to remove or transfer silicon.

Conventional methods for forming μ LEDs on silicon involve removing the silicon substrate by etching. The proposed invention selects selectively through the patterned photoresist rather than removing the entire substrate. Selective removal of the substrate provides the desired access to contact the bottom of the n-GaN layer. This implementation is important to the proposed invention. Because the present invention requires creating through-silicon vias to process each subpixel (with a common transparent electrode on the front side) from behind. Unlike sapphire, which is traditionally used for LED formation, silicon can be easily etched.

One embodiment of the process described herein is illustrated in Figures 1A-Ig. Referring to FIG. 1A, an optional buffer layer 115 is grown or formed on a silicon wafer 120. The buffer layer 115 may comprise known precursors such as NH ₃ and Al or alternative components through known methods including molecular beam epitaxy (MBE), chemical vapor deposition (CVD) . The GaN layer 110 is then coated onto the buffer-coated silicon substrate 120 to a desired thickness through known means including MBE, CVD, hydride vapor phase epitaxy, metal organic vapor phase epitaxy, do. In some embodiments, the GaN layer 110 is doped in such a way that the GaN layer progresses from the n-type to the p-type as the silicon 120 or the optional buffer layer 115 is further away.

Referring now to FIG. 1B, the GaN 110 and, optionally, the optional buffer layer 115 may be etched using etch techniques and masks known in the art such as wet etching or dry etching, and silicon tetrachloride, Etched using etchants such as acid, peroxide, and laser-assisted etch to form a GaN structure 110 'comprising individual GaN elements of any desired shape, such as columns, cubes, cylinders, pyramids, ). ≪ / RTI > The GaN layer is etched starting from the surface-exposed GaN surface furthest from the silicon and then proceeding down toward the silicon layer and the silicon surface.

Referring to FIG. 1C, the silicon 120 and, optionally, the optional buffer layer 115 may be etched using etch techniques and masks known in the art, such as wet etch or dry etch, The via 125 may be etched using etchants such as copper, copper, copper, copper, copper, copper, copper, copper, The silicon 120 is etched starting from the surface-exposed silicon surface furthest from the GaN and then proceeding down toward the GaN surface and the GaN structure 110 '. The vias 125 may have any desired shape and may mimic the shape of the GaN structures 110 'at their top. This step exposes the bottom surface of the GaN structures 110 'to enable the formation of a circuit through the silicon substrate.

Etching of the silicon may be followed by known processes such as those shown in FIG. 1D, including vapor deposition processes under vacuum, films, pastes, liquid coating, blading, The conductive material 130 may be inserted into the via 125. For example, a reflective metal layer may be deposited on the GaN layer through the vias, and then a copper paste may be deposited which is used to fill the vias and form the contacts. As described above, the conductive material 130 may include conductive metals and metal oxides such as Al, Au, Cu, Ag, Pt, and the like.

FIG. 1E illustrates the step of selectively coating the GaN-on-silicon substrate 100 with a planarization layer 140. The planarization layer 140 is designed to fill the voids around the GaN structures 110 'without coating the upper surface, which is the contact contact for the transparent conductor 150. The planarization layer 140 may be disposed on the device through mechanical means or chemical means including vapor deposition, chemical reaction, blading, and the like.

Referring again to FIG. 1e, a transparent conductor 150 is then disposed over the GaN 110 'and the optional planarization layer 140. May be deposited as films, liquids, or vapors, depending on the transparent conductor, and then allowed to settle or crosslink, or may undergo other chemical or physical processes to attach and settle into the GaN and / or planarization layer . The transparent conductor may also be carried on a transparent film.

With the formation of the transparent conductor 150, the wall elements 160, as shown in FIG. 1F, can be developed into a structure such as a well and coated on the transparent conductor, May be formed on the transparent conductor from any nonconductive material that will not cause problems in operation. In some embodiments, the wall element 160 is formed through polymerization, lithography, or the like.

Referring to FIG. 1G, once the wall elements 160 are formed, materials are placed in the wells, and then the wells and wall elements 160 are encapsulated under the transparent substrate 170. The resulting device 190 is a μLED using a forming substrate and integrated with a forming substrate, as well as using both micro-scale forming techniques and LED techniques, as well as the properties of QDs.

While the embodiments herein have been described with reference to specific aspects and features, it should be understood that these embodiments are merely illustrative of the desired principles and applications. It is, therefore, to be understood that numerous modifications may be made to the illustrated embodiments without departing from the scope and spirit of the appended claims, and that other arrangements may be devised.

Claims (23)

A silicon substrate including at least one via having a conductive material therein;
A structured GaN layer comprising at least one independent GaN element and a void space on the silicon substrate;
A transparent conductor over the GaN layer and the optional planarization layer;
At least one wall element forming a well on the transparent conductor;
A quantum dot material located within said well; And
A transparent substrate on the wall element and the well;
Wherein the GaN layer or an optional buffer layer is exposed to the conductive material through the vias. The method according to claim 1,
Wherein the structured GaN layer is adjacent to the silicon substrate and varies in composition as a function of distance from the silicon layer. 3. The method of claim 2,
Wherein the structured GaN layer has an n-type on a surface closest to the silicon layer and a p-type on a surface remote from the silicon layer. 4. The method according to any one of claims 1 to 3,
Wherein the structured GaN layer is doped with oxygen, silicon, magnesium, aluminum or indium. 5. The method according to any one of claims 1 to 4,
Wherein the structured GaN layer has a thickness of about 1 [mu] m to about 100 [mu] m. 6. The method according to any one of claims 1 to 5,
Wherein the device further comprises a planarization layer on the silicon substrate. The method according to claim 6,
Wherein the planarization layer comprises a photopolymerizable organic or inorganic polymer that optionally comprises nano- or microparticles. 8. The method according to any one of claims 1 to 7,
RTI ID = 0.0 > 1, < / RTI > wherein the device further comprises a buffer layer. 9. The method according to any one of claims 1 to 8,
Wherein the device further comprises a buffer layer between the silicon substrate and the GaN layer. 10. The method according to claim 8 or 9,
The buffer device is characterized in that it comprises the _{InGaN, AlGaN, Gd 2 O 3} , Ga 2 O 3, AlN or Si ₃ N _4. 11. The method according to any one of claims 1 to 10,
The quantum dot material is CdSe, CdS, ZnS, CdS _x Se _1-x / ZnS, InP / ZnS, PbS, or a core-element characterized in that it comprises a shell, quantum dots or an alloy-type core. The method according to any one of claims 1 to 11,
Characterized in that the wall element comprises a photopolymerizable organic or inorganic polymer optionally comprising nano- or microparticles. 13. The method according to any one of claims 1 to 12,
Wherein the transparent substrate comprises glass, glass ceramic, polymer, or crystalline material. 14. The method according to any one of claims 1 to 13,
Wherein the device further comprises a fill for burying the at least one independent GaN element and the void space on the silicon substrate. 15. The method according to any one of claims 1 to 14,
Wherein the silicon substrate comprises monocrystalline or polycrystalline silicon optionally substituted with boron, phosphorus, arsenic, oxygen, or antimony in an amount of 10 ¹³ to 10 ¹⁶ atoms / cm ³ . 16. The method according to any one of claims 1 to 15,
Wherein the vias are about 1 [mu] m to about 50 [mu] m in their shortest direction in planar dimensions. 17. The method according to any one of claims 1 to 16,
Wherein the via comprises a conductive material. 18. The method of claim 17,
Wherein the conductor material comprises gold, aluminum, silver, copper, or platinum. 19. The method according to any one of claims 1 to 18,
Characterized in that the device comprises a micro-light emitting diode. 20. A method of manufacturing a device according to any one of claims 1 to 19,
a. Removing at least a portion of the GaN layer from the silicon substrate coated with a GaN layer and optionally covered with a buffer layer to produce a structured GaN layer comprising at least one independent GaN element and a void space on the silicon substrate ;
b. Removing at least a portion of the silicon substrate below the at least one discrete GaN element to form a vias exposing the GaN or selective buffer layer;
c. Inserting a conductive material in the via;
d. Forming a transparent conductor on the GaN layer;
f. Forming at least one wall element on the transparent conductor to create at least one well;
g. Disposing a quantum dot material in the well; And
h. Disposing or forming a transparent substrate on the wall element and the well;
≪ / RTI > 21. The method of claim 20,
Further comprising selectively inserting a planarization layer in the void space on the silicon substrate. 22. The method according to claim 20 or 21,
Wherein the buffer layer is formed by molecular beam epitaxy or chemical vapor deposition. 23. The method according to any one of claims 20 to 22,
Wherein removing at least a portion of the GaN layer comprises etching the GaN through silicon tetrachloride, base, acid, peroxide, or laser-assisted etching.

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