CN117038696A - Multi-stage light-emitting branch nanowire light-emitting device and preparation method thereof - Google Patents

Multi-stage light-emitting branch nanowire light-emitting device and preparation method thereof Download PDF

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CN117038696A
CN117038696A CN202311008754.7A CN202311008754A CN117038696A CN 117038696 A CN117038696 A CN 117038696A CN 202311008754 A CN202311008754 A CN 202311008754A CN 117038696 A CN117038696 A CN 117038696A
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nanowire
light emitting
tree
emitting device
light
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张运炎
张林君
查超飞
程志渊
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Zhejiang University ZJU
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Zhejiang University ZJU
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

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Abstract

The application discloses a multi-level branch nanowire light-emitting device and a preparation method thereof, wherein the multi-level branch nanowire light-emitting device comprises at least one tree-shaped nanowire which grows on an active region of a CMOS device or a silicon substrate, the tree-shaped nanowire comprises a trunk nanowire and at least one branch nanowire connected to the trunk nanowire, and the branch nanowire comprises a plurality of light-emitting regions. The technical bottleneck in the aspect of miniaturization of pixel particles is solved, so that the problems that the reality of a picture is seriously affected by serious particle feeling, grids, insufficient brightness contrast and the like of a VR picture can be relieved by a single chip. Therefore, the display device manufactured by the semiconductor adopting the technology has the advantages of ultrahigh pixel density, small volume, light weight, low power consumption, high luminous brightness, large portability, stable color temperature, long service life, realization of full color/single color and the like.

Description

Multi-stage light-emitting branch nanowire light-emitting device and preparation method thereof
Technical Field
The application belongs to a semiconductor light-emitting device, and particularly relates to a multi-stage light-emitting branch nanowire light-emitting device and a preparation method thereof.
Background
With the application and development of artificial intelligence in modern society, the acquisition, storage, transmission, processing and output of information are increasingly important. In terms of information acquisition, visual information is the primary way humans obtain outside world information. Currently, liquid Crystal Displays (LCDs) and organic electroluminescent displays (OLEDs) are dominant in the market, and they are mainly applied to the fields of mobile televisions, computers, etc., but the pursuit of display performance is endless, especially in applications such as Virtual Reality (VR), augmented Reality (AR), and ultra-large screen display in recent years. However, there are many problems in display, and the core problem is that the display fineness of the display screen built in the VR is not high. Most displays of VR devices currently exist along with existing LCD or OLED screens, both of which present a problem in terms of pixel particle miniaturization. Liquid crystal particles are sufficient in the existing medium-long distance application, but are obviously not fine enough in the design of VR (virtual reality) such as ultra-short distance and enlarged pixels, and OLED (organic light emitting diode) has difficulty in further shrinking due to the principle problem, so that a VR picture seen by people can have serious particles, grids and insufficient brightness contrast, and the reality of the picture is seriously affected.
Disclosure of Invention
The embodiment of the application aims to provide a multi-stage light-emitting branch nanowire light-emitting device and a preparation method thereof, so as to solve the technical bottleneck in the aspect of miniaturization of pixel particles, and enable a single chip to alleviate the problems that a VR picture has serious particle feeling, grid, insufficient brightness contrast and the like, and seriously affects the picture reality.
The application adopts the following technical scheme:
in a first aspect, embodiments of the present application provide a multi-level branched nanowire light emitting device comprising at least one tree-structured nanowire grown on an active region or silicon substrate of a CMOS device, the tree-structured nanowire comprising a backbone nanowire and at least one branched nanowire connected to the backbone nanowire, the branched nanowire comprising a plurality of light emitting regions.
The application directly integrates the Si-based CMOS device or the common silicon substrate with the multilevel luminescence tree-shaped structure nanowire. The design designs different quantum wells or quantum dots and the combination of the quantum wells and the quantum dots through the multi-layer branch nanowire of the nanowire with the tree structure, realizes a plurality of luminous points, realizes miniaturization of pixel particles and obtains a high-precision nanowire luminous device. The application does not need a huge transfer technology, does not need additional leads or welding spots to connect the array and the circuit, breaks through the problem of integration of devices and circuits, and has the advantages of ultrahigh pixel point, high brightness, high contrast, small volume, low power consumption, independent driving, convenience for portable use and the like.
The NLED emits light from the micro-sized nanowires, and under the condition that the process meets the requirements, fine display can be realized by designing the directions of the branched nanowires. That is, the smallest pixel particles that can be achieved are finer than those of Micro-LEDs currently popular, and the characteristics of high brightness and the like also lead to better contrast and better image effects. In terms of energy consumption, NLED is naturally low in power consumption, so that the NLED is excellent in energy consumption performance when applied to equipment such as VR helmets, and is excellent in cruising, heating and the like.
The tree-shaped nanowire can be integrally grown in an active area of a CMOS device, high integration of a circuit system such as a driving circuit and a control circuit and a light emitting array is realized, and the tree-shaped nanowire can also be grown on a common silicon substrate and is connected with other control circuits. The CMOS device substrate of the present application is preferably a Si (100) substrate.
Optionally, the light-emitting area at least includes a light-emitting wavelength, and the light-emitting area can be designed according to the color distribution and the requirement of the actual pixel point.
Optionally, the CMOS device includes more than two Si (100) MOS devices, at least one of which is an independent control unit. The MOS device can be divided into an N-channel enhancement type, an N-channel depletion type, a P-channel enhancement type and a P-channel depletion type, and comprises a source electrode, a drain electrode and a grid electrode.
Optionally, the active region of the MOS device is grown with a single or multiple tree-structured nanowires. For a MOS comprising a plurality of tree-shaped structure nanowires, adjacent tree-shaped structure nanowires in one MOS control unit can be made of homogeneous or heterogeneous materials, and the tree-shaped structure nanowires of the adjacent MOS control units can be distributed in a homogeneous or heterogeneous material arrangement. By the design of the nanowire material, a single-color or multi-color full-color luminous array is realized, and the colors can cover red, orange, yellow, green, cyan, blue, purple, white and other multi-color system colors.
Optionally, the tree-structured nanowires and the silicon substrate are made of heterogeneous materials. The tree-structured nanowire material adopts a semiconductor material system, so that the ultra-long practical service life, stable luminous efficiency and stable luminous color of the luminous array are realized. And the tree-shaped structure nanowires and the silicon substrate are made of heterogeneous materials, so that the limitation of single color of a light-emitting array on the silicon substrate is broken through.
Alternatively, the trunk nanowire and the branch nanowire may be homogeneous or heterogeneous materials. Each level of branched nanowires may be of homogeneous or heterogeneous material from branched nanowire to branched nanowire. And regulating and controlling according to the color of the luminous array.
Optionally, the light emitting regions are arranged radially or axially along the nanowire. The number of the luminous areas can be more than 50 through controllable synthesis of the nanowires, and is far higher than the luminous number of the thin film luminous array, so that the luminous brightness of the nanowire luminous array can be adjusted to be high.
Optionally, the light emitting region of the present application is a PN junction and a structure including an interlayer, such as a p-i-n junction. The PN junction may be a homojunction, a Single Heterojunction (SH), a Double Heterojunction (DH).
Optionally, the nanowire PN junction region is formed by a quantum well, a quantum dot or a combination of the quantum well and the quantum dot.
Alternatively, each segment of the branched nanowire may be segmented, partially segmented, or globally and uniformly controlled.
In a second aspect, the present application further provides a method for preparing the multi-stage branched nanowire light emitting device, at least comprising: preparing nano wires on a silicon substrate and constructing a CMOS circuit; the sequence of the two links can be adjusted according to the actual working condition;
the preparation method of the nanowire on the silicon substrate comprises the following steps:
nanowires are grown on a Si (111) substrate or a Si (100) substrate.
In some embodiments of the application, the specific process of CMOS circuit construction is as follows:
1) Depositing a first layer of photoresist;
2) Masking, exposing and etching to form an opening structure;
3) Stripping the first photoresist layer;
4) Filling a first insulating medium in the opening to form a shallow trench isolation structure;
5) Sequentially depositing a first insulating layer, a first conductive layer and a second photoresist layer;
6) Masking, exposing and etching to form a grid electrode of the MOS device;
7) Stripping the second photoresist layer;
8) Depositing a third layer of photoresist;
9) Exposing and photoetching a mask to form regions of the source electrode and the drain electrode of the MOS device to be doped;
10 Ion implantation is carried out to form a source electrode and a drain electrode of the MOS device;
11 Stripping the third layer of photoresist;
12 Depositing a fourth layer of photoresist;
13 Mask exposure, lithography exposing the source or drain of the MOS device (without the position of the tree structured nanowire array);
14 Depositing a second conductive layer and etching the second conductive layer to form a metal contact;
15 Removing the fourth photoresist layer;
16 Deposition of fifth layer photoresist
17 Mask exposure, lithography exposing the source or drain of the MOS device (the position of the tree structured nanowire array);
18 Depositing a third conductive layer and etching the third conductive layer to form a metal contact;
19 The fifth layer photoresist is removed.
In some embodiments of the application, the tree-structured nanowires may be grown vertically on the CMOS, including but not limited to, the following:
1) Depositing a first photoresist;
2) Masking, exposing and etching to form an opening structure;
3) Depositing a mask material;
4) Stripping the first photoresist, wherein the mask material only exists at the original opening structure position;
5) The nanowire is grown in the areas without masking material (the areas without masking material correspond to the source or drain of the MOS device);
6) The masking material is stripped.
Or, the constrained channel directional growth tree-shaped structure nanowire formed by the tree-shaped structure nanowire on the silicon substrate is specifically as follows:
1) Depositing a first layer of photoresist;
2) Masking, exposing and etching to form an opening structure;
3) Depositing a mask material;
4) Depositing a second layer of photoresist;
5) Masking, exposing and etching the mask material area to form at least one constraint channel;
6) The second layer of photoresist is stripped.
The first insulating medium and the mask material are SiO 2 、SiO x 、Si 3 N 4 、SiN x 。
The first insulating layer is silicon dioxide, high k material, two-dimensional material or a mixed layer between the two materials. The first conductive layer is made of metal gate materials such as TiN and TaN or doped polysilicon.
The second and third conductive layers are made of Cu, al, ti, au metal conductive materials.
In certain embodiments of the present application, the tree-structured nanowire growth method is etching, hydrothermal self-assembly, epitaxial growth, including MOCVD, LPCVD, MBE, and the like. And (3) normally growing a trunk nanowire array, then performing catalytic droplet sputtering on the classified nanowire nucleation points of the trunk nanowires, and performing classified nanowire growth on the nucleation points.
The nanowire material is a semiconductor of Si, ge, oxide, II-IV or III-V material.
The application has the beneficial effects that:
the multi-stage branch nanowire provided by the application is integrated on a silicon substrate to form a nanowire light-emitting device, so that the problem that the display fineness of a display screen built in Virtual Reality (VR) is not high, the technical structure of each stage of branch nanowire light-emitting array for realizing independent control on the silicon substrate is provided, the technical bottleneck in the aspect of miniaturization of pixel particles is solved, and the problems that the serious particle sense, grid, brightness contrast ratio and the like of a VR picture seriously influence the picture reality are solved by a single chip. Therefore, the display device manufactured by the semiconductor adopting the technology has the advantages of ultrahigh pixel density, small volume, light weight, low power consumption, high luminous brightness, large portability, stable color temperature, long service life, realization of full color/single color and the like. Moreover, the high integration of the CMOS integrated circuit and the light emitting array greatly simplifies the system of the nanowire display device, reduces the production cost and has commercial prospect.
Drawings
FIG. 1 is a schematic diagram showing the connection between an active region and an overall metal electrode of a CMOS device with integrated growth of a plurality of nanowires with independent tree structures in an embodiment of the present application; wherein (a) is a side view and (b) is a top view;
FIG. 2 is a schematic diagram of a silicon substrate grown simultaneously with a plurality of independent tree-structured nanowire arrays (each segment of a branched nanowire can be controlled in a segmented, partially segmented or integrally unified manner) according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a tree-structured nanowire array grown silicon substrate in an embodiment of the present application;
FIG. 4 is a schematic radial structure of a tree-structured nanowire according to an embodiment of the present application; wherein (a) is a side view, and (b), (c), (d) and (e) are top views of different light-emitting area structures;
FIG. 5 is a schematic axial structure of a tree-structured nanowire according to an embodiment of the present application;
FIG. 6a is a schematic diagram of a mask process for a silicon substrate according to an embodiment of the present application;
fig. 6b is a schematic diagram of a source region and a drain region of a MOS transistor according to an embodiment of the application;
fig. 6c is a schematic diagram of a MOS transistor according to an embodiment of the present application;
FIG. 6d is a schematic diagram of growing nanowires and filling a protective layer on the MOS in an embodiment of the application;
fig. 6e is a schematic diagram of the fabrication of a nanowire array electrode according to an embodiment of the present application.
The semiconductor device comprises a silicon substrate 1, a doped region 2, a source region 3, a drain region 4, a gate dielectric layer/shallow groove isolation structure 5, a gate electrode 6, an electrode 7, a filling material 8, a tree-shaped structure nanowire 9, an ITO transparent electrode 10, an n-type region 11, a light emitting layer 12/13/14 and a p-type region 15.
Detailed Description
The application will be further described with reference to the drawings and the specific examples.
The drawings are for illustrative purposes only and are not to be construed as limiting the present patent; for the purpose of better illustrating the embodiments, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the actual product dimensions; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationship depicted in the drawings is for illustrative purposes only and is not to be construed as limiting the present patent.
As shown in fig. 1-2, a CMOS integrated, ac driven active addressing NLED micro-display device comprises a light emitting component and a CMOS device, wherein the CMOS device comprises four types of MOS cells ABCD, and the MOS device comprises a source region 3, a drain region 4, and a gate region comprising a gate dielectric layer 5 and a gate electrode 6 as is known in the art. The source region 3 and the drain region 4 are both active regions according to the application; the Nano LED tree-shaped structure nanowire/Nano LED tree-shaped structure luminous array grows in the source region 3 or the drain region 4. The shallow trench isolation structure 5 serves as an isolation layer for each MOS group in the MOS circuit.
The size of each MOS can be regulated and controlled according to the existing integration process, each MOS can be independently controlled through a grid electrode of each MOS, so that the MOS and the integrated growth nanowire become an independent pixel point, and each pixel can be LEDs with different colors and has the functions of independently driving and emitting light beams by alternating voltage.
In fig. 1, class a and class B MOS are NMOS, having N channels; the MOS of the C type and the D type is PMOS and provided with a P channel. The N-type substrate is a Si (100) substrate doped with pentavalent elements such as arsenic, phosphorus, antimony and the like, and the P-type substrate can be a Si (100) substrate doped with trivalent elements such as boron and the like.
Fig. 2 is a MOS light emitting cell, which may be a class B/C MOS device and a tree-structured nanowire array 9 self-assembled to grow in the active region of the MOS device, and shows that each segment of the branched nanowire may be controlled in segments, or in whole. FIG. 3 is a schematic diagram of the growth of a tree-structured nanowire array. The MOS device adopts a silicon substrate 1 as a (100) crystal face. The nanowire light-emitting array can be composed of AlGaAs, inGaAsP, gaP, gaAsP, alGaInP, inGaN, gaN, siC and other materials and contains single or multiple quantum wells, quantum dots or pure single material structures. The nanowire surface is coated with passivation layers that separate the nanowire and nanowire from other materials and protect the device from the external environment. In fig. 2, the filling material 8 may encapsulate and protect the device. The electrode 7 is made of a metal material, and the electrode 10 is made of a transparent ITO material and is used as a connecting part of the tree-shaped nanowire branches and the electrode 7. V of the multi-level branch nanowire of the tree-shaped structure nanowire is achieved by controlling the voltage of the top electrode of the multi-level branch nanowire DS Differently, form V DS1 、V DS2 、V DS3 、V DSx Etc. by V G And V DSx The independent control of the multi-level branch nanowires of the tree-shaped structure nanowire is realized, and the multi-level control effect can be realized. It should be noted that the B unit is two independent branch nanowires, which can be extended into two tree-structured nanowire arrays.
For the above tree structured nanowire 9, the following five cases are possible:
1) The contact interface between the source electrode or the drain electrode on the surface of the CMOS device and the single (multiple) tree-shaped structure nanowire in the area is p-type material which is of a first type;
2) The contact interface between the source electrode or the drain electrode on the surface of the CMOS device and the single (multiple) tree-shaped structure nanowire in the area is of a second type, wherein the n-type material is the same;
3) The contact interface between the source electrode or the drain electrode on the surface of the CMOS device and the single (multiple) tree-shaped structure nanowire in the area is p-n type material which is of a third type;
4) The contact interface between the source electrode or the drain electrode on the surface of the CMOS device and the single (multiple) tree-shaped structure nanowire in the area is n-p type material which is of a fourth type;
5) The single contact interface between the source electrode or the drain electrode of the CMOS device surface and the plurality of tree-shaped structure nanowires in the region is p-type, n-type, p-n-type and n-p-type materials.
The whole nanowire light-emitting array can be arranged and combined by the five types or the derivative types of the five types.
The branched nanowires of the tree-structured nanowires comprise at least one light emitting region, and in certain preferred embodiments more than two light emitting regions. The light-emitting region refers to a light-emitting region of the nanowire, and can emit light for the whole branch nanowire or locally emit light for the branch nanowire. Either wholly or partially illuminated, may be comprised of one or more illuminated regions. Each light emitting region is typically carrier radiation recombination light emission (light emission is achieved based on electron and hole recombination); the carrier radiation composite luminescence can be realized based on the intrinsic material luminescence of the nanowire material or the PN junction of the nanowire and the structure luminescence containing the interlayer, so the application is called an intrinsic luminescence area of the nanowire or a PN junction area of the nanowire.
Materials for realizing the luminescence of the application include inorganic materials and organic materials. The inorganic material is typically a semiconductor material such as Si, ge, oxide, III-V, or the like. The organic electroluminescent materials can be divided into two major classes of small molecules and high molecules according to the difference of molecular weights of the organic luminescent materials. The small molecular OLED material takes organic dye or pigment as a luminescent material, and the high molecular OLED material takes conjugated or non-conjugated high polymer (polymer) as a luminescent material, and the typical high molecular luminescent material is PPV and derivatives thereof.
The above-described PN junction and sandwich-containing structures may be composed of single or multiple quantum well or quantum dot structures.
In the embodiment of the present application, the manufacturing process of the semiconductor device shown in fig. 3 and 4 will be described by taking InGaN/GaN material as an example.
The radial PN light-emitting structure of fig. 4 (a) is composed of n-type GaN (n-type region 11), inGaN/GaN quantum well (light-emitting layer 12) and p-type GaN (p-type region 15) grown from inside to outside, wherein the growth mode is that a nuclear nanowire of an n-type GaN trunk is grown in a hole formed by patterning a source region, and then the quantum well and the p-type GaN are sequentially grown on the surface of the nuclear nanowire of the trunk, so that the radial PN structure is formed. And repeating the growth of the branch nanowires by the whole trunk nanowire. Fig. 4 (b), (c), (d), (e) show different quantum well structure schematic diagrams.
The axial pn structure of fig. 5 is composed of n-type GaN (n-type region 11), inGaN/GaN quantum dots (light emitting layer 12) and p-type GaN (p-type region 15) grown from bottom to top, the growth mode is that a nuclear nanowire of an n-type GaN trunk is grown in a hole formed by patterning a source region, and then the quantum dots and the n-type GaN are grown above the nanowire in sequence, so that the axial pn structure is formed. And repeating the growth of the branch nanowires by the whole trunk nanowire.
The tree-structured nanowire light emitting arrays integrated into a silicon substrate disclosed herein can be fabricated by a number of methods. Described below is an example of a method of manufacturing a nanowire light emitting array of a Si (100) substrate as shown in fig. 1, which is disclosed in the present application. Fig. 6a to 6e illustrate a fabrication process for fabricating a nanowire light emitting array as shown in fig. 1.
(1) Depositing a layer of photoresist on the Si (100) substrate, masking, exposing, etching to form an opening structure, filling an insulating medium in the formed opening to form a shallow trench isolation structure 5, stripping the residual photoresist, and removing the residual photoresist, wherein the insulating medium is preferably SiO 2 。
(3) Next, a layer of photoresist is deposited, and then a pattern to be doped in the source region and the drain region of the MOS transistor is formed by masking, exposing and photoetchingIon implantation is then performed to form the source region 3 and the drain region 4 of the MOS circuit, as shown in fig. 6 b. And depositing an insulating dielectric layer and stripping photoresist. Next, a photoresist layer is deposited again, then a gate electrode of the MOS circuit is formed by masking, exposing, etching, and then the remaining photoresist is stripped, as shown in fig. 6 c. The insulating medium layer is made of SiO 2 And one or two layers of structures formed of high-k materials. The gate electrode 9 is a metal such as Ti/Au.
(4) A layer of photoresist is deposited, then a hole array is formed on the source region 3 by masking, exposing and etching, and a tree-structured nanowire light emitting array is sequentially grown through an epitaxial process (preferably MBE). After growing the nanowire array, the transparent organic is filled, and the resulting structure is shown in fig. 6 d.
(5) A layer of photoresist is deposited and then the source and drain top regions are exposed by masking, exposing, etching, depositing a layer of metal and etching the metal to form the electrode 10 as shown in fig. 6 e.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. A multi-level branched nanowire light emitting device comprising at least one tree-structured nanowire grown on an active region or silicon substrate of a CMOS device, the tree-structured nanowire comprising a backbone nanowire and at least one branched nanowire connected to the backbone nanowire, the branched nanowire comprising at least one light emitting region.
2. The multi-branched nanowire light emitting device of claim 1, wherein the plurality of light emitting regions comprise at least one light emitting wavelength.
3. The multi-branched nanowire light emitting device of claim 1, wherein the CMOS device comprises more than two Si (100) MOS devices, at least one MOS device being an independent control unit.
4. The multi-branched nanowire light emitting device of claim 1, wherein the active region of the MOS device is grown with single or multiple tree-structured nanowires.
5. The multi-branched nanowire light emitting device of claim 1, wherein the tree-structured nanowire comprises at least one non-silicon semiconductor material.
6. The multi-level branched nanowire light emitting device of claim 1, wherein the light emitting regions are arranged radially or axially along a direction of growth of the branched nanowire.
7. The multi-branched nanowire light emitting device of claim 1, wherein the light emitting region is a PN junction and a structure comprising an interlayer, the PN junction being a homojunction, a Single Heterojunction (SH), a Double Heterojunction (DH).
8. The multi-branched nanowire light emitting device of claim 7, wherein the nanowire PN junction region is a quantum well, a quantum dot, or a combination of quantum well and quantum dot.
9. The multi-level branched nanowire light emitting device of claim 1, wherein each segment of the branched nanowire is segmented, partially segmented, or globally uniformly controlled.
10. A method of fabricating a multi-branched nanowire light emitting device as claimed in any one of claims 1 to 9, comprising at least:
preparing nano wires with tree structures on a substrate and constructing a CMOS circuit;
the preparation method of the tree-shaped structure nanowire on the silicon substrate comprises the following steps:
tree-structured nanowires are grown on a silicon substrate.
CN202311008754.7A 2023-08-11 2023-08-11 Multi-stage light-emitting branch nanowire light-emitting device and preparation method thereof Pending CN117038696A (en)

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