CN116632034B - Micro-LED chip structure and preparation method thereof - Google Patents
Micro-LED chip structure and preparation method thereof Download PDFInfo
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- 238000005530 etching Methods 0.000 claims description 8
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- 229910004298 SiO 2 Inorganic materials 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
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- 238000005566 electron beam evaporation Methods 0.000 claims description 4
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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Abstract
The application provides a Micro-LED chip structure and a preparation method thereof, and belongs to the technical field of LED semiconductors. The Micro-LED chip structure comprises a plurality of Micro-LED chips distributed in an array, wherein each Micro-LED chip comprises a substrate, a Micro-LED main body and an active addressing driving circuit, and each Micro-LED main body comprises a Si doped n-type GaN layer, a multi-quantum well layer and a Mg doped p-type GaN layer; the Micro-LED main body is of a step structure with a step surface, and the step surface is the upper surface of the Si doped n-type GaN layer; the Micro-LED main body further comprises a first metal layer which is separated by a first insulating layer and is respectively connected with the Si doped n-type GaN layer and the Mg doped p-type GaN layer; the active addressing drive circuit includes a first transistor, a second transistor, and a capacitor, all disposed on a substrate. The active addressing driving circuit with the driving transistor and the capacitor and the LED light-emitting chip are prepared on the GaN-based epitaxial wafer at the same time, so that the active addressing driving circuit is suitable for large-scale mass production; and greatly simplifies the preparation process to effectively reduce the manufacturing cost.
Description
Technical Field
The application belongs to the technical field of LED semiconductors, and particularly relates to a Micro-LED chip structure and a preparation method thereof.
Background
Micro-LEDs are a display technology that miniaturizes and matrices the LED structure, individually drives and addresses each pixel. Since various indexes such as brightness, service life, contrast ratio, reaction time, energy consumption, visual angle and resolution of Micro-LED technology are superior to those of LCD and OLED technologies, the Micro-LED technology is regarded as a new generation display technology capable of exceeding OLED and conventional LED. However, as the size of the LED chip decreases, the difference between the luminous intensity and luminous efficiency between the chips becomes more and more remarkable. Passive driving circuits have not met the needs of such high quality display screens due to the disadvantage of their own signal being prone to crosstalk. Therefore, the adoption of active addressing driving is extremely necessary to realize high quality Micro-LED display technology.
Currently, micro-LED chips based on active addressing driving circuits are typically based on POB technology, i.e. Micro-LED die are transferred onto the driving circuit board by mass transfer. However, the current mass transfer technology has various defects (such as high requirement on machine precision, low chip transfer efficiency, substandard transfer yield, high manufacturing cost, high chip repair difficulty and the like) and the preparation scheme has low yield and extremely high manufacturing cost, and cannot be applied to large-scale mass production.
Therefore, it is important to provide a Micro-LED display technical scheme which can effectively reduce the manufacturing cost and is suitable for active addressing driving in mass production.
Disclosure of Invention
In order to solve the technical problems, the application provides a Micro-LED chip structure and a preparation method thereof, wherein an active addressing driving circuit with a driving transistor and a capacitor and an LED light-emitting chip are prepared on a GaN-based epitaxial wafer at the same time, so that the Micro-LED chip structure is suitable for large-scale mass production; and greatly simplifies the preparation process to effectively reduce the manufacturing cost.
In a first aspect, the application provides a Micro-LED chip structure, which comprises a plurality of Micro-LED chips distributed in an array, wherein the Micro-LED chips comprise a substrate, a Micro-LED main body and an active addressing driving circuit, and the Micro-LED main body comprises a Si doped n-type GaN layer, a multiple quantum well layer and a Mg doped p-type GaN layer which are sequentially deposited on the substrate from bottom to top; the Micro-LED main body is of a step structure with a step surface, and the step surface is the upper surface of the Si-doped n-type GaN layer; the Micro-LED main body further comprises a first metal layer which is separated by a first insulating layer and is respectively connected with the Si-doped n-type GaN layer and the Mg-doped p-type GaN layer;
the active addressing driving circuit comprises a first transistor, a second transistor and a capacitor which are all arranged on the substrate, and the Micro-LED main body, the first transistor and the second transistor are sequentially distributed on the substrate; the pixel circuit of the Micro-LED main body is controlled to be turned on or off through the first transistor, the second transistor is communicated with a power supply and provides stable current for the Micro-LED main body in a specific pulse time period, and the capacitor for storing signals provides stable current for the Micro-LED main body after the pulse is ended, so that active addressing drives the Micro-LED main body.
Compared with the prior art, the application has the beneficial effects that: according to the Micro-LED chip structure, the light-emitting array of the Micro-LED main body is prepared on the GaN-based epitaxial wafer, and meanwhile, the active addressing driving circuit with the double-transistor and single-capacitor structure is prepared on the wafer in situ, so that the preparation flow is greatly simplified and the cost is reduced on the basis of actively addressing driving the light-emitting array of the Micro-LED main body; and the full-color Micro-LED display can be realized by matching with the quantum dot technology.
Preferably, the first transistor and the second transistor each comprise the Si-doped n-type GaN layer, the multiple quantum well layer and the Mg-doped p-type GaN layer which are sequentially deposited on the substrate from bottom to top; the first transistor further comprises a heavily doped n-type GaN layer formed by partially treating the Mg-doped p-type GaN layer by adopting a Si ion implantation mode, a first metal layer which is separated from the first insulating layer and is respectively connected with the heavily doped n-type GaN layer arranged corresponding to the heavily doped n-type GaN layer, and a second metal layer arranged corresponding to a part of the Mg-doped p-type GaN layer which is not treated by adopting the Si ion implantation mode; the first metal layers and the second metal layers are separated through a second insulating layer.
Preferably, the capacitor includes the first insulating layer, the first metal layer, the second insulating layer, and the second metal layer sequentially stacked on the substrate from bottom to top.
Preferably, the second insulating layer is deposited on the upper surface of the Micro-LED body such that the Micro-LED body is completely covered.
Preferably, the first metal layer and the second metal layer are both made of at least one metal of Cr, al, pt, au.
Preferably, the first insulating layer and the second insulating layer are made of SiO 2 Or Al 2 O 3 And the thickness of the two is 100 nm-400 nm.
In a second aspect, the present application provides a method for preparing a Micro-LED chip structure according to the first aspect, the method comprising:
s1, providing a GaN-based epitaxial wafer grown on a substrate, wherein the GaN-based epitaxial wafer comprises a Si doped n-type GaN layer, a multi-quantum well layer and a Mg doped p-type GaN layer which are sequentially deposited on the substrate from bottom to top;
s2, performing imaging treatment on the GaN-based epitaxial wafer obtained in the S1, and performing deep etching on the GaN-based epitaxial wafer subjected to the imaging treatment by adopting ICP until the substrate is exposed, so that the GaN-based epitaxial wafer is separated into a plurality of mutually independent Micro-LED main bodies with array distribution; and each Micro-LED main body is provided with three island boss structures;
s3, carrying out graphical processing on each Micro-LED main body obtained in the S2, and starting etching from part of the Mg-doped p-type GaN layer in the island-shaped boss structure of each Micro-LED main body until the Si-doped n-type GaN layer is exposed, so as to form a step surface, wherein the step surface is the upper surface of part of the Si-doped n-type GaN layer;
s4, carrying out graphical treatment on each Micro-LED main body obtained in the S3, and treating part of the Mg doped p-type GaN layer in the remaining two island-shaped boss structures of each Micro-LED main body by adopting a Si ion implantation mode to form a heavily doped n-type GaN layer;
and S5, sequentially depositing a first insulating layer, a first metal layer, a second insulating layer and a second metal layer on the three island-shaped boss structures of each Micro-LED main body processed by the S3 and the S4, so that the Micro-LED chips are formed in the area corresponding to one island-shaped boss structure processed by the S3, the first transistor and the second transistor are formed in the area corresponding to the remaining two island-shaped boss structures processed by the S4, and the capacitor is formed in the area corresponding to the remaining two island-shaped boss structures processed by the S4, thereby obtaining the Micro-LED chips distributed in a plurality of arrays.
Compared with the prior art, the application has the beneficial effects that: the light-emitting array of the Micro-LED main body is driven by active addressing through the active addressing driving circuit with the double-transistor and single-capacitor structure prepared on the wafer in situ while the light-emitting array of the Micro-LED main body is prepared on the GaN-based epitaxial wafer. And the full-color Micro-LED display can be realized by matching with the quantum dot technology, and the structural integrity is guaranteed.
Preferably, the first transistor and the second transistor each include a heavily doped n-type GaN layer, a first insulating layer, a first metal layer, a second insulating layer and a second metal layer, which are formed by sequentially depositing the Si doped n-type GaN layer, the multiple quantum well layer, the Mg doped p-type GaN layer, and the Mg doped p-type GaN layer on the substrate from bottom to top; the first metal layer is separated from the first insulating layer by the first insulating layer and is respectively connected with the heavily doped n-type GaN layer which is correspondingly arranged, the second metal layer is correspondingly arranged with the part of the Mg doped p-type GaN layer which is not treated by adopting a Si ion implantation mode, and the first metal layer and the second metal layer are separated by the second insulating layer.
Preferably, the capacitor includes the first insulating layer, the first metal layer, the second insulating layer, and the second metal layer sequentially stacked on the substrate from bottom to top.
Preferably, the first insulating layer and the second insulating layer are made of SiO 2 Or Al 2 O 3 The material is deposited and formed by an ALD surface evaporation mode; the first metal layer and the second metal layer are formed by electron beam evaporation of at least one metal of Cr, al, pt, auDeposited in a manner.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is an array diagram of a Micro-LED chip structure provided by an embodiment of the present application;
FIG. 2 is a schematic diagram of a Micro-LED chip according to an embodiment of the present application;
FIG. 3 is a circuit diagram of a Micro-LED chip provided by an embodiment of the application;
FIG. 4 is a cross-sectional view taken along line A in FIG. 2;
FIG. 5 is a cross-sectional view taken along line B in FIG. 2;
FIG. 6 is a cross-sectional view taken along line C in FIG. 2;
fig. 7 is a schematic structural diagram of a Micro-LED chip according to an embodiment of the present application in the process of manufacturing the Micro-LED chip.
Reference numerals illustrate:
10-substrate, 11-Micro-LED body, 12-first transistor, 13-second transistor, 14-capacitor;
the device comprises a 21-Si doped n-type GaN layer, a 22-multiple quantum well layer, a 23-Mg doped p-type GaN layer and a 231-heavily doped n-type GaN layer;
31-a first insulating layer, 32-a second insulating layer;
40-a first metal layer;
50-a second metal layer.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended to illustrate embodiments of the application and should not be construed as limiting the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present application, the meaning of "plurality" is two or more, unless explicitly defined otherwise.
The driving modes of the existing Micro-LED chip mainly comprise two modes: active drive and passive drive. In active driving, a Micro-LED active addressing driving circuit needs at least two transistors and one capacitor, and the structure is more complex than that of passive driving. But compared with passive driving, active driving has the advantages of stronger driving capability, better brightness uniformity and contrast, higher independent controllability and resolution, and the like. Thus, the combination of active driving and Micro-LED arrays is a great trend in the production of high resolution displays. At present, the preparation method for manufacturing the high-fraction display is commonly used as follows: micro-LED die were prepared first and then transferred to a transistor drive matrix by mass transfer. The method has the defects of low chip transfer efficiency, substandard transfer yield, high machine precision requirement, high manufacturing cost, high chip repair difficulty and the like due to huge number of transferred Micro-LED core particles, and the preparation scheme has the advantages of low yield, extremely high manufacturing cost and incapability of being applied to large-scale mass production. The present application has been made in view of this.
As shown in fig. 1 and 2, the present embodiment provides a Micro-LED chip structure including a plurality of Micro-LED chips arrayed in a rectangular array arrangement. In specific practice, each Micro-LED chip is connected with external driving signal V Data Source driving signal V s Drain driving signal V DD Scan signal V Scan And (3) electrically connecting.
Further, each Micro-LED chip of the present embodiment includes a substrate 10, a Micro-LED body 11, and an active address driving circuit. The substrate 10 is a sapphire substrate, and has the characteristics of mature preparation process, low price, easy cleaning and processing, and good stability at high temperature. Specifically, the active addressing driving circuit is specifically a circuit structure of a double transistor and a single capacitor; the active addressing driving circuit specifically comprises a first transistor 12, a second transistor 13 and a capacitor 14 which are all arranged on a substrate 10, wherein a micro-LED main body 11, the first transistor 12 and the second transistor 13 are sequentially distributed on the substrate 10, and the capacitor 14 is arranged between the first transistor 12 and the second transistor 13; of course, in embodiments, the location of the capacitor is not limited to between the first transistor and the second transistor. As shown in fig. 3, the pixel circuit of the Micro-LED body 11 is controlled to be turned on and off by the first transistor 12 (T1), a stable current is supplied to the Micro-LED body 11 through the second transistor 13 (T2) and for a specific pulse period, and the capacitor 14 (C1) is used to store a data signal, and the capacitor (C1) is still maintained at a voltage when the pulse of the scan signal is ended, thereby supplying a stable driving current to the Micro-LED body 11.
As shown in fig. 4, the Micro-LED body 11 includes a Si doped n-type GaN layer 21, a multiple quantum well layer 22, a Mg doped p-type GaN layer 23, a first insulating layer 31, a first metal layer 40, and a second insulating layer 32. The multiple quantum well layer 22 is an InGaN/GaN multiple quantum well layer. Specifically, the Si-doped n-type GaN layer 21, the multiple quantum well layer 22, the Mg-doped p-type GaN layer 23, the first insulating layer 31, the first metal layer 40, and the second insulating layer 32 are sequentially deposited on the substrate 10 from bottom to top. Preferably, the Micro-LED body 11 has a step structure with a step surface, the step surface is the upper surface of the Si-doped n-type GaN layer 21, the first metal layer 40 is separated by the patterned first insulating layer 31, and the separated first metal layer 40 is respectively connected to the Si-doped n-type GaN layer 21 and the Mg-doped p-type GaN layer 23, so as to realize electrical conduction between the first metal layer 40 and the Si-doped n-type GaN layer 21 and the Mg-doped p-type GaN layer 23. It should be noted that the second insulating layer 32 is deposited on the upper surface of the Micro-LED body 11 so that the Micro-LED body 11 is completely covered for protecting the first metal layer 40.
As shown in fig. 5, the first transistor 12 and the second transistor 13 are bothComprising a Si-doped n-type GaN layer 21, a multiple quantum well layer 22, a Mg-doped p-type GaN layer 23, a heavily doped n-type GaN layer 231, a first insulating layer 31, a first metal layer 40, a second insulating layer 32, and a second metal layer 50. Specifically, the Si-doped n-type GaN layer 21, the multiple quantum well layer 22, the Mg-doped p-type GaN layer 23, the heavily doped n-type GaN layer 231, the first insulating layer 31, the first metal layer 40, the second insulating layer 32, and the second metal layer 50 are sequentially deposited on the substrate 10 from bottom to top. In specific practice, after patterning the Mg-doped p-type GaN layer 23, siCl is introduced into the ICP machine 4 And (3) gas and setting proper power, implanting a large amount of Si ions into the Mg-doped p-type GaN layer 23 in the patterned region by adopting a plasma gas etching technology, and forming a heavily doped n-type GaN layer 231 in the region in the Mg-doped p-type GaN layer 23. The first metal layers 40 are separated by the patterned first insulating layer 31, and the separated first metal layers 40 are respectively connected to the heavily doped n-type GaN layers 231 disposed corresponding to the separated first metal layers 40, so as to realize electrical conduction between the first metal layers 40 and the heavily doped n-type GaN layers 231. The second metal layer 50 is disposed corresponding to a portion of the Mg-doped p-type GaN layer 23 that is not treated by Si ion implantation, and the first metal layer 40 and the second metal layer 50 are separated by the second insulating layer 32. Through the structure arrangement, a transistor with an NPN structure can be formed.
As shown in fig. 6, the capacitor 14 includes a first insulating layer 31, a first metal layer 40, a second insulating layer 32, and a second metal layer 50. Specifically, the first insulating layer 31, the first metal layer 40, the second insulating layer 32, and the second metal layer 50 are sequentially layered on the substrate 10 from bottom to top. Through the structure arrangement, the prepared laminated structure of the metal layer, the insulating layer and the metal layer obtains a capacitor structure required by active addressing driving.
It should be noted that: the materials of the first metal layer 40 and the second metal layer 50 in this embodiment are at least one metal of Cr, al, pt, au, that is, the materials of the first metal layer 40 and the second metal layer 50 are one or two or three or four of Cr, al, pt, au. In addition, the first insulating layer 31 and the second insulating layer 32 are made of SiO 2 Or Al 2 O 3 And the thickness of the two is 100 nm-400 nm; the specific material selection and thickness control are actually required according to specific generation.
In summary, in the Micro-LED chip structure of the embodiment, when the light emitting array of the Micro-LED main body is prepared on the GaN-based epitaxial wafer, and the active addressing driving circuit with the double-transistor and single-capacitor structure is prepared on the wafer in situ, so that the preparation flow is greatly simplified and the cost is reduced on the basis of realizing active addressing driving of the light emitting array of the Micro-LED main body; and the full-color Micro-LED display can be realized by matching with the quantum dot technology.
In order to better explain and explain the Micro-LED chip structure of the present embodiment, a preparation flow of one Micro-LED body in the Micro-LED chip structure is illustrated, and a schematic structural diagram in a specific preparation process is shown in fig. 7.
Further, a flowchart of a preparation method of the Micro-LED chip of the embodiment is provided, which specifically includes:
s1, providing a GaN-based epitaxial wafer grown on a substrate.
Specifically, the substrate is a sapphire substrate, and the sapphire substrate has the characteristics of mature preparation process, low price, easy cleaning and processing, and good stability at high temperature, so that the industrial production is conveniently realized.
Further, growing a GaN-based epitaxial wafer on the sapphire substrate; the GaN-based epitaxial wafer comprises a Si doped n-type GaN layer, a multiple quantum well layer and a Mg doped p-type GaN layer which are sequentially deposited on a sapphire substrate from bottom to top; the multi-quantum well layer is an InGaN/GaN multi-quantum well layer which is periodically and alternately stacked. In order to activate the Mg acceptor, the catalyst is used in the following formula N 2 Carrying out thermal annealing on the Mg-doped p-type GaN layer in the atmosphere, wherein the annealing temperature is 750 ℃, the annealing time is 20min, and the growth of the GaN-based epitaxial wafer is finished; and cleaning the epitaxial wafer by adopting HCl solution, and spin-drying after cleaning.
S2, spin-coating photoresist on the surface of the GaN-based epitaxial wafer, patterning the region to be etched, starting deep etching from the surface of the GaN-based epitaxial wafer patterned by using ICP (inductively coupled plasma) until the GaN-based epitaxial wafer is etched to the substrate, forming three island-shaped boss structures (see (a) in FIG. 7 for specific details), and cleaning and photoresist removing.
Specifically, spin-coating photoresist on the surface of a GaN-based epitaxial wafer, patterning a region to be etched by utilizing a photoetching technology, and deep etching by adopting ICP until the substrate is exposed, so that the Micro-LED main body has three island boss structures in an island shape, and the upper surface of the Micro-LED main body is the surface of a Mg-doped p-type GaN layer.
S3, spin-coating photoresist on the surface of the Micro-LED main body obtained in the S2, patterning a region to be etched, starting etching a part of the Mg-doped p-type GaN layer in an island-shaped boss structure of the Micro-LED main body by using ICP until the Si-doped n-type GaN layer is exposed to form a step surface (see (b) in FIG. 7 for details), and cleaning and photoresist removing.
Specifically, the step surface is part of the upper surface of the Si-doped n-type GaN layer
And S4, carrying out graphical treatment on the Micro-LED main body obtained in the step S3, and treating part of the Mg doped p-type GaN layer in the residual two island-shaped boss structures of the Micro-LED main body by adopting a Si ion implantation mode to form a heavily doped n-type GaN layer (see (c) in FIG. 7 for details).
Specifically, the Si ion implantation method specifically includes: siCl is introduced into an ICP machine table 4 And (3) carrying out Si element injection on the patterned region, and forming a heavily doped n-type GaN layer in part of the Mg doped p-type GaN layer.
S5, adopting ALD to vapor-deposit a first insulating layer on the upper surfaces of the three island-shaped boss structures of the Micro-LED main body processed by the S3 and the S4.
Specifically, the first insulating layer is made of SiO 2 And the thickness is selected in the range of 100nm to 400nm. Of course, other embodiments may also use Al 2 O 3 The thickness is selected in the range of 100nm to 400nm.
And S6, spin-coating photoresist on the surface of the first insulating layer, patterning the region to be etched, and removing the first insulating layer by wet etching.
Specifically, wet etching is specifically performed by wet etching with a KOH solution.
S7, spin-coating photoresist on the surface of the wafer obtained in the step S6, patterning the region where metal needs to be evaporated, adopting electron beam evaporation to deposit a first metal layer (see (d) in FIG. 7 for details), and cleaning and photoresist removing.
Specifically, the first metal layer is made of one of Cr, al, pt, au, or two or three of the metal materials.
S8, evaporating a second insulating layer on the surface of the wafer obtained in the S7 by ALD.
Specifically, the second insulating layer is made of SiO 2 And the thickness is selected in the range of 100nm to 400nm. Of course, other embodiments may also use Al 2 O 3 The thickness is selected in the range of 100nm to 400nm.
And S9, spin-coating photoresist on the surface of the second insulating layer, patterning the area to be etched, and removing the second insulating layer by wet etching.
Specifically, wet etching is specifically performed by wet etching with a KOH solution.
S10, spin-coating photoresist on the surface of the wafer obtained in the step S9, patterning the region where metal needs to be evaporated, adopting electron beam evaporation to deposit a second metal layer (see (e) in fig. 7 for details), and cleaning and photoresist removing.
Specifically, the second metal layer is made of one of Cr, al, pt, au, or two or three or four metal materials.
In summary, through the steps, the light-emitting array of the Micro-LED main body is prepared on the GaN-based epitaxial wafer, and meanwhile, the active addressing driving circuit with the double-transistor and single-capacitor structure is prepared on the wafer in situ, so that the light-emitting array of the Micro-LED main body is driven by active addressing. And the full-color Micro-LED display can be realized by matching with the quantum dot technology, and the structural integrity is guaranteed.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the application.
Claims (8)
1. The preparation method of the Micro-LED chip structure is characterized by comprising the following steps of:
s1, providing a GaN-based epitaxial wafer grown on a substrate, wherein the GaN-based epitaxial wafer comprises a Si doped n-type GaN layer, a multi-quantum well layer and a Mg doped p-type GaN layer which are sequentially deposited on the substrate from bottom to top;
s2, performing imaging treatment on the GaN-based epitaxial wafer obtained in the S1, and performing deep etching on the GaN-based epitaxial wafer subjected to the imaging treatment by adopting ICP until the substrate is exposed, so that the GaN-based epitaxial wafer is separated into a plurality of mutually independent Micro-LED main bodies with array distribution; and each Micro-LED main body is provided with three island boss structures;
s3, carrying out graphical processing on each Micro-LED main body obtained in the S2, and starting etching from part of the Mg-doped p-type GaN layer in the island-shaped boss structure of each Micro-LED main body until the Si-doped n-type GaN layer is exposed, so as to form a step surface, wherein the step surface is the upper surface of part of the Si-doped n-type GaN layer;
s4, carrying out graphical treatment on each Micro-LED main body obtained in the S3, and treating part of the Mg doped p-type GaN layer in the remaining two island-shaped boss structures of each Micro-LED main body by adopting a Si ion implantation mode to form a heavily doped n-type GaN layer;
s5, sequentially depositing a first insulating layer, a first metal layer, a second insulating layer and a second metal layer on the three island-shaped boss structures of each Micro-LED main body processed by the S3 and the S4, so that Micro-LED chips are formed in the area corresponding to one island-shaped boss structure processed by the S3, the first transistor and the second transistor are formed in the area corresponding to the remaining two island-shaped boss structures processed by the S4, and the capacitor is formed in the area corresponding to the remaining two island-shaped boss structures processed by the S4, so that the Micro-LED chips distributed in a plurality of arrays are obtained;
the first transistor and the second transistor comprise the Si doped n-type GaN layer, the multiple quantum well layer, the Mg doped p-type GaN layer, a heavy doped n-type GaN layer formed by partially treating the Mg doped p-type GaN layer in a Si ion implantation mode, a first insulating layer, a first metal layer, a second insulating layer and a second metal layer which are sequentially deposited on the substrate from bottom to top; the first metal layer is separated from the first insulating layer by the first insulating layer and is respectively connected with the heavily doped n-type GaN layer which is correspondingly arranged, the second metal layer is correspondingly arranged with the part of the Mg doped p-type GaN layer which is not treated by adopting a Si ion implantation mode, and the first metal layer and the second metal layer are separated by the second insulating layer.
2. The method of claim 1, wherein the capacitor comprises the first insulating layer, the first metal layer, the second insulating layer, and the second metal layer sequentially stacked on the substrate from bottom to top.
3. The method for manufacturing a Micro-LED chip structure according to any one of claims 1 to 2, wherein the first insulating layer and the second insulating layer are made of SiO 2 Or Al 2 O 3 The material is deposited and formed by an ALD surface evaporation mode; the first metal layer and the second metal layer are formed by adopting at least one metal in Cr, al, pt, au through an electron beam evaporation mode.
4. A Micro-LED chip structure, which adopts the preparation method of the Micro-LED chip structure according to any one of claims 1 to 3, and comprises a plurality of Micro-LED chips distributed in an array, and is characterized in that the Micro-LED chip comprises a substrate, a Micro-LED main body and an active addressing driving circuit, and the Micro-LED main body comprises a Si doped n-type GaN layer, a multi-quantum well layer and a Mg doped p-type GaN layer which are sequentially deposited on the substrate from bottom to top; the Micro-LED main body is of a step structure with a step surface, and the step surface is the upper surface of the Si-doped n-type GaN layer; the Micro-LED main body further comprises a first metal layer which is separated by a first insulating layer and is respectively connected with the Si-doped n-type GaN layer and the Mg-doped p-type GaN layer;
the active addressing driving circuit comprises a first transistor, a second transistor and a capacitor which are all arranged on the substrate, and the Micro-LED main body, the first transistor and the second transistor are sequentially distributed on the substrate; the pixel circuit of the Micro-LED main body is controlled to be turned on and off through the first transistor, the second transistor is communicated with a power supply and provides stable current for the Micro-LED main body in a specific pulse time period, and the capacitor for storing signals provides stable current for the Micro-LED main body after the pulse is ended, so that active addressing drives the Micro-LED main body;
the first transistor and the second transistor comprise the Si doped n-type GaN layer, the multi-quantum well layer and the Mg doped p-type GaN layer which are sequentially deposited on the substrate from bottom to top; the first transistor further comprises a heavily doped n-type GaN layer formed by partially treating the Mg-doped p-type GaN layer by adopting a Si ion implantation mode, a first metal layer which is separated from the first insulating layer and is respectively connected with the heavily doped n-type GaN layer arranged corresponding to the heavily doped n-type GaN layer, and a second metal layer arranged corresponding to a part of the Mg-doped p-type GaN layer which is not treated by adopting the Si ion implantation mode; the first metal layers and the second metal layers are separated through a second insulating layer.
5. The Micro-LED chip structure of claim 4, wherein the capacitor comprises the first insulating layer, the first metal layer, the second insulating layer, the second metal layer sequentially deposited on the substrate from bottom to top.
6. The Micro-LED chip structure of claim 4, wherein the second insulating layer is deposited on the upper surface of the Micro-LED body such that the Micro-LED body is completely covered.
7. The Micro-LED chip structure of claim 4, wherein the first metal layer and the second metal layer are both made of at least one metal of Cr, al, pt, au.
8. The Micro-LED chip structure of claim 4, wherein the first insulating layer and the second insulating layer are made of SiO 2 Or Al 2 O 3 And the thickness of the two is 100 nm-400 nm.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105702623A (en) * | 2016-02-02 | 2016-06-22 | 武汉华星光电技术有限公司 | TFT array substrate manufacture method |
| CN110071125A (en) * | 2019-05-05 | 2019-07-30 | 京东方科技集团股份有限公司 | TFT backplate and preparation method thereof, OLED display panel |
| CN111682043A (en) * | 2020-06-24 | 2020-09-18 | 京东方科技集团股份有限公司 | Chip structure, manufacturing method thereof and display device |
| CN112701139A (en) * | 2020-12-29 | 2021-04-23 | 武汉大学 | Integrated structure Micro-LED display and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105702623A (en) * | 2016-02-02 | 2016-06-22 | 武汉华星光电技术有限公司 | TFT array substrate manufacture method |
| CN110071125A (en) * | 2019-05-05 | 2019-07-30 | 京东方科技集团股份有限公司 | TFT backplate and preparation method thereof, OLED display panel |
| CN111682043A (en) * | 2020-06-24 | 2020-09-18 | 京东方科技集团股份有限公司 | Chip structure, manufacturing method thereof and display device |
| CN112701139A (en) * | 2020-12-29 | 2021-04-23 | 武汉大学 | Integrated structure Micro-LED display and preparation method thereof |
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