WO2019109940A1

WO2019109940A1 - Led display module, display, and manufacturing method thereof

Info

Publication number: WO2019109940A1
Application number: PCT/CN2018/119330
Authority: WO
Inventors: 黎子兰
Original assignee: 黎子兰
Priority date: 2017-12-07
Filing date: 2018-12-05
Publication date: 2019-06-13
Also published as: CN108198835A

Abstract

An LED display module, a display, and a manufacturing method thereof. The LED display module (300) comprises: a substrate (301); an LED region (302) provided on the substrate, comprising an LED light emitting structure; and a circuit region (303) provided on the substrate, comprising at least one transistor, wherein at least one transistor is electrically connected to the LED light emitting structure.

Description

LED display unit, display and manufacturing method thereof

Technical field

The present invention relates to the field of LED display, and in particular to a micro LED (Micro-LED) display unit, a display, and a method of fabricating the same.

Background technique

Micro LED technology's life, contrast, response time, energy consumption, viewing angle, resolution and other indicators are better than the current LCD and OLED, has been considered by many manufacturers as the next generation of display technology. However, there are still many problems in the application of Micro LED.

Summary of the invention

In view of the technical problems existing in the prior art, the present invention provides an LED display unit comprising: a substrate; an LED region on the substrate including an LED light emitting structure; and a circuit region on the substrate including at least one a transistor; wherein the at least one transistor is electrically connected to the LED lighting structure.

An LED display unit as described above, wherein said at least one transistor comprises a first transistor; and a source and a drain of the first transistor are connected between the power source and the LED lighting structure.

One or more LED display units as described above, wherein the at least one transistor comprises a second transistor; wherein the gate of the second transistor is connected to a row scan signal and the source and drain of the second transistor are connected in a column scan Between the signal and the LED lighting structure.

One or more LED display units as described above, wherein the at least one transistor comprises a first transistor, a second transistor, and a capacitor; a source and a drain of the first transistor are connected between the power source and the LED light emitting structure; and the second transistor The gate is connected to the row scan signal, the source of the second transistor is connected to the column scan signal, the drain of the second transistor is connected to the gate of the first transistor, and the capacitor is connected between the gate of the second transistor and the power source.

One or more LED display units as described above, wherein the LED lighting structure comprises a GaN-based LED lighting structure.

One or more LED display units as described above, wherein the LED light emitting structure comprises an overlapping electron transport layer, a radiation composite layer, and a hole transport layer.

The one or more LED display units as described above, wherein the LED light emitting structure comprises a nucleation layer, an electron transport layer core on the partial nucleation layer, and a radiation composite layer and a hole transport layer on the electron transport layer core.

One or more LED display units as described above, wherein the LED lighting structure further comprises an insulating layer on the nucleation layer, wherein the insulating layer includes an opening to expose the portion of the nucleation layer.

The one or more LED display units as described above, wherein the LED light emitting structure comprises a nucleation layer core, an electron transport layer core on the core of the nucleation layer, and a radiation composite layer and a hole transport layer on the core of the electron transport layer.

The one or more LED display units as described above, wherein the LED light emitting structure further comprises an insulating layer, wherein the core of the nucleation layer is located in the opening of the insulating layer.

According to another aspect of the present invention, there is provided an LED display unit comprising: a substrate; an LED region on the substrate comprising an LED light emitting structure; a first doped region on the substrate comprising a first transistor; The source and the drain of the first transistor are connected between the power source and the LED light emitting structure.

The LED display unit as described above further includes a second doped region on the substrate including the second transistor; a source or a drain of the second transistor is coupled to the gate of the first transistor.

The one or more LED display units as described above further include a capacitance formed on a region other than the first doped region and the second doped region.

The one or more LED display units as described above, wherein the LED light emitting structure comprises an overlapping electron transport layer, a radiation composite layer, and a hole transport layer.

According to another aspect of the present invention, an LED display is provided, comprising: a substrate; a plurality of LED light emitting structures on the substrate; and a plurality of transistors on the substrate; wherein at least one of the plurality of transistors Connected to an LED lighting structure.

According to another aspect of the present invention, an LED display is provided, comprising: a substrate; and an LED matrix on the substrate, comprising a plurality of LED display units arranged in rows and columns; wherein the LED display unit comprises: on the substrate An LED region comprising an LED lighting structure; and a circuit region on the substrate comprising at least one transistor; wherein the at least one transistor is electrically coupled to the LED lighting structure.

According to another aspect of the present invention, an LED display is provided, comprising: a substrate; and an LED matrix on the substrate, comprising a plurality of LED display units arranged in rows and columns; wherein the LED display unit comprises: on the substrate a first doped region comprising a first transistor; an undoped region on the substrate comprising an LED light emitting structure; wherein a source and a drain of the first transistor are connected between the power source and the LED light emitting structure.

According to another aspect of the present invention, a method for fabricating an LED display unit includes: forming a P-electrode and an N-electrode on an LED epitaxial structure on a substrate, wherein the LED epitaxial structure includes a nucleation layer, an electron transport layer, a radiation composite layer and a hole transport layer; forming a first transistor on the substrate; and electrically connecting the P-electrode or the N-electrode to the first transistor.

The manufacturing method as described above, wherein forming the N-electrode comprises: removing a portion of the radiation composite layer and the hole transport layer, exposing the electron transport layer; partially removing the exposed electron transport layer and the nucleation layer, exposing the substrate And forming an N-electrode on the remaining electron transport layer.

The one or more manufacturing methods as described above, further comprising: forming an insulating layer covering at least the P-electrode and the N-electrode.

One or more manufacturing methods as described above, wherein the source and drain of the first transistor are connected between the power source and the LED lighting structure.

According to another aspect of the present invention, a method of fabricating an LED display unit includes: forming a P-electrode and an N-electrode on an epitaxial structure of an LED on a substrate, wherein the epitaxial structure of the LED comprises: a nucleation layer; an insulating layer And comprising an opening to expose a portion of the nucleation layer; an electron transport layer core extending from the exposed partial nucleation layer; and a radiation composite layer and a hole transport layer on the core of the electron transport layer; forming a first transistor on the substrate; And electrically connecting the P-electrode or the N-electrode to the first transistor.

The method as described above, wherein forming the P-electrode comprises forming a P-electrode on the hole transport layer, wherein at least a portion of the P-electrode extends over the insulating layer.

The method of one or more of the above, wherein forming the N-electrode comprises removing a portion of the radiation composite layer and the hole transport layer, exposing the electron transport layer core; forming an N-electrode on the exposed electron transport layer core .

The method of one or more of the above described, further comprising: forming a second transistor on the substrate, the second transistor being coupled to the first transistor.

The method of one or more of the methods described above, further comprising forming a capacitance between the first transistor between the first transistors.

According to another aspect of the present invention, a method of fabricating an LED display unit is provided, comprising: forming a P-electrode and an N-electrode on an LED epitaxial structure on a substrate, wherein the LED epitaxial structure comprises: an insulating layer including an opening a nucleation layer located in the opening of the insulating layer; an electron transport layer core extending from the nucleation layer; and a radiation composite layer and a hole transport layer on the core of the electron transport layer; forming a first transistor on the substrate; The P-electrode or the N-electrode are electrically connected to the first transistor.

One or more methods as described above, wherein forming the N-electrode comprises removing a portion of the radiation composite layer and the hole transport layer, exposing the electron transport layer core; forming an N-electrode on the exposed electron transport layer core.

The one or more methods as described above, further comprising: forming a second transistor on the substrate, the second transistor being coupled to the first transistor.

The one or more methods as described above, further comprising: forming a capacitance between the first transistor between the first transistors.

According to another aspect of the present invention, a method of fabricating an LED display includes: forming a plurality of P-electrodes and a plurality of N-electrodes on a plurality of LED epitaxial structures on a substrate, wherein the LED epitaxial structure comprises nucleation a layer, an electron transport layer, a radiation composite layer, and a hole transport layer; forming a plurality of first transistors on the substrate; and electrically connecting the plurality of P-electrodes or N-electrodes to the plurality of first transistors, respectively.

According to another aspect of the present invention, a method of fabricating an LED display includes: forming a plurality of P-electrodes and a plurality of N-electrodes on a plurality of LED epitaxial structures on a substrate, wherein the LED epitaxial structure comprises: a core layer; an insulating layer including an opening to expose a portion of the nucleation layer; an electron transport layer core extending from the exposed partial nucleation layer; and a radiation composite layer and a hole transport layer on the core of the electron transport layer; Forming a plurality of first transistors; and electrically connecting the plurality of P-electrodes or N-electrodes to the plurality of first transistors, respectively.

According to another aspect of the present invention, a method of fabricating an LED display includes: forming a plurality of P-electrodes and a plurality of N-electrodes on a plurality of LED epitaxial structures on a substrate, wherein the LED epitaxial structure comprises: insulating a layer comprising an opening; a nucleation layer located in the opening of the insulating layer; an electron transport layer core extending from the nucleation layer; and a radiation composite layer and a hole transport layer on the electron transport layer core; First transistors; and electrically connecting a plurality of P-electrodes or N-electrodes to the plurality of first transistors, respectively.

DRAWINGS

Hereinafter, preferred embodiments of the present invention will be further described in detail with reference to the accompanying drawings, in which:

Figures 1a-1c show schematic diagrams of the manner in which these three types of Micro LEDs are located;

2 is a schematic diagram of a process flow of an active driving Micro LED;

3 is a schematic structural view of an LED display unit according to an embodiment of the present invention;

4 is a schematic structural view of an LED display unit according to an embodiment of the present invention;

Figure 5 is a schematic illustration of an LED display device in accordance with one embodiment of the present invention;

6a-6j are schematic diagrams showing a manufacturing process of an LED display unit structure according to an embodiment of the present invention;

7a-7n are schematic diagrams showing a manufacturing process of an LED display unit structure according to another embodiment of the present invention;

FIG. 8 is a schematic structural view of an LED display unit according to still another embodiment of the present invention; FIG.

9 is a flow chart of a method of fabricating an LED display structure in accordance with an embodiment of the present invention;

10 is a flow chart of a method of fabricating an LED display structure in accordance with another embodiment of the present invention;

11 is a flow chart of a method of fabricating an LED display structure in accordance with another embodiment of the present invention;

12 is a flow chart of a method of fabricating an LED display structure in accordance with another embodiment of the present invention;

13 is a flow chart of a method of fabricating an LED display structure in accordance with another embodiment of the present invention;

14 is a flow chart of a method of fabricating an LED display structure in accordance with another embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. It is a partial embodiment of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

In the following detailed description, reference should be made to the claims In the drawings, like reference characters refer to the FIGS The specific embodiments of the present application are described in sufficient detail below to enable those of ordinary skill in the art to implement the technical solutions of the present application. It is understood that other embodiments may be utilized or structural, logical or electrical changes may be made to the embodiments of the application.

The existing Micro LED driving methods mainly include a passive address driving method, a semi-active address driving method, and an active location driving method. Figures 1a-1c show schematic diagrams of the manner in which these three Micro LEDs are addressed. Figure 1a shows the passive location drive approach. As shown, a plurality of LEDs 101 are included for the LED matrix 100. The cathodes of the respective LEDs of the same row are connected to a row scan line (Scan Line) 102; the anodes of the respective LEDs of the same column are connected to the column scan line 103. The column scan line 103 is connected to a plurality of data current sources for providing drive signals for the LEDs. When the X-th row and the Y-th column scan line are gated, the LED (X, Y) at the intersection thereof is illuminated. By scanning the entire LED matrix in a progressive scan manner, a desired image can be obtained on the LED matrix. However, the passive location method is complicated, the parasitic capacitance and the resistance are large, and crosstalk between the LEDs is prone to occur, and it is difficult to realize large-area display.

Figure 1b shows a semi-active location drive approach. As shown, transistor 104 is incorporated into each LED display unit of the LED matrix. The source of the transistor 104 is connected to the column scan line 103, the gate is connected to the row scan line 102, and the drain is connected to the LED 101. When the transistor 104 is gated by the row scan line 102, the drive current signal from the column scan line 103 drives the LED 101 to emit light via the transistor 104. Although the semi-active address driving method can solve the problem of crosstalk between LEDs, the driving current signals of each column need to be separately modulated, and there are still many restrictions on the use.

Figure 1c shows the active location drive approach. Unlike the semi-active addressing method, a more complete drive circuit is included in each LED display unit. Specifically, the driving circuit includes a gate transistor 104, a driving transistor 105, and a capacitor 106. The source of the gate transistor 104 is connected to the column scan line 103, the gate is connected to the row scan line 102, and the drain is connected to the gate of the drive transistor 105. The source of the driving transistor 105 is connected to the power source, and the drain is connected to the LED 101. Both ends of the capacitor 106 are connected between the source and the gate of the driving transistor 105. The gate transistor 104 is used to control the on or off of the display unit circuit. The driving transistor 105 supplies a stable current to the LED 101 for a predetermined time (for example, one frame). Capacitor 106 is used to store the drive current signal. When the scan driving current signal pulse of the LED 101 is over, the capacitor 106 can still maintain the voltage of the gate of the driving transistor 105, so that the LED 101 continues to obtain the driving current until the end of the predetermined time.

Those skilled in the art should understand that the above description is for illustrative purposes only and is not intended to limit the scope of the invention. For example, there are other active drive circuits for the Micro LED, such as a 4T2C drive circuit, a 4T1C drive circuit, a 5T1C drive circuit, and the like. The drive circuits of these structures are equally applicable to the solution of the present invention without departing from the teachings of the present invention.

Both semi-active or active drive methods involve the fabrication of associated circuits for the LED matrix. In the prior art, the LED matrix and the circuit are fabricated separately. For example, U.S. Patent No. 7,349,911 discloses an active drive Micro LED process flow. As shown in Figure 2, and with reference to the related description of the patent, the Micro LED matrix is fabricated on a sapphire substrate; and the driver circuit is fabricated on silicon or other substrate. The Micro LED matrix is then combined with the drive circuit through a flip chip process. This process is very complicated and requires a high degree of precision for flip chip bonding, so the cost is extremely high. Moreover, this process flow is not conducive to further miniaturization of the Micro LED due to the accuracy limitations of flip chip bonding.

The present invention proposes a completely new structure that combines the LED lighting structure and the driving circuit in a single substrate, thereby avoiding many problems in the prior art.

3 is a schematic structural view of an LED display unit according to an embodiment of the present invention. As shown, the LED display unit 300 includes a substrate 301 and an LED region 302 and a drive circuit region 303 on the substrate 301. LED area 302 includes an LED lighting structure. According to an embodiment of the present invention, the LED light emitting structure is based on a III-V nitride semiconductor such as GaN, AlGaN, InGaN, or the like. According to one embodiment of the invention, the size of the LED lighting structure is below 100 microns, below 50 microns, below 20 microns, below 10 microns, below 1 micron or less.

The drive circuit region 303 includes a drive circuit. The drive circuit includes at least one or more transistors. The one or more transistors may also include drive transistors. One end of the drive transistor is connected to the LED illumination structure and the other end is connected directly or indirectly to the power supply. The drive transistor is controlled to provide current to the LED illumination structure to drive the LED illumination structure to emit light. Further, the one or more transistors include at least a gate transistor. When the gate transistor is gated, the drive current is driven by the gate transistor to drive the LED illumination structure. Alternatively, the gate transistor is connected to the gate of the drive transistor. When the gate transistor is gated, the drive current is driven to drive the LED illumination structure through the drive transistor. Further, the driving circuit may further include a storage capacitor connected between the gate of the driving transistor and the power source for storing a driving current signal from the column scanning line. Thus, even after the drive current signal pulse disappears, the storage capacitor can provide a working bias to the drive transistor for a predetermined time. Further, the one or more transistors may also include other transistors to form a current compensation circuit or other functional circuit. Further, the driver circuit may also include one or more capacitors or other devices.

4 is a schematic structural view of an LED display unit according to an embodiment of the present invention. As shown, display unit 400 includes a substrate 401 and one or more

doped regions

402, 404 and a non-doped region 403 on substrate 401. The display unit 400 includes one or more transistors formed on the doped regions and an LED light emitting structure formed on the LED regions 403. The doped region includes at least a driving transistor. One end of the drive transistor is connected to the LED illumination structure and the other end is connected directly or indirectly to the power supply. The drive transistor is controlled to provide current to the LED illumination structure to drive the LED illumination structure to emit light. Further, the one or more transistors include at least a gate transistor. When the gate transistor is gated, the drive current is driven by the gate transistor to drive the LED illumination structure. Alternatively, the gate transistor is connected to the gate of the drive transistor. When the gate transistor is gated, the drive current is driven to drive the LED illumination structure through the drive transistor. Further, a storage capacitor may be further included between the gate of the driving transistor and the power source for storing a driving current signal from the column scan line. Thus, even after the drive current signal pulse disappears, the storage capacitor can provide a working bias to the drive transistor for a predetermined time. According to an embodiment of the invention, the storage capacitor is disposed over a region other than the plurality of doped regions. Further, the one or more transistors may also include other transistors to form a current compensation circuit or other functional circuit. Further, one or more capacitors or other devices may also be included.

Figure 5 is a schematic illustration of an LED display device in accordance with one embodiment of the present invention. As shown, the LED display device 500 includes an LED matrix 501, a row driving circuit 502, and a column driving circuit 503. The LED matrix includes a plurality of LED display units; wherein the LED display unit includes an LED lighting structure and a driving circuit on the same substrate. Further, the row driving circuit 502 is connected to the driving circuits of the plurality of LED display units through the row scanning lines; the column driving circuit 503 is connected to the driving circuits of the plurality of LED display units through the column driving lines. Under the control of the row driving circuit 502 and the column driving circuit 503, the driving circuits of the plurality of LED display units drive the corresponding LED light emitting structures. The LED lighting structure of each LED display unit can be driven separately.

According to an embodiment of the invention, the substrate of the invention is a silicon (Si) substrate. Those skilled in the art will appreciate that the present invention is equally applicable to other types of substrates, such as gallium nitride GaN, gallium arsenide GaAs, indium phosphide InP, silicon carbide SiC, aluminum nitride AlN, zinc oxide ZnO, and the like.

The following is an example of an active location driving method on a Si substrate, and specifically illustrates a technical solution of the LED display structure of the present invention. Those skilled in the art will appreciate that different choices of LED lighting structures or drive circuits may result in different LED display configurations of the present invention, and such variations are also within the scope of the present invention.

6a-6j are schematic diagrams showing the manufacturing flow of an LED display unit structure in accordance with one embodiment of the present invention. Figure 6a shows a GaN-on-Si epitaxial wafer. The GaN-on-Si epitaxial wafer includes a silicon Si substrate and a nucleation layer, an electron transport layer, a radiation composite layer, and a hole transport layer on the Si substrate. It is difficult to directly epitaxially grow a group III/V nitride such as gallium nitride GaN on a Si substrate, and the Si substrate includes a nucleation layer. An example of a nucleation layer is aluminum nitride AlN. Of course, other materials suitable as nucleation layers for the Si substrate can also be used. Further, one or more buffer layers or intervening layers may be included above, below or between the nucleation layer and the electron transport layer. For example, the electron transport layer may include N-type gallium nitride N-GaN, the radiation composite layer may include a multi-element compound InGaN of gallium nitride GaN, indium nitride, and the like, and the hole transport layer may include P-type gallium nitride. P-GaN. According to another embodiment of the present invention, the process of the present invention can also be started directly from a Si substrate without using a GaN-on-Si epitaxial wafer.

As shown in Fig. 6b, a P-electrode layer and an insulating layer are formed on the hole transport layer. Next, the insulating layer, the P-electrode layer, the hole transport layer, and the radiation composite layer are partially removed to expose the electron transport layer. According to an embodiment of the present invention, the electron transport layer can be partially removed to ensure the effect of removal. As shown in Figure 6c, an N-electrode is formed on the exposed electron transport layer. So far, a general-purpose LED light-emitting structure has been formed on the GaN-on-Si epitaxial wafer. Those skilled in the art should understand that the LED light emitting structure may also be formed in other manners according to different or actual needs of the LED light emitting structure.

As shown in Figure 6d, the electron transport layer and the nucleation layer are partially removed to expose the Si substrate. Further, doped regions 601 and doped regions 602 which are spaced apart from each other and a spacer 603 therebetween are formed on the exposed Si substrate.

As shown in Figure 6e, an isolation layer 604 is formed over the entire Si substrate. Two openings are then formed on the doped region 601 and the doped region 602, respectively.

As shown in FIG. 6f, a transistor 605 and a transistor 606 are formed in the openings of the doped region 601 and the doped region 602, respectively; wherein the transistor 605 includes a drain 6051, a gate 6052, and a source 6053. Transistor 606 includes a drain 6061, a gate 6062, and a source 6063.

As shown in Fig. 6g, an isolation layer 607 is formed over the entire Si substrate. Then, an opening is formed on the isolation layer 607 to expose the drain 6051 and the source 6053 of the transistor 605. At the same time, a portion of the insulating layer on the P electrode, the isolation layer 604, and the isolation layer 607 are removed, and a portion of the P-electrode is exposed.

As shown in FIG. 6h, a conductive material layer 608 and a conductive material layer 609 are formed, wherein the conductive material layer 608 electrically connects the P-electrode to the drain 6051 of the transistor 605; the conductive material layer 609 electrically connects the source 6053 of the transistor 605, and The conductive material layer 609 partially covers the spacer 603 between the doped region 601 and the doped region 602.

As shown in FIG. 6i, an isolation layer 610 is formed over the entire Si substrate. The isolation layer 610 is then partially removed, exposing the gate 6052 of the transistor 605 and the drain 6061 of the transistor 606.

As shown in FIG. 6j, a conductive material layer 611 is formed in which the conductive material layer 611 electrically connects the gate 6052 of the transistor 605 and the drain 6061 of the transistor 606, and the conductive material layer 611 partially covers the conductive material layer 609. Thereby, the isolation layer 610 is spaced between the conductive material layer 609 and the conductive material layer 611, thereby forming a capacitor 612.

Referring to FIG. 6j, the transistor 605 can function as a driving transistor to drive the LED light emitting structure; the transistor 606 can function as a gate transistor; and the capacitor 612 can serve as a storage capacitor to form the driving circuit of the active addressing mode of FIG.

Thus, according to the above embodiment of the present invention, an LED light emitting structure and a driving circuit LED display structure are formed on a single Si substrate, and monolithic integration of the Micro LED light emitting structure and the driving circuit is realized, thereby avoiding the prior art. Complex and costly flip-chip bonding process. Further, the LED display structure of the present invention is less limited in size, and is more advantageous for miniaturization of the Micro LED.

For Micro LED applications, one of the patented technical challenges recognized in the art is the massive transfer of Micro LEDs. According to the above embodiment of the present invention, the Micro LED does not need to be divided and relocated, thereby avoiding the problem of a large amount of transfer. According to some embodiments of the present invention using a Si substrate, since the cost of the Si substrate is low and the process maturity is high, the technical solution of the present invention can break through many limitations in the application of the Micro LED and become a revolutionary meaning. Program.

The following is another embodiment of the present invention. In this embodiment, a pyramid-type LED light-emitting structure is employed, eliminating the need for a planar GAN-on-Si epitaxial layer, and thus avoiding the limitation of warpage due to the planar GAN-on-Si epitaxial wafer.

7a-7m are schematic diagrams showing a manufacturing process of an LED display unit structure in accordance with another embodiment of the present invention. Figure 7a shows a Si substrate and a nucleation layer formed on Si. Further, as shown in FIG. 7b, an insulating layer such as SiO ₂ or SiN is formed on the nucleation layer. However, an opening is formed on the insulating layer while a portion of the nucleation layer is exposed.

As shown in FIG. 7c, an electron transport layer 720, a radiation composite layer 721, and a hole transport layer 722 are formed by epitaxial growth on the exposed nucleation layer. The electron transport layer 720, the radiation composite layer 721, and the hole transport layer 722 form a GaN epitaxial structure. For the epitaxial growth of the selection, reference is made to Glo, AB, U.S. Patent No. 8,921,141. The entire content of this patent is incorporated herein by reference.

As shown in FIG. 7d, a P-electrode layer 723 is formed on the hole transport layer 722, and the P-electrode layer 723 includes an extended portion 724 on the insulating layer. Further, a spacer layer 725 is formed on the P-electrode layer 723. The partial spacer layer 725, the P-electrode layer 723, the hole transport layer 722, and the radiation composite layer 721 are removed, and the electron transport layer 720 is exposed. According to an embodiment of the present invention, the electron transport layer 720 may be partially removed to ensure the effect of removal.

As shown in Figure 7e, an isolation layer 726 having good conformality is formed over the entire Si substrate.

As shown in FIG. 7f, the isolation layer 726 overlying the spacer layer 725 and the insulating layer is removed by a vertically downward anisotropic etch, and the electron transport layer 720 is again exposed, leaving the isolation layers on the sidewalls. The sidewalls 7261 of the spacer layer 725, the sidewalls 7262 within the openings of the electron transport layer 720, and the sidewalls 7263 of the hole transport layer 720 and the spacer layer 725 are included. Since the etching speed is slower in parallel with the vertically downward etching direction, the respective side walls 7261-7263 are retained.

As shown in FIG. 7g, an N-electrode 727 is formed on the exposed electron transport layer 720. The N-electrode 727 is electrically connected to the electron transport layer 720. Due to the protection of the

spacer sidewalls

7261 and 7263, the N-electrode 726 and the electron transport layer 720 and the hole transport layer 722, the radiation composite layer 721, and the P-electrode 723 form a good electrical insulation and electrical activity of the etched surface. Passivation. Further, a portion of the insulating layer and the nucleation layer are removed while a portion of the Si substrate is exposed.

As shown in FIG. 7h, mutually spaced doped regions 701 and doped regions 702 and spacer regions 703 therebetween are formed on the exposed Si substrate.

As shown in Fig. 7i, an isolation layer 704 is formed over the entire Si substrate. Two openings are then formed on the doped region 701 and the doped region 702, respectively.

As shown in FIG. 7j, a transistor 705 and a transistor 706 are formed in the openings of the doped region 701 and the doped region 702, respectively; wherein the transistor 705 includes a drain 7051, a gate 7052, and a source 7053. Transistor 706 includes a drain 7061, a gate 7062, and a source 7063.

As shown in FIG. 7k, a spacer layer 707 is formed on the entire Si substrate. Then, an opening is formed on the spacer layer 707 to expose the drain 7051 and the source 7053 of the transistor 705. At the same time, the spacer layer 725, the spacer layer 704, and a portion of the spacer layer 707 on the extended portion 724 of the P-electrode 723 on the insulating layer are removed, and a portion of the P-electrode 723 is exposed.

As shown in FIG. 71, a conductive material layer 708 and a conductive material layer 709 are formed, wherein the conductive material layer 708 electrically connects the exposed P-electrode 723 with the drain 7051 of the transistor 705; the conductive material layer 709 electrically connects the source of the transistor 705. The pole 7053, and the conductive material layer 709 partially covers the spacer 703 between the doped region 701 and the doped region 702.

As shown in Fig. 7m, a spacer layer 710 is formed over the entire Si substrate. Then, the spacer layer 710 is partially removed, and the gate 7052 of the transistor 705 and the drain 7061 of the transistor 706 are exposed.

As shown in FIG. 7n, a conductive material layer 711 is formed in which the conductive material layer 711 electrically connects the gate 7052 of the transistor 705 and the drain 7061 of the transistor 706, and the conductive material layer 711 partially covers the conductive material layer 709. Thereby, the conductive material layer 709 and the conductive material layer 711 are spaced apart from each other by the layer 710, thereby forming a capacitor 712.

Referring to FIG. 7n, the transistor 705 can function as a driving transistor to drive the LED light emitting structure; the transistor 707 can function as a gate transistor; and the capacitor 712 can function as a storage capacitor to form the driving circuit of the active addressing mode of FIG.

In this embodiment, a thinner nitride nucleation layer is grown only on the Si substrate, and then a hole is formed in the insulating layer thereon to expose the nitride nucleation layer. The LED epitaxial layer structure is grown on the exposed nucleation layer by a method of epitaxial extension. Since the LED epitaxial layer covers only a portion of the Si substrate, the probability of cracking of the epitaxial layer or wafer caused by stress is greatly reduced, wafer warpage is reduced, temperature uniformity, and product yield are significantly improved.

Further, it is not necessary in the present embodiment to etch all of the LED epitaxial layers other than the non-LED light emitting structure regions. This embodiment can further reduce the cost of the process due to the difficulty in etching the GaN-based material. At the same time, since the etched surface has a high non-radiative recombination center density, this may result in a decrease in luminous efficiency of the LED light-emitting structure; and the LED light-emitting structure of the present embodiment does not include an etched surface, which avoids this.

Figure 8 is a block diagram showing the structure of an LED display unit in accordance with still another embodiment of the present invention. Compared to Figure 7m, the embodiment shown in Figure 8 differs in that only the local silicon surface contains a nitride nucleation layer. According to an embodiment of the present invention, an insulating layer is formed on a Si substrate, an opening is formed in the insulating layer, and then a nitride nucleation layer is grown, and a lower quality nucleation layer grown on the insulating layer is removed. . According to another embodiment of the present invention, a nitride nucleation layer is uniformly grown on a Si substrate, a nitride nucleation layer is patterned to form a plurality of separated nitride nucleation layer cores, and then a long insulating layer is regenerated, and A portion of the insulating layer is removed to expose the nitride nucleation layer. The other parts of the embodiment of Fig. 8 are similar to the embodiment of Fig. 7, and are not described again here.

The embodiment of Figure 8 further reduces the stresses that may result from the direct growth of a uniform nitride semiconductor on silicon, thereby further increasing the yield of the product.

9 is a flow chart of a method of fabricating an LED display structure in accordance with an embodiment of the present invention. As shown, the manufacturing method includes the following steps:

At step 910, a P-electrode and an N-electrode are formed on the LED epitaxial structure on the substrate, wherein the LED epitaxial structure includes a nucleation layer, an electron transport layer, a radiation composite layer, and a hole transport layer.

At step 920, at least one transistor is formed on the substrate.

At step 930, the P-electrode or N-electrode is electrically coupled to at least one of the plurality of transistors. According to an embodiment of the invention, the source and the drain of the transistor may be connected between the power source and the LED lighting structure. The LED light-emitting structure and the transistor can be connected differently through different circuit designs. Thus, although in most embodiments herein a P-electrode is exemplified, either the P-electrode or the N-electrode can be an electrode directly connected to the transistor.

According to an embodiment of the present invention, the forming the N-electrode may include: removing a portion of the radiation composite layer and the hole transport layer, exposing the electron transport layer; partially removing the exposed electron transport layer and the nucleation layer, exposing the a substrate; and forming an N-electrode on the remaining electron transport layer.

According to an embodiment of the present invention, the method may further include: forming an insulating layer covering at least the P-electrode and the N-electrode.

10 is a flow chart of a method of fabricating an LED display structure in accordance with another embodiment of the present invention. As shown, the manufacturing method includes the following steps:

At step 1010, a P-electrode and an N-electrode are formed on the LED epitaxial structure on the substrate, wherein the LED epitaxial structure comprises: a nucleation layer; an insulating layer including an opening to expose a portion of the nucleation layer; and the exposed portion An electron transport layer core extending from the nucleation layer; and a radiation composite layer and a hole transport layer on the core of the electron transport layer.

At step 1020, at least one transistor is formed on the substrate.

At step 1030, a P-electrode or N-electrode is electrically coupled to the at least one transistor.

According to an embodiment of the invention, forming the P-electrode in the method comprises forming a P-electrode on the hole transport layer, wherein at least a portion of the P-electrode extends over the insulating layer.

According to an embodiment of the invention, forming the N-electrode in the method comprises removing a portion of the radiation composite layer and the hole transport layer, exposing the electron transport layer core; forming an N-electrode on the exposed electron transport layer core.

11 is a flow chart of a method of fabricating an LED display structure in accordance with another embodiment of the present invention. As shown, the manufacturing method includes the following steps:

At step 1110, a P-electrode and an N-electrode are formed on the epitaxial structure of the LED on the substrate, wherein the epitaxial structure of the LED comprises: an insulating layer including an opening; a nucleation layer located in the opening of the insulating layer; a layer extending electron transport layer core; and a radiation composite layer and a hole transport layer on the electron transport layer core.

At step 1120, at least one transistor is formed on the substrate.

At step 1130, a P-electrode or N-electrode is electrically coupled to the at least one transistor.

12 is a flow chart of a method of fabricating an LED display structure in accordance with another embodiment of the present invention. As shown, the manufacturing method includes the following steps:

At step 1210, a plurality of P-electrodes and a plurality of N-electrodes are formed on the plurality of LED epitaxial structures on the substrate, wherein the LED epitaxial structure comprises a nucleation layer, an electron transport layer, a radiation recombination layer, and a hole transport layer;

At step 1220, at least one transistor is formed on the substrate.

At step 1230, a P-electrode or N-electrode is electrically coupled to the at least one transistor.

Figure 13 is a flow chart of a method of fabricating an LED display structure in accordance with another embodiment of the present invention. As shown, the manufacturing method includes the following steps:

At step 1310, a plurality of P-electrodes and a plurality of N-electrodes are formed on the plurality of LED epitaxial structures on the substrate, wherein the LED epitaxial structure comprises: a nucleation layer; an insulating layer including an opening to expose a portion of the nucleation layer An electron transport layer core extending from the exposed partial nucleation layer; and a radiation composite layer and a hole transport layer on the core of the electron transport layer.

At step 1320, at least one transistor is formed on the substrate.

At step 1330, a P-electrode or N-electrode is electrically coupled to the at least one transistor.

14 is a flow chart of a method of fabricating an LED display structure in accordance with another embodiment of the present invention. As shown, the manufacturing method includes the following steps:

At step 1410, a plurality of P-electrodes and a plurality of N-electrodes are formed on the plurality of LED epitaxial structures on the substrate, wherein the LED epitaxial structure comprises: an insulating layer including an opening; and a nucleation layer located on the insulating layer In the opening; an electron transport layer core extending from the nucleation layer; and a radiation composite layer and a hole transport layer on the core of the electron transport layer.

At step 1420, at least one transistor is formed on the substrate.

At step 1430, a P-electrode or N-electrode is electrically coupled to the at least one transistor.

The above-described embodiments are merely illustrative of the invention, and are not intended to limit the invention, and various changes and modifications can be made by those skilled in the art without departing from the scope of the invention. Equivalent technical solutions are also within the scope of the present disclosure.

Claims

An LED display unit comprising:

Substrate

An LED region on the substrate that includes an LED illumination structure;

a circuit region on the substrate comprising at least one transistor;

Wherein the at least one transistor is electrically connected to the LED lighting structure.
The LED display unit of claim 1, wherein the at least one transistor comprises a first transistor; the source and drain of the first transistor are connected between a power supply and an LED lighting structure.
The LED display unit according to claim 1, wherein said at least one transistor comprises a second transistor; wherein a gate of the second transistor is connected to the row scan signal, and a source and a drain of the second transistor are connected to the column scan signal Between the LED lighting structure.
The LED display unit of claim 1, wherein the at least one transistor comprises a first transistor, a second transistor, and a capacitor; a source and a drain of the first transistor are connected between the power source and the LED light emitting structure; The gate is connected to the row scan signal, the source of the second transistor is connected to the column scan signal, the drain of the second transistor is connected to the gate of the first transistor, and the capacitor is connected between the gate of the second transistor and the power source.
The LED display unit of claim 1, wherein the LED light emitting structure comprises a GaN-based LED light emitting structure.
The LED display unit of claim 5, wherein the LED light emitting structure comprises an overlapping electron transport layer, a radiation composite layer, and a hole transport layer.
The LED display unit of claim 5, wherein the LED light emitting structure comprises a nucleation layer, an electron transport layer core on the partial nucleation layer, and a radiation composite layer and a hole transport layer on the electron transport layer core.
The LED display unit of claim 7, wherein the LED light emitting structure further comprises an insulating layer on the nucleation layer, wherein the insulating layer includes an opening to expose the portion of the nucleation layer.
The LED display unit of claim 5, wherein the LED light emitting structure comprises a nucleation layer core, an electron transport layer core on the core of the nucleation layer, and a radiation composite layer and a hole transport layer on the core of the electron transport layer.
The LED display unit of claim 9, wherein the LED light emitting structure further comprises an insulating layer, wherein the core of the nucleation layer is located in the opening of the insulating layer.
An LED display unit comprising:

Substrate

An LED region on the substrate, which includes an LED light emitting structure;

a first doped region on the substrate, including a first transistor;

The source and the drain of the first transistor are connected between the power source and the LED light emitting structure.
The LED display unit of claim 11 further comprising a second doped region on the substrate comprising a second transistor; the source or drain of the second transistor being coupled to the gate of the first transistor.
The LED display unit of claim 12, further comprising a capacitor formed on a region outside the first doped region and the second doped region.
An LED display comprising:

Substrate

a plurality of LED light emitting structures on the substrate;

a plurality of transistors on the substrate;

Wherein at least one of the plurality of transistors is connected to the LED light emitting structure.
An LED display comprising:

Substrate;

a matrix of LEDs on a substrate comprising a plurality of LED display units arranged in rows and columns;

Wherein, the LED display unit comprises:

An LED region on the substrate that includes an LED illumination structure;

a circuit region on the substrate comprising at least one transistor;

Wherein the at least one transistor is electrically connected to the LED lighting structure.
An LED display comprising:

Substrate;

a matrix of LEDs on a substrate comprising a plurality of LED display units arranged in rows and columns;

Wherein, the LED display unit comprises:

a first doped region on the substrate, including a first transistor;

An undoped region on the substrate, which includes an LED light emitting structure;

The source and the drain of the first transistor are connected between the power source and the LED light emitting structure.