CN116613084A - Chip, test machine, calibration method of internal comparator of chip and related equipment - Google Patents
Chip, test machine, calibration method of internal comparator of chip and related equipment Download PDFInfo
- Publication number
- CN116613084A CN116613084A CN202310874988.3A CN202310874988A CN116613084A CN 116613084 A CN116613084 A CN 116613084A CN 202310874988 A CN202310874988 A CN 202310874988A CN 116613084 A CN116613084 A CN 116613084A
- Authority
- CN
- China
- Prior art keywords
- chip
- comparator
- calibration
- output
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000012360 testing method Methods 0.000 title claims abstract description 38
- 230000006854 communication Effects 0.000 claims abstract description 25
- 238000004891 communication Methods 0.000 claims abstract description 24
- 238000004590 computer program Methods 0.000 claims description 10
- 238000011161 development Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention is suitable for the technical field of chip processes, and particularly relates to a calibration method and related equipment for a chip, a test machine and a comparator in the chip. The invention provides a comparator calibration method based on chip internal circuit realization, a corresponding chip and a test machine, wherein the test machine and the chip have less communication content and short communication time in the calibration method, and the calibration scheme based on sequential traversal logic realization can reduce the development burden of the chip internal circuit, improve the calibration accuracy and shorten the calibration time.
Description
Technical Field
The invention is suitable for the technical field of chip processes, and particularly relates to a calibration method and related equipment for a chip, a test machine and a comparator in the chip.
Background
Due to variations in the dimensions, doping concentrations, etc. during wafer fabrication, after integrated circuits (Integrated Circuit Chip, ICs) such as chips are fabricated, there may be a certain mismatch of the differential pair tubes inside, resulting in a certain offset (offset) of the comparator. In some chips with high precision requirements, the calibration of the comparator is required before shipment in order to achieve the expected parameter performance of the product and good consistency. The principle of calibration is to add a threshold deviation that can be adjusted manually, by which the actual deviation generated during manufacture is counteracted.
In the related art, two input pins of a comparator are generally shortened in a chip, then a register of the chip is operated by an external test machine to adjust a threshold deviation according to a certain logic, and whether calibration is completed is determined according to the flip condition of the output of the comparator, as shown in fig. 1.
Based on the calibration environment of fig. 1, the related art generally performs comparator calibration using two methods:
1. the logic to operate the chip registers from the external test bench is a walk through, by operating the register values to walk through from all 0 s to all 1 s (or from all 1 s to all 0 s), and determining the comparator output each time, stopping the walk through when the comparator output toggles.
2. The logic of the machine operation IC register is 'dichotomy', and the machine decides whether each bit of the register is 0 or 1 according to the turnover condition of the output of the comparator. This approach greatly shortens the test time and registers several times with several bits of register.
However, the above method has the following problems:
for the first mode, as the chip clamp and the machine are connected by a long flexible flat cable and are easy to interfere, the communication rate is not very high, and the traversing operation has a large number of communication processes for modifying the register, the worst case of the 5bit register needs 32 times of communication for modifying the register, the average case also needs 16 times of communication, the communication time is multiplied when the register is increased by 1bit, in addition, the IO port is connected to the machine by a long path, in order to ensure accurate results, a period of anti-shake (debounce) time is needed to be added in the related technology, the single anti-shake time is fixed, the total anti-shake time is in direct proportion to the adjustment times of the register, and therefore, the total anti-shake time is multiplied when the register is increased by 1 bit;
for the second mode, since the comparator of the chip often has a hysteresis characteristic, the value of each register bit is determined by flipping the comparator back and forth in the dichotomy, which results in that the final value is not necessarily the threshold value of the expected comparator just flipped, thus causing a deviation, which may even be as high as more than ten steps on some comparators with hysteresis made larger.
Therefore, there is a need for a new calibration system and method for chip comparators that addresses the above-mentioned issues.
Disclosure of Invention
The invention provides a chip, a test machine, a calibration method of an internal chip comparator and related equipment, and aims to solve the technical problems that the method for calibrating the internal chip comparator is limited by flat cable connection and binary traversal logic, so that the waiting time is long and the communication time is long in the prior art.
In a first aspect, an embodiment of the present invention provides a chip, which can be calibrated by a test machine, where the chip includes a comparison module, a switch module, and a control module, the comparison module includes a comparator to be calibrated, an input end of the comparison module is connected to the switch module, and an output end of the comparison module is connected to the control module, where:
the switch module is used for acquiring a calibration starting signal, carrying out short circuit connection on the input end of the comparator according to the calibration starting signal, and carrying out open circuit connection on the input end of the comparator according to a calibration finishing signal; the calibration starting signal is sent by the test machine, and the calibration completion signal is generated by the control module when the output of the comparator is overturned;
the control module is used for traversing the register value of the chip and outputting the register value to the comparator, and judging whether the register value enables the output of the comparator to be inverted or not: if yes, releasing the calibration completion signal to the switch module and the test machine, and storing the register value which enables the output of the comparator to be overturned so as to complete the calibration of the comparator; if not, continuing to output the traversal of the register value;
the comparison module is used for adjusting the deviation value of the comparator according to the register value.
Further, when the switch module is in open circuit connection, the output of the comparator remains unchanged.
Furthermore, the switch module is a MOS tube, the source electrode and the drain electrode of the MOS tube are respectively connected with the input end of the comparator, and the grid electrode of the MOS tube is connected with the output end of the control module.
Still further, the control module includes a first output terminal connected to the switch module to transmit the calibration complete signal, and a second output terminal connected to the comparison module to transmit the register value.
In a second aspect, an embodiment of the present invention further provides a test machine, configured to calibrate a comparator in a chip, where the test machine includes a machine communication module, where the machine communication module is configured to send a calibration start signal to the chip according to an instruction, and receive a calibration end signal returned by the chip.
In a third aspect, an embodiment of the present invention further provides a calibration system for an on-chip comparator, where the calibration system includes a chip and a test bench according to any one of the above.
In a fourth aspect, an embodiment of the present invention further provides a calibration method of an on-chip comparator, the calibration method being implemented based on the chip as set forth in any one of the preceding claims, the calibration method comprising the steps of:
s11, receiving the calibration start signal in a switch module of the chip, and carrying out short-circuit connection on the input end of the comparator;
s12, traversing the register value of the chip in a control module of the chip and outputting the traversed register value to the comparator;
s13, judging whether the register value causes the output of the comparator to flip or not in a control module of the chip: if yes, releasing the calibration completion signal, executing step S14, and if not, returning to step S12;
s14, stopping traversing output of the register value in a control module of the chip, carrying out open circuit connection on the input end of the comparator according to the calibration completion signal, and storing the register value which enables output of the comparator to be overturned so as to complete calibration of the comparator.
In a fifth aspect, an embodiment of the present invention further provides a calibration method of an on-chip comparator, where the calibration method is implemented based on the test machine as described above, and the calibration method includes the following steps:
s21, inputting an instruction into a machine communication module of the test machine to send a calibration start signal to a chip containing a comparator to be calibrated so as to start parameter calibration;
s22, receiving a calibration end signal through the machine communication module, and ending parameter calibration, wherein the calibration end signal is sent out when the calibration of the comparator is completed.
In a sixth aspect, an embodiment of the present invention further provides a computer apparatus, including: memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps in the method of calibrating an on-chip comparator as claimed in any one of the preceding claims when the computer program is executed.
In a seventh aspect, embodiments of the present invention further provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps in the method of calibrating an on-chip comparator as described in any of the above.
The invention has the beneficial effects that the invention provides the comparator calibration method based on the chip internal circuit, the corresponding chip and the test machine, the test machine and the chip are less in communication content and short in communication time in the calibration method, and the calibration scheme based on the logic implementation of sequential traversal can not only reduce the development burden of the chip internal circuit, but also improve the calibration accuracy and shorten the calibration time.
Drawings
FIG. 1 is a schematic diagram of a prior art implementation of on-chip comparator calibration;
FIG. 2 is a schematic diagram of a calibration system for an on-chip comparator according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a calibration method of an on-chip comparator according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating steps of another method for calibrating an on-chip comparator according to an embodiment of the present invention
Fig. 5 is a schematic structural diagram of a computer device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1
The embodiment of the invention provides a chip 100, which can be calibrated by a test machine 200, wherein the chip 100 comprises a comparison module 101, a switch module 102 and a control module 103, the comparison module 101 comprises a comparator to be calibrated, the input end of the comparison module 101 is connected with the switch module 102, and the output end of the comparison module 101 is connected with the control module 103, wherein:
the switch module 102 is configured to obtain a calibration start signal, short-circuit the input end of the comparator according to the calibration start signal, and open-circuit the input end of the comparator according to a calibration completion signal; wherein, the calibration start signal is sent by the test machine 200, and the calibration completion signal is generated by the control module 103 when the output of the comparator is flipped;
the control module 103 is configured to output the register value of the chip to the comparator in a traversing manner, and determine whether the register value causes the output of the comparator to flip: if yes, releasing the calibration completion signal to the switch module 102 and the test machine 200, and saving the register value for enabling the output of the comparator to be inverted, so as to complete the calibration of the comparator; if not, continuing to output the traversal of the register value;
the comparison module 101 is configured to adjust an offset value of the comparator according to the register value.
Still further, the output of the comparator remains unchanged when the switch module 102 is an open circuit connection.
Further, the switch module 102 is a MOS transistor, a source and a drain of the MOS transistor are respectively connected to the input end of the comparator, and a gate of the MOS transistor is connected to the output end of the control module 103. In the embodiment of the present invention, the comparison module 101 and the control module 103 may be implemented by multiplexing structures except that the switch module 102 has a specific structure, so as to save hardware resources.
Still further, the control module 103 includes a first output terminal connected to the switch module 102 for transmitting the calibration complete signal, and a second output terminal connected to the comparison module 101 for transmitting the register value.
Specifically, in the embodiment of the present invention, for the comparator to be calibrated, only the control module 103 determines the register value to perform the cyclic comparison, so that in the actual implementation process, if the circuit structure can be implemented, the chip 100 provided in the embodiment of the present invention may also perform the process of calibrating multiple comparators at the same time.
Example two
The embodiment of the invention further provides a test machine 200 for calibrating the comparator in the chip, wherein the test machine 200 comprises a machine communication module 201, and the machine communication module 201 is configured to send a calibration start signal to the chip 100 according to an instruction and receive a calibration end signal returned by the chip 100.
Example III
Referring to fig. 2, fig. 2 is a schematic structural diagram of a calibration system 300 for an internal chip comparator according to an embodiment of the present invention, where the calibration system includes a chip 100 and a test bench 200 as described in the above embodiments.
In the calibration system 300 of the on-chip comparator according to the embodiment of the present invention, the calibration start signal and the calibration end signal are transmitted between the chip 100 and the test machine 200 through one transmission channel, and the calibration start signal and the calibration end signal are irrelevant to the accuracy of the calibration of the comparator, and because the transmission is completed only at the moment of the start and the end of the calibration, the communication time caused by the process is negligible, and compared with the prior art, the data interference of the long flat cable can be avoided, the calibration time is reduced, and the implementation flow of the calibration is simplified.
Example IV
An embodiment of the present invention further provides a method for calibrating an internal chip comparator, referring to fig. 3, fig. 3 is a schematic flow chart of steps of the method for calibrating an internal chip comparator according to the embodiment of the present invention, where the method for calibrating an internal chip comparator is implemented based on the chip 100 as described in any one of the above, and the method for calibrating an internal chip comparator includes the following steps:
s11, receiving the calibration start signal in a switch module 102 of the chip 100, and performing short-circuit connection on the input end of the comparator;
s12, traversing the register value of the chip in the control module 103 of the chip 100 and outputting the traversed register value to the comparator;
s13, judging whether the register value causes the output of the comparator to flip or not in the control module 103 of the chip 100: if yes, releasing the calibration completion signal, executing step S14, and if not, returning to step S12;
s14, stopping traversing output of the register value in the control module 103 of the chip 100, carrying out open circuit connection on the input end of the comparator according to the calibration completion signal, and storing the register value which enables output of the comparator to be inverted so as to complete calibration of the comparator.
In step S13, the output register value is traversed, so that the comparator output is turned over when the threshold value of the comparator reaches the value that just enables the output to be turned over, and calibration of the comparator is completed at this time.
Example five
The embodiment of the present invention further provides a calibration method of an internal chip comparator, please refer to fig. 4, fig. 4 is a schematic step flow diagram of another calibration method of an internal chip comparator provided in the embodiment of the present invention, the calibration method is implemented based on the test bench 200 described above, and the calibration method includes the following steps:
s21, inputting an instruction into a machine communication module 201 of the test machine 200 to send a calibration start signal to a chip containing a comparator to be calibrated so as to start parameter calibration;
s22, receiving a calibration end signal through the machine communication module 201, and ending parameter calibration, wherein the calibration end signal is sent out when the calibration of the comparator is completed.
The invention has the beneficial effects that the invention provides the comparator calibration method based on the chip internal circuit, the corresponding chip and the test machine, the test machine and the chip are less in communication content and short in communication time in the calibration method, and the calibration scheme based on the logic implementation of sequential traversal can not only reduce the development burden of the chip internal circuit, but also improve the calibration accuracy and shorten the calibration time.
Example six
An embodiment of the present invention further provides a computer device, referring to fig. 5, fig. 5 is a schematic structural diagram of the computer device provided in the embodiment of the present invention, including: the steps in the method for calibrating an on-chip comparator according to any one of the fourth or fifth embodiments are implemented when the processor executes the computer program, and the same technical effects can be achieved, and the description of the above embodiments is omitted herein.
Example seven
The embodiment of the present invention further provides a computer readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps in the method for calibrating an on-chip comparator described in the fourth or fifth embodiment, and can implement the same technical effects, which are not described in detail herein, with reference to the description of the foregoing embodiment.
Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM) or the like.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method according to the embodiments of the present invention.
While the embodiments of the present invention have been illustrated and described in connection with the drawings, what is presently considered to be the most practical and preferred embodiments of the invention, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various equivalent modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (10)
1. The utility model provides a chip, can be by the calibration of a test bench comparator, its characterized in that, the chip includes comparison module, switch module, control module, comparison module includes the comparator of waiting to calibrate, the input of comparison module is connected switch module, the output of comparison module is connected control module, wherein:
the switch module is used for acquiring a calibration starting signal, carrying out short circuit connection on the input end of the comparator according to the calibration starting signal, and carrying out open circuit connection on the input end of the comparator according to a calibration finishing signal; the calibration starting signal is sent by the test machine, and the calibration completion signal is generated by the control module when the output of the comparator is overturned;
the control module is used for traversing the register value of the chip and outputting the register value to the comparator, and judging whether the register value enables the output of the comparator to be inverted or not: if yes, releasing the calibration completion signal to the switch module and the test machine, and storing the register value which enables the output of the comparator to be overturned so as to complete the calibration of the comparator; if not, continuing to output the traversal of the register value;
the comparison module is used for adjusting the deviation value of the comparator according to the register value.
2. The chip of claim 1, wherein the output of the comparator remains unchanged when the switch module is an open circuit connection.
3. The chip of claim 1, wherein the switch module is a MOS transistor, a source and a drain of the MOS transistor are respectively connected to the input end of the comparator, and a gate of the MOS transistor is connected to the output end of the control module.
4. The chip of claim 1, wherein the control module includes a first output coupled to the switch module to transmit the calibration complete signal and a second output coupled to the compare module to transmit the register value.
5. The test machine is used for calibrating a comparator in a chip and is characterized by comprising a machine communication module, wherein the machine communication module is used for sending a calibration start signal to the chip according to an instruction and receiving a calibration end signal returned by the chip.
6. A calibration system for an on-chip comparator, comprising a chip according to any one of claims 1-4 and a test station according to claim 5.
7. A method of calibrating an on-chip comparator, the method being implemented on the basis of a chip as claimed in any one of claims 1-4, the method comprising the steps of:
s11, receiving the calibration start signal in a switch module of the chip, and carrying out short-circuit connection on the input end of the comparator;
s12, traversing the register value of the chip in a control module of the chip and outputting the traversed register value to the comparator;
s13, judging whether the register value causes the output of the comparator to flip or not in a control module of the chip: if yes, releasing the calibration completion signal, executing step S14, and if not, returning to step S12;
s14, stopping traversing output of the register value in a control module of the chip, carrying out open circuit connection on the input end of the comparator according to the calibration completion signal, and storing the register value which enables output of the comparator to be overturned so as to complete calibration of the comparator.
8. A method of calibrating an on-chip comparator, the method being implemented on the basis of the test station of claim 5, the method comprising the steps of:
s21, inputting an instruction into a machine communication module of the test machine to send a calibration start signal to a chip containing a comparator to be calibrated so as to start parameter calibration;
s22, receiving a calibration end signal through the machine communication module, and ending parameter calibration, wherein the calibration end signal is sent out when the calibration of the comparator is completed.
9. A computer device, comprising: memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps in the method of calibrating an on-chip comparator according to claim 7 or 8 when the computer program is executed.
10. A computer readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the method for calibrating an on-chip comparator according to claim 7 or 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310874988.3A CN116613084B (en) | 2023-07-17 | 2023-07-17 | Chip, test machine, calibration method of internal comparator of chip and related equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310874988.3A CN116613084B (en) | 2023-07-17 | 2023-07-17 | Chip, test machine, calibration method of internal comparator of chip and related equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116613084A true CN116613084A (en) | 2023-08-18 |
| CN116613084B CN116613084B (en) | 2024-02-23 |
Family
ID=87680409
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310874988.3A Active CN116613084B (en) | 2023-07-17 | 2023-07-17 | Chip, test machine, calibration method of internal comparator of chip and related equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116613084B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6298465B1 (en) * | 1998-06-29 | 2001-10-02 | Process Intelligence Limited | Skew calibration means and a method of skew calibration |
| WO2006132821A2 (en) * | 2005-06-06 | 2006-12-14 | Atmel Corporation | Output level voltage regulation |
| US20080304608A1 (en) * | 2007-06-07 | 2008-12-11 | Advantest Corporation | Test apparatus, and device for calibration |
| CN102354265A (en) * | 2011-06-28 | 2012-02-15 | 埃派克森微电子(上海)股份有限公司 | Device and method for detecting key |
| CN105049043A (en) * | 2015-06-30 | 2015-11-11 | 北京时代民芯科技有限公司 | High-speed comparator with offset correction function |
| US20160233846A1 (en) * | 2013-09-27 | 2016-08-11 | Cristian Pavao-Moreira | Integrated calibration circuit and a method for calibration of a filter circuit |
| CN115480234A (en) * | 2021-06-15 | 2022-12-16 | 上海禾赛科技有限公司 | Voltage calibration method, circuit, laser radar system and storage medium |
| CN115542132A (en) * | 2022-11-28 | 2022-12-30 | 深圳市鹏芯数据技术有限公司 | SOC (system on chip) built-in test circuit, SOC and test method |
-
2023
- 2023-07-17 CN CN202310874988.3A patent/CN116613084B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6298465B1 (en) * | 1998-06-29 | 2001-10-02 | Process Intelligence Limited | Skew calibration means and a method of skew calibration |
| WO2006132821A2 (en) * | 2005-06-06 | 2006-12-14 | Atmel Corporation | Output level voltage regulation |
| US20080304608A1 (en) * | 2007-06-07 | 2008-12-11 | Advantest Corporation | Test apparatus, and device for calibration |
| CN102354265A (en) * | 2011-06-28 | 2012-02-15 | 埃派克森微电子(上海)股份有限公司 | Device and method for detecting key |
| US20160233846A1 (en) * | 2013-09-27 | 2016-08-11 | Cristian Pavao-Moreira | Integrated calibration circuit and a method for calibration of a filter circuit |
| CN105049043A (en) * | 2015-06-30 | 2015-11-11 | 北京时代民芯科技有限公司 | High-speed comparator with offset correction function |
| CN115480234A (en) * | 2021-06-15 | 2022-12-16 | 上海禾赛科技有限公司 | Voltage calibration method, circuit, laser radar system and storage medium |
| CN115542132A (en) * | 2022-11-28 | 2022-12-30 | 深圳市鹏芯数据技术有限公司 | SOC (system on chip) built-in test circuit, SOC and test method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116613084B (en) | 2024-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11340286B2 (en) | On-wafer S-parameter calibration method | |
| EP3930075A1 (en) | Battery pack ocv-soc curve update method, battery management system and vehicle | |
| CN113159324B (en) | Quantum device calibration method, device and medium | |
| CN116613084B (en) | Chip, test machine, calibration method of internal comparator of chip and related equipment | |
| CN112202507A (en) | WIFI production measurement and calibration method and computer-readable storage medium | |
| CN111432428A (en) | Measuring method and device | |
| WO2023165293A1 (en) | Channel state information updating method, base station, device, and storage medium | |
| CN102385641A (en) | Correction method for device dismatch of bipolar transistor | |
| CN115356561B (en) | Line loss calibration method, system, electronic device and computer readable storage medium | |
| CN112257363B (en) | Memory selection method and device | |
| CN112632887B (en) | Clock delay adjusting method and device of memory, storage medium and terminal | |
| WO2023010499A1 (en) | Radio resource management measurement method and apparatus | |
| CN114063758A (en) | Current value obtaining method, device and medium | |
| CN114024882B (en) | Router performance test method, device, system and storage medium | |
| CN111651157A (en) | Python-based PoE instrument packaging method | |
| Casparsen et al. | Bluetooth Low Energy with Software-Defined Radio: Proof-of-Concept and Performance Analysis | |
| CN116598218A (en) | Chip, test machine, calibration system and method of chip parameters and related equipment | |
| WO2024016622A1 (en) | Timeout parameter determination method and apparatus and communication device | |
| WO2023206634A1 (en) | Calibration control circuit, electronic device and calibration control method | |
| CN114070514B (en) | Control information receiving processing method and device, electronic equipment and storage medium | |
| CN117110707B (en) | SOC integrated chip, frequency measurement circuit and frequency measurement method | |
| US11984895B2 (en) | Calibration method and calibration apparatus for delay of quantum computer system | |
| CN115130422B (en) | Automatic construction method and device for standard unit, terminal and storage medium | |
| TWI763174B (en) | Parameter correction method and semiconductor device utilizing the same | |
| CN105955724B (en) | A kind of call method and device of terminal parameter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |