CN112257363B - Memory selection method and device - Google Patents
Memory selection method and device Download PDFInfo
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- CN112257363B CN112257363B CN202011187259.3A CN202011187259A CN112257363B CN 112257363 B CN112257363 B CN 112257363B CN 202011187259 A CN202011187259 A CN 202011187259A CN 112257363 B CN112257363 B CN 112257363B
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/337—Design optimisation
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Abstract
A method for selecting a memory includes the following steps. According to the test model, a plurality of first parameters of the reference memory are obtained. According to the first parameters, parameter extraction is carried out on a memory to obtain a plurality of second parameters of the memory. And comparing the first parameters with the second parameters to determine whether the memory is qualified, determining that the memory is qualified when the second parameters of the memory are respectively less than or equal to the corresponding first parameters, and determining that the memory is unqualified when any one of the second parameters of the memory is greater than the corresponding first parameters.
Description
Technical Field
The present invention relates to a selection method and apparatus, and more particularly, to a method and apparatus for selecting a memory.
Background
Generally, for the conventional back-end design, the physical design can be performed only according to the memory (e.g., static Random Access Memory (SRAM)) provided by the front-end. However, the memory provided by the front end only meets the basic functional requirements, and does not relate to the problems of time sequence, physical size and the like. Therefore, the problem that the timing convergence of a plurality of critical paths connected with the memory is difficult to realize is caused, and a back-end engineer needs to take a lot of time to repeatedly modify and continuously manually optimize the timing.
Therefore, how to select an appropriate memory efficiently becomes a topic to be researched by various manufacturers.
Disclosure of Invention
The invention provides a method and a device for selecting a memory, which are used for quickly selecting a proper memory (namely, the memory meeting the design requirement), so that the time can be saved when a back end optimizes a critical path comprising the memory, and the convenience in use is improved.
The invention provides a method for selecting a memory, which comprises the following steps. According to the test model, a plurality of first parameters of the reference memory are obtained. And extracting parameters of a memory according to the first parameters to obtain a plurality of second parameters of the memory. And comparing the first parameters with the second parameters to determine whether the memory is qualified, determining that the memory is qualified when the second parameters of the memory are respectively less than or equal to the corresponding first parameters, and determining that the memory is unqualified when any one of the second parameters of the memory is greater than the corresponding first parameters.
The invention provides a memory selection device, which comprises a test device, an extraction device, a comparison device and a processing device. The test device obtains a plurality of first parameters through the test model. The extracting device extracts parameters of a memory according to the first parameters to obtain a plurality of second parameters of the memory. The comparison device compares whether the second parameters are smaller than or equal to the corresponding first parameters. And the processing device is used for determining whether the memory is qualified or not, determining that the memory is qualified when the second parameters of the memory are respectively less than or equal to the corresponding first parameters, and determining that the memory is unqualified when any one of the second parameters of the memory is greater than the corresponding first parameters.
According to the method and the device for selecting the memory, disclosed by the invention, a plurality of first parameters are obtained through the test model. The method comprises the steps of extracting parameters of a memory to obtain a plurality of second parameters of the memory, comparing the first parameters with the corresponding second parameters to generate comparison results, and determining whether the memory is qualified or not according to the comparison results. Therefore, whether the designed memory is matched with other components in the chip can be quickly judged, so that the memory matched with other components in the chip is selected, the time can be saved when the back end optimizes the design including the memory, and the convenience in use is improved.
Drawings
Fig. 1 is a schematic diagram of a memory selection device 100 according to an embodiment of the invention.
FIG. 2 is a diagram of a test model 200 according to an embodiment of the invention.
FIG. 3A is a schematic diagram of a first portion of the test model of FIG. 2.
FIG. 3B is a schematic diagram of a second portion of the test model of FIG. 2.
Fig. 4 is a flowchart illustrating a method for predicting an operating parameter of an integrated circuit according to an embodiment of the invention.
Fig. 5 is a detailed flowchart of step S402 of fig. 4.
Detailed Description
In each of the embodiments listed below, the same or similar components or parts will be denoted by the same reference numerals.
Fig. 1 is a schematic diagram of a memory selection device 100 according to an embodiment of the invention. Referring to fig. 1, the memory selection apparatus 100 includes a testing apparatus 110, a fetching apparatus 120, a comparing apparatus 130 and a processing apparatus 140. In this embodiment, the memory selection device 100 may be a computing device, such as a notebook computer or a desktop computer. Moreover, the memory selection apparatus 100 of the present embodiment is adapted to select an appropriate memory according to design requirements, so as to provide a reference for a back-end designer to select a memory.
FIG. 2 is a diagram of a test model 200 according to an embodiment of the invention. The testing apparatus 110 performs a path timing analysis on the reference memory 210 through the test model 200 to obtain a plurality of timing parameters of the reference memory 210. In this embodiment, the reference memory 210 is a virtual memory that satisfies the requirements of the test model 200 and is used to select a qualified memory from a plurality of candidate memories. The alternative Memory is, for example, a Static Random Access Memory (SRAM), but the invention is not limited thereto.
As shown in fig. 2, in the present embodiment, the test model 200 includes a reference memory 210, a first buffer 220, a first D flip-flop 230, a first logic unit 240, a second buffer 250, a second logic unit 260, a second D flip-flop 270, and a third buffer 280. The connection relationships among the reference memory 210, the first buffer 220, the first D flip-flop 230, the first logic unit 240, the second buffer 250, the second logic unit 260, the second D flip-flop 270, and the third buffer 280 are shown in fig. 2, and are not described herein again. In this embodiment, the first logic 240 and the second logic 260 may respectively include one or more logic components, such as a buffer, an inverter, and the like. When first logic 240 and second logic 260 include multiple logic components, the logic components may be coupled to each other in series, parallel, or both.
FIG. 3A is a schematic diagram of a first portion of the test model 200 of FIG. 2. As shown in fig. 3A, the testing apparatus 110 may perform a timing analysis on the path of the reference memory 210 at a first process angle and a second process angle respectively through the first portion 310 of the test model 200 to obtain the constraints on the setup time and the hold time required for the data signal to be input into the reference memory 210. The setup time refers to a time that the data signal Din needs to be kept stable before the rising edge of the clock signal Sin arrives, and if the setup time is not enough, the data cannot be stably driven into the reference memory 210 or any register, buffer, or flip-flop at the rising edge of the clock signal Sin. The holding time refers to a time when data is stable after the rising edge of the clock signal Sin arrives, and if the holding time is not enough, the data also cannot be stably transmitted by the reference memory 210 or any register, buffer or flip-flop. In the present embodiment, the first portion 310 of the test model 200 represents a portion of the register (e.g., the first D flip-flop 230) to the reference memory 210. The paths refer to paths from the data signal Din and the clock signal Sin to the reference memory 210. The timing analysis is, for example, static Timing Analysis (STA), the first process corner is, for example, an SS corner (SS corner), and the second process corner is, for example, an FF corner (FF corner).
Due to process variations in the fabrication process, the properties of devices at different locations on the same wafer may vary. An embodiment of the invention employs a model with 5 Process corners (also called Process corners) FF, SS, TT, FS, SF, under which the transistors exhibit different characteristics at each Process Corner, including at least the threshold voltages of the transistors. The process deviation needs to be considered when the path time sequence is carried out, so that the chip can normally work under each process angle, and the designed chip can be reliable. The FF angle refers to a maximum limit value FF of Carrier mobility corresponding to a driving current between the drain and the source of the transistor at the highest level, and the SS angle refers to a minimum limit value SS of Carrier mobility corresponding to a driving current between the drain and the source of the transistor at the lowest level, wherein Carrier mobility refers to an average drift velocity of carriers under a unit electric field.
Referring to FIG. 3A, the first portion 310 of the test model 200 includes a reference memory 210, a first buffer 220, a first D flip-flop 230, a first logic 240, and a second buffer 250. The test apparatus 110 obtains the setup time of the input clock signal Sin to reach the reference memory 210 at the first process corner and the second process corner, respectively.
The test apparatus 110 tests the reference memory 210 at a first process corner (e.g., SS corner), the setup time required for the reference memory 210 to access the data signal Din is Tssetup1, and the test apparatus 110 obtains the time Tarr1 of the data signal Din from the data input D of the first D flip-flop 230 to the input IN of the reference memory 210 and the time Treq1 of the clock signal Sin from the input of the second buffer 250 to the clock input CP of the reference memory 210. The time Tarr1 and the time Treq1 can be represented by the following formulas (1) and (2), respectively.
Tarr1＝Tlaunch1+Tck2q+Tdp1 (1)
Treq1＝Tcycle+Tcapture1-Tssetup1-Tuncertainty+Tcppr (2)
Wherein, the time Tarr1 is a time from the data input terminal D of the first D flip-flop 230 to the data input terminal IN of the reference memory 210, the time Treq1 is a time from the input terminal of the second buffer 250 to the clock input terminal CP of the reference memory 210, tlaunch1 is a delay (latency) generated by the first buffer 220 to the clock signal Sin, tck2q is a time (register transmission time) required by the first D flip-flop 230 to transmit the data signal Din, tdp1 is a time (data path latency) required by the first logic part 240 to transmit the data signal Din, tcycle is a clock period of the clock signal Sin, tcapture1 is a delay generated by the second buffer 250 to the clock signal Sin, tssetup1 is a setup time required by the reference memory 210 to access the data signal Din, tuservicer is an indeterminacy factor to consume the clock signal Sin, and the cancellation time (clock path) is a common path time (elapsed).
According to the formula (1) and the formula (2), the setup time margin tstack 1 is calculated as follows:
Tsslack1＝Treq1-Tarr1
＝Tcycle+Tcapture1-Tuncertainty+Tcppr-Tssetup1-Tlaunch1-Tdp1-Tck2q (3)
to enable the data signal Din to be correctly written into the reference memory 210, the setup time margin tsslew 1 should be greater than or equal to 0. Therefore, equation (3) can be rewritten to equation (4) to obtain the constraint on the setup time Tssetup1 of the reference memory 210.
Tssetup1<＝Tcycle+Tcapture1+Tcppr-Tuncertainty-Tlaunch1-Tdp1-Tck2q (4)
As can be seen from equation (4), since the condition that the setup time margin tstack 1 is equal to or greater than 0 needs to be satisfied, the maximum setup time Tssetup1 corresponding to the reference memory 210 can be obtained according to the sizes of the parameters Tcycle, tcaperture 1, tucertainty, tcppr, tlaunch1, tdp1, and Tck2q that cannot be converged continuously max . Wherein the content of the first and second substances,
Tssetup1 max ＝Tcycle+Tcapture1+Tcppr-Tuncertainty-Tlaunch1-Tdp1-Tck2q (5)
the test apparatus 110 tests the reference memory 210 at a first process corner (for example, FF corner), the retention time required for the reference memory 210 to access the data signal Din is Tshold1, and the test apparatus 110 obtains the time Tarr2 of the data signal Din from the data input D of the first D flip-flop 230 to the input IN of the reference memory 210 and the time Treq2 of the clock signal Sin from the input of the second buffer 250 to the clock input CP of the reference memory 210. The time Tarr2 and the time Treq2 can be represented by the following formulas (6) and (7), respectively:
Tarr2＝Tlaunch1+Tck2q+Tdp1 (6)
Treq2＝Tcapture1+Tshold1+Tuncertainty-Tcppr (7)
where, tarr2 is the time of the data signal Din from the data input terminal D of the first D flip-flop 230 to the input terminal IN of the reference memory 210, treq2 is the time of the clock signal Sin from the input terminal of the second buffer 250 to the clock input terminal CP of the reference memory 210, and Tshold1 is the holding time required for the reference memory 210 to access the data signal Din.
In addition, the retention time margin thbatch 1 may be calculated according to the equations (6) and (7), and the retention time margin thbatch 1 may be expressed as the following equation (8).
Thslack1＝Tarr2-Treq2
＝Tlaunch1+Tck2q+Tdp1-Tcapture1-Tshold1-Tuncertainty+Tcppr (8)
To enable the data signal Din to be transmitted correctly by the reference memory 210, the hold time margin thslide 1 should be greater than or equal to 0. Therefore, the formula (8) can be rewritten to the formula (9) to obtain the constraint on the retention time Tshold 1.
Tshold1<＝Tlaunch1+Tck2q-Tcapture1+Tdp1-Tuncertainty+Tcppr (9)
As can be seen from equation (9), since the condition that the retention time margin thslide 1 is equal to or greater than 0 needs to be satisfied, the maximum retention time Tshold1 corresponding to the reference memory 210 can be obtained according to the sizes of the parameters Tlaunch1, tck2q, tcapiture 1, tdp1, tunicaitantiny, and Tcppr that cannot be converged continuously max . Wherein, the first and the second end of the pipe are connected with each other,
Tshold1 max ＝Tlaunch1+Tck2q-Tcapture1+Tdp1-Tuncertainty+Tcppr (10)
in addition, as shown in fig. 3B, the testing apparatus 110 performs a timing analysis on the path of the reference memory 210 under the first process corner and the second process corner respectively through the second portion 320 of the test model 200 to obtain the constraints on the setup time and the hold time of the reference memory 210. In the present embodiment, the second portion 320 of the test model 200 is, for example, a memory to register (MEMORY TO REGISTER) portion. In the present embodiment, the second portion 320 of the test model 200 represents a portion of the reference memory 210 to a register (e.g., the second D flip-flop 270). The paths refer to a plurality of paths from the data input terminal IN of the memory under test 210 and the input terminal of the second buffer 250 to the data input terminal D and the clock input terminal CK of the buffer (e.g., the second D flip-flop 270), respectively.
Referring to FIG. 3B, the second portion 320 of the test model 200 includes the reference memory 210, the second logic 260, the second D flip-flop 270, and the third buffer 280. The testing apparatus 110 may obtain the time for the reference memory 210 to transmit the data signal Din at the first process corner and obtain the time for the reference memory 210 to transmit the data signal Din at the second process corner.
The test apparatus 110 tests the reference memory 210 under a first process corner (for example, an SS corner), a time from the data input terminal IN of the reference memory 210 to the output terminal OUT of the reference memory 210 of the data signal Din is Tcp2q1, the test apparatus 110 obtains a time Tarr3 from the data input terminal IN of the reference memory 210 to the input terminal D of the second D flip-flop 270 of the data signal Din and a time Treq3 from the output terminal of the second buffer 250 to the clock input terminal CK of the second D flip-flop 270 of the clock signal Sin, and the time Tarr3 and the time Treq3 are respectively shown IN the following equations (11) and (12):
Tarr3＝Tlaunch2+Tcp2q1+Tdp2 (11)
Treq3＝Tcycle+Tcapture2-Tsetup2-Tuncertainty+Tcppr (12)
where, tarr3 is the time from the data input terminal IN of the reference memory 210 to the input terminal D of the second D flip-flop 270 for the data signal Din, treq3 is the time from the output terminal of the second buffer 250 to the clock input terminal CK of the second D flip-flop 270 for the clock signal Sin, tlaunch2 is the delay (launch clock latency) generated by the second buffer 250 for the clock signal Sin, tcp2q1 is the time from the data input terminal IN of the reference memory 210 to the output terminal OUT of the reference memory 210 for the data signal Din, tdp2 is the delay generated by the second logic unit 260 for the data signal Din, tcycle is the clock period of the clock signal Sin, tcapot 2 is the delay generated by the third buffer 280 for the clock signal Sin, and Tsetup2 is the setup time required by the second D flip-flop 270 to access the data signal Din.
Further, the setup time margin tsslew 2 may be calculated according to the equations (11) and (12), and the setup time margin tsslew 1 may be expressed by the following equation (13).
Tsslack2＝Treq3-Tarr3
＝Tcycle+Tcapture2-Tsetup2-Tuncertainty+Tcppr-Tlaunch2-Tdp2-Tcq2q2 (13)
To enable the data signal Din to be correctly written to the second D flip-flop 270, the setup time margin tssleep 2 should be equal to or greater than 0. Therefore, equation (13) can be rewritten as equation (14) to obtain the constraint on the time Tcp2q1 of the data signal Din from the data input terminal IN of the reference memory 210 to the output terminal OUT of the reference memory 210.
Tcp2q1<＝Tcycle+Tcapture2-Tlaunch2-Tdp2-Tsetup2-Tuncertainty+Tcppr (14)
As can be seen from equation (14), since the condition that the setup time margin tstack 2 is equal to or greater than 0 needs to be satisfied, the maximum time Tcp2q1 corresponding to the reference memory 210 can be obtained according to the sizes of the parameters Tcycle, tcappure 2, tlaunch2, tdp2, tsetup2, tunteraity, and Tcppr that cannot be converged max . Wherein the content of the first and second substances,
Tcp2q1 max ＝Tcycle+Tcapture2-Tlaunch2-Tdp2-Tsetup2-Tuncertainty+Tcppr (15)
the test apparatus 110 tests the reference memory 210 under a second process corner (for example, an FF corner), a time from the data input terminal IN of the reference memory 210 to the output terminal OUT of the reference memory 210 of the data signal Din is Tcp2q2, the test apparatus 110 obtains a time Tarr4 from the data input terminal IN of the reference memory 210 to the input terminal D of the second D flip-flop 270 of the data signal Din and a time Treq4 from the input terminal of the second buffer 250 to the clock input terminal CK of the second D flip-flop 270 of the clock signal Sin, and the time Tarr4 and the time Treq4 may be respectively expressed as following equations (16) and (17):
Tarr4＝Tlaunch2+Tcp2q2+Tdp2 (16)
Treq4＝Tcapture2+Thold2+Tuncertainty-Tcppr (17)
where, tarr4 is the time of the data signal Din from the data input terminal IN of the reference memory 210 to the input terminal D of the second D flip-flop 270, treq4 is the time of the clock signal Sin from the input terminal of the second buffer 250 to the clock input terminal CK of the second D flip-flop 270, and Thold2 is the holding time required by the second D flip-flop 270 to correctly transmit the data signal Din.
In addition, the remaining holding time amount thslide 2 may be calculated according to the equations (16) and (17), and the remaining holding time amount thslide 2 may be expressed as the following equation (18).
Thslack2＝Tarr4-Treq4
＝Tlaunch2+Tcp2q2+Tdp2-Tcapture2-Thold2-Tuncertainty+Tcppr (18)
To enable the second D flip-flop 270 to correctly transmit the data signal Din, the hold time margin thslide 2 should be equal to or greater than 0, and therefore equation (18) may be rewritten to equation (19) to obtain the constraint on the time Tcp2q 2.
Tcp2q2>＝Tcapture2+Thold2-Tdp2-Tlaunch2+Tuncertainty-Tcppr (19)
As can be seen from equation (19), since the condition that the remaining time period thbatch 2 is equal to or greater than 0 needs to be satisfied, the maximum time period Tcp2q1 corresponding to the reference memory 210 can be obtained from the sizes of the parameters tcaperture 2, thold2, tdp2, and Tlaunch2 that cannot converge max . Wherein the content of the first and second substances,
Tcp2q1 max ＝Tcapture2+Thold2-Tdp2-Tlaunch2+Tuncertainty-Tcppr (20)
the extracting device 120 extracts a second timing parameter from an alternative memory according to a plurality of first timing parameters of the reference memory 210, wherein the first timing parameter of the reference memory 210 includes the maximum setup time Tssetup1 max Maximum retention time Thold 1 max Maximum time Tcp2q1 max And a maximum time Tcp2q2 max . For example, after the extracting device 120 obtains the first plurality of timing parameters of the reference memory 210, the extracting device 120 obtains the candidate memory from the memory bank, and performs the extraction of the second timing parameter to the candidate memory by using an interpolation algorithm (interpolation algorithm) to obtain a plurality of second timing parameters of the candidate memory. In this embodiment, the plurality of second timing parameters include a setup time Tssetup1, a hold time Tshold1, a time Tcp2q2, and the like corresponding to the candidate memory. In addition, the alternative memory may be compiled (complex) in advance to obtain the second timing parameters of the alternative memory, and the alternative memory and the related information and the second timing parameters may be storedAnd the database is used for conveniently carrying out parameter extraction operation on the alternative memory.
The comparing device 130 compares the first timing parameter of the reference memory 210 with the second timing parameter of the alternative memory to generate a comparison result. Specifically, the comparison device 130 compares whether the setup time Tssetup1 corresponding to the candidate memory is less than or equal to the maximum setup time Tssetup1 corresponding to the reference memory 210 max And comparing whether the retention time Thold 1 corresponding to the alternative memory is less than or equal to the maximum retention time Thold 1 corresponding to the reference memory 210 max Comparing whether the time Tcp2q1 of the alternative memory is less than or equal to the maximum time Tcp2q1 of the reference memory 210 max And comparing whether the time Tcp2q1 of the alternative memory is less than or equal to the maximum time Tcp2q2 of the reference memory 210 max 。
The processing device 140 determines whether the candidate memory is a qualified memory according to the comparison result. When the second timing parameter of the candidate memory matches the first timing parameter of the reference memory 210, that is, the setup time Tssetup1 corresponding to the candidate memory is less than or equal to the maximum setup time Tssetup1 corresponding to the reference memory 210 max The retention time Thold 1 corresponding to the candidate memory is less than or equal to the maximum retention time Thold 1 corresponding to the reference memory 210 max The time Tcp2q1 of the alternative memory is less than or equal to the maximum time Tcp2q1 of the reference memory 210 max And the time Tcp2q1 of the alternative memory is less than or equal to the maximum time Tcp2q2 of the reference memory 210 max And if so, the alternative memory is a qualified memory. When the second timing parameter of the alternative memory cannot match the first timing parameter of the reference memory 210, that is, the setup time Tssetup1 corresponding to the alternative memory is greater than the maximum setup time Tssetup1 corresponding to the reference memory 210 max And/or the retention time Thold 1 corresponding to the alternative memory is greater than the maximum retention time Thold 1 corresponding to the reference memory 210 max And/or the time Tcp2q1 of the alternative memory is greater than the maximum time Tcp2q1 of the reference memory 210 max And/or the time Tcp2q1 of the alternative memory is greater than the maximum time Tcp2q2 of the reference memory 210 max And if so, the alternative memory is the unqualified memory. The processing device 140 may beAnd selecting a proper memory from the plurality of candidate memories according to the comparison result. Therefore, a proper memory (i.e., a memory meeting design requirements) can be quickly selected, so that the back end does not need to deal with the violation of retention time and setup time caused by the memory after adding the memory into the chip design, the time cost can be saved, and the convenience in use can be improved.
Timing analysis of a small number of paths may be shown in the test model 200 described above, but the invention is not limited thereto. In practical applications, the timing analysis tests of a large number of paths can be performed with reference to the test of the memory 210, and the timing analysis tests of other paths can refer to the above description of the test model 200, so that the description thereof is omitted.
With the above description of the embodiments, the present invention provides a method for selecting a memory. Fig. 4 is a flowchart of a memory selection method according to an embodiment of the invention. In step S402, a path timing analysis is performed on the reference memory through the test model to obtain a plurality of first timing parameters. In step S404, a memory is subjected to parameter extraction according to the first timing parameter, so as to obtain a plurality of second timing parameters of the memory. Optionally, in step S404, under the condition of multiple candidate memories, according to the first timing parameter, performing parameter extraction on the multiple candidate memories to obtain multiple second timing parameters corresponding to the candidate memories. In step S406, the first timing parameter is compared with the corresponding second timing parameters of the memory to generate a comparison result. Optionally, in step S406, in the case of multiple candidate memories, the first timing parameter is compared with the second timing parameter of each candidate memory to generate a comparison result. In step S408, it is determined whether the memory is qualified according to the comparison result. Optionally, in step S408, in the case of multiple candidate memories, according to the comparison result, a qualified memory is selected from the candidate memories, where a second timing parameter of the selected candidate memory is matched with the first timing parameter. In an embodiment, in step S404, an interpolation algorithm is further used to perform parameter extraction on a plurality of candidate memories with the same function and different parameters according to the first timing parameter, so as to obtain a plurality of second timing parameters corresponding to each of the candidate memories.
Fig. 5 is a detailed flowchart of step S402 of fig. 4. In step S502, a path timing analysis is performed on the reference memory under the first process corner and the second process corner respectively by the first part of the test model to obtain constraints on the setup time and the hold time, such as obtaining a maximum setup time and a maximum hold time. In step S504, a path timing analysis is performed on the reference memory under the first process corner and the second process corner respectively by the second part of the test model to obtain constraints on transmission time of the data signal in the reference memory, such as a maximum first access time and a maximum second access time. The first part of the test model is a buffer-to-memory part, and the second part of the test model is a memory-to-buffer part.
Although the present invention has been described with reference to specific embodiments, it will be apparent to one of ordinary skill in the art that changes and modifications may be made without departing from the spirit and scope of the invention as defined by the following claims.
Claims (10)
1. A method for selecting a memory comprises the following steps:
according to the test model, performing path time sequence analysis on a reference memory to obtain a plurality of first parameters of the reference memory;
extracting parameters of a memory according to the first parameters to obtain second parameters of the memory; and
comparing the plurality of first parameters with the plurality of second parameters to determine whether the memory is qualified,
when the second parameters of the memory are respectively less than or equal to the corresponding first parameters, determining that the memory is qualified,
and when any one of the second parameters of the memory is larger than the corresponding first parameter, determining that the memory is unqualified.
2. The method of claim 1, wherein the step of obtaining the first parameters according to the test model comprises:
performing first path time sequence analysis on the reference memory under a first process angle and a second process angle respectively through the test model to obtain maximum establishing time and maximum holding time corresponding to the reference memory; and
performing a second path timing analysis on the reference memory to obtain a maximum first access time and a maximum second access time of the reference memory,
wherein the plurality of first parameters includes the maximum setup time, the maximum hold time, the maximum first access time, and the maximum second access time.
3. The method of selecting a memory as claimed in claim 2, wherein the first path timing analysis and the second path timing analysis are static timing analysis, the first process corner is an SS corner, and the second process corner is an FF corner.
4. The memory selection method of claim 2, wherein the test model comprises a first portion comprising:
a first buffer comprising an input and an output, the input of the first buffer receiving a clock signal, the first buffer producing a first clock delay to the clock signal;
a first buffer comprising a data input, a clock input, and a data output, the data input of the first buffer receiving a data signal, the first buffer consuming a first transmission time to transmit the data signal;
a first logic including an input and an output, the first logic receiving the data signal, the first logic consuming a second transmission time to transmit the data signal;
a second buffer comprising an input and an output, the second buffer receiving the clock signal, the second buffer generating a second clock delay to the clock signal; and
the reference memory comprises a data input terminal, a clock input terminal and a data output terminal, the clock input terminal of the reference memory receives the clock signal, the data input terminal of the reference memory receives the data signal, the output terminal of the reference memory outputs the data signal,
wherein the maximum setup time and the maximum hold time for supporting the reference memory to receive and output the data signal are respectively calculated according to the first clock delay, the first transmission time, the second transmission time, and the second clock delay at the first process corner and the second process corner, respectively.
5. The memory selection method of claim 2, wherein the test model includes a second portion, the second portion including:
the reference memory comprises a data input end, a clock input end and a data output end, wherein the clock input end of the reference memory receives a clock signal, the data input end of the reference memory receives a data signal, and the output end of the reference memory outputs the data signal;
a second logic comprising an input and an output, the second logic receiving the data signal, the second logic consuming a third transmission time to transmit the data signal;
a second buffer comprising a data input, a clock input, and a data output, the data input of the second buffer receiving the data signal, the second buffer consuming a fourth transmission time to transmit the data signal; and
a third buffer comprising an input and an output, the third buffer receiving the clock signal, the third buffer producing a third clock delay to the clock signal,
and calculating the maximum first access time and the maximum second access time for the reference memory to transmit the data signal according to the third transmission time, the fourth transmission time and the third clock delay under the first process corner and the second process corner respectively.
6. A memory selection device, comprising:
the testing device is used for carrying out time sequence analysis on a path of a reference memory through a testing model so as to obtain a plurality of first parameters of the reference memory;
the extracting device is used for extracting parameters of a memory according to the first parameters so as to obtain a plurality of second parameters of the memory;
the comparison device is used for comparing whether the plurality of second parameters are smaller than or equal to the corresponding first parameters or not; and
a processing device for determining whether the memory is qualified,
wherein, when the plurality of second parameters of the memory are respectively less than or equal to the corresponding first parameters, the memory is determined to be qualified,
and when any one of the second parameters of the memory is larger than the corresponding first parameter, determining that the memory is unqualified.
7. The memory selection device of claim 6, wherein
The test device respectively performs first path time sequence analysis on the reference memory under a first process angle and a second process angle through the test model to obtain maximum establishing time and maximum holding time corresponding to the reference memory; and
performing a second path timing analysis on the reference memory under the first process corner and the second process corner respectively to obtain a maximum first access time and a maximum second access time of the reference memory,
wherein the plurality of first parameters includes the maximum setup time, the maximum hold time, the maximum first access time, and the maximum second access time.
8. The memory selection device of claim 7, wherein the first path timing analysis and the second path timing analysis are static timing analysis, the first process corner is an SS corner, and the second process corner is an FF corner.
9. The memory selection device of claim 7, wherein the test model comprises a first portion comprising:
a first buffer comprising an input and an output, the input of the first buffer receiving a clock signal, the first buffer producing a first clock delay to the clock signal;
a first buffer comprising a data input, a clock input, and a data output, the data input of the first buffer receiving a data signal, the first buffer consuming a first transmission time to transmit the data signal;
a first logic including an input and an output, the first logic receiving the data signal, the first logic consuming a second transmission time to transmit the data signal;
a second buffer comprising an input and an output, the second buffer receiving the clock signal, the second buffer generating a second clock delay to the clock signal; and
the reference memory comprises a data input terminal, a clock input terminal and a data output terminal, the clock input terminal of the reference memory receives the clock signal, the data input terminal of the reference memory receives the data signal, the output terminal of the reference memory outputs the data signal,
wherein the maximum setup time and the maximum hold time supporting the reference memory to receive and output the data signal are respectively calculated according to the first clock delay, the first transmission time, the second transmission time, and the second clock delay at the first process corner and the second process corner, respectively.
10. The memory selection device of claim 7, wherein the test model includes a second portion, the second portion including:
the reference memory comprises a data input end, a clock input end and a data output end, wherein the clock input end of the reference memory receives a clock signal, the data input end of the reference memory receives a data signal, and the output end of the reference memory outputs the data signal;
a second logic comprising an input and an output, the second logic receiving the data signal, the second logic consuming a third transmission time to transmit the data signal;
a second buffer comprising a data input, a clock input, and a data output, the data input of the second buffer receiving the data signal, the second buffer consuming a fourth transmission time to transmit the data signal; and
a third buffer comprising an input and an output, the third buffer receiving the clock signal, the third buffer generating a third clock delay to the clock signal,
and calculating the maximum first access time and the maximum second access time for the reference memory to transmit the data signal according to the third transmission time, the fourth transmission time and the third clock delay under the first process corner and the second process corner respectively.
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