WO2006132821A2 - Output level voltage regulation - Google Patents

Output level voltage regulation Download PDF

Info

Publication number
WO2006132821A2
WO2006132821A2 PCT/US2006/020428 US2006020428W WO2006132821A2 WO 2006132821 A2 WO2006132821 A2 WO 2006132821A2 US 2006020428 W US2006020428 W US 2006020428W WO 2006132821 A2 WO2006132821 A2 WO 2006132821A2
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
output
level
polarity
circuit
Prior art date
Application number
PCT/US2006/020428
Other languages
French (fr)
Other versions
WO2006132821A3 (en
Inventor
Gaetan Bracmard
Henri Bottaro
Original Assignee
Atmel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0505712A external-priority patent/FR2886746B1/en
Application filed by Atmel Corporation filed Critical Atmel Corporation
Priority to CN2006800200904A priority Critical patent/CN101194216B/en
Priority to JP2008515744A priority patent/JP5058158B2/en
Priority to EP06771283A priority patent/EP1889134A2/en
Publication of WO2006132821A2 publication Critical patent/WO2006132821A2/en
Publication of WO2006132821A3 publication Critical patent/WO2006132821A3/en

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31703—Comparison aspects, e.g. signature analysis, comparators

Definitions

  • the invention relates to electrical interface circuits and, more particularly, to a circuit for matching an output voltage to a desired voltage.
  • Computer systems are comprised of a number of electronic components that must interoperate . To minimize the costs of various components, different components are made which operate at different voltages. If the output level is not compatible with an input level, the device may be damaged and interoperation thwarted.
  • a level shifter circuit commonly would be used to interconnect devices, for example by interconnecting sections of a bus system. Each section would have a different supply voltage and different logic level. In a typical example, each section would have a supply voltage; pull up resistors and devices connected to the supply voltage; and a serial data bus line and a serial clock bus line connected to the devices.
  • An exemplary level shifter circuit would include a gate connected to the lower voltage supply, sources connected to the lower voltage bus lines, and drains connected to the higher voltage bus lines. One such level shifter circuit would be required for each different supply voltage.
  • Level shifter circuits are generally specific to specific voltage levels. Thus for each device or group of devices having a specific voltage operating level, the system requires specific circuitry to allow use of the devices .
  • a circuit and method of adapting an output voltage level toward a target voltage level includes applying an output voltage from a pin or pad to an output line and applying a reference voltage to a reference voltage line for comparison by a comparator having a logical output, high or low.
  • a state machine receives a signal from the comparator. The state machine generates a trim bus signal in response to the signal from the comparator and in response to the registered prior logic output. If the two polarities match, further corrective voltage feedback is required. If the two polarities do not match, corrective voltage feedback of the opposite sign is indicated by flipping the output state of the comparator.
  • a clocked trim bus signal is sent to a sense circuit and voltage regulator, which changes a switched resistor value to step the output voltage one step towards the reference voltage.
  • the resistor value (resistance) of the sense circuit and voltage regulator is changed to increase the output voltage one step towards the reference voltage.
  • the comparison between the output voltage and the reference voltage would then be repeated on the next clock cycle, as will the subsequent steps effected by the comparator, the state machine, and the sense/resistor. Sequential voltage steps would be completed until the output voltage crossed the reference voltage threshold in polarity. At this point the comparator signal would flip states, signaling the state machine to save the trim bus value into a register.
  • Fig. 1 is a circuit overview of an output adapter.
  • Fig. 2 is a graph of signal voltage over time using a circuit such as the circuit of Fig. 1.
  • Fig. 3 is a circuit diagram of the resistor network shown as a block in Fig. 1.
  • Fig. 4 is a circuit diagram of the decoder circuit shown as a block in Figs. 1 and 3.
  • Fig. 5 is a circuit diagram of the regulator shown as a block in Fig. 1.
  • an output pad 12 produces an output voltage applied at output line 14.
  • a reference supply such as a tester 16 produces a stable and fixed reference voltage onto line 18.
  • comparator 20 an analog error amplifier that produces an output by sensing an error either above or below the reference threshold voltage.
  • the resulting comparator output will be either a logic high or low, depending upon the polarity of the error.
  • the initial output voltage level 40 is compared to the reference voltage level 60. Since initially the value of the voltage 40 at node 38 in
  • Fig. 1 is below the reference voltage level, in this example the state of the comparator output remains at low state 50.
  • the comparator 20 sends a signal to the state machine 22, a logic device.
  • the logic device has registered what it did on the previous cycle. If the error signal was of the same polarity on the previous clock cycle then the incremental output signal is set to be one step larger than the prior output signal. If the error signal has a reverse polarity, then the incremental output signal is one step of opposite polarity.
  • the state machine 22 receives a clock signal from the clock 24, allowing clocking of logic signals and register of the state machine.
  • the state machine sends a three-bit trim bus value signal to decoder 27 for establishing a correction voltage in a resistor network 28. The signal is sent on three-bit line 26, such that a three-bit word may be transmitted.
  • a three-bit word may encode eight states of the trim bus value, or four bits and a sign bit, presenting a number of corresponding voltage step heights that are possible.
  • the sense circuit 21 and voltage regulator 30 are part of a voltage feedback loop that may be changed to alter output voltage at node 38. This is done in defined increments corresponding to the eight step heights described above.
  • the output signal is stepped up or down a maximum of one step per clock cycle until the polarity of the error signal in the comparator reverses.
  • output signal 42 is shown stepped up one step per clock cycle compared to output level 40. At this voltage output level, the output voltage 42 is still below the reference voltage 60. Thus, as explained in Fig. 1, the comparator output logic level remains at low state 50.
  • the state machine a clocked logic device, adds one to the registered state of the trim bus value in a signal which is again transmitted to the sense circuit and voltage regulator. The regulator again incrementally changes the resistance of the feedback loop, again increasing the output voltage in a stepped manner so long as the error signal maintains its polarity.
  • Fig. 2 the result of this is the output voltage level 44 is maintained at a one step increase for one clock cycle with clock intervals indicated by vertical dashed lines. This process is repeated.
  • An increase, to output voltage 46, is compared in the comparator to reference voltage 60. At this point the output voltage is above the reference voltage 60 and the polarity of the error signal is reversed.
  • the comparator output then flips states to high state 52. This signals the state machine to memorize the trim bus value into a memory.
  • the output voltage is initially below the reference voltage.
  • This voltage is incrementally stepped up at clocked intervals until the output voltages crosses the reference voltage threshold.
  • the incremental stepping of the output voltage in the direction of the reference voltage is effected by modifying a switched resistor network described below with reference to Figs. 3 and 4. This is repeated in clocked cycles until the output voltage crosses the reference voltage threshold.
  • the initial output voltage be above the reference voltage.
  • the comparator logic level would start in the high state, indicating to the state machine that the output voltage level is above the reference voltage threshold.
  • the trim bus logic signal value would then signal the switched resistor network to modify resistance for the output, incrementally stepping down the voltage. This would be repeated until the output voltage crossed the reference voltage threshold in polarity. At that time the comparator would flip state, in this instance from high to low.
  • the trim bus logic signal value would again be saved into a register for comparison with polarity of the next logic signal value.
  • the previous logic signal value is increased by one unit. If the polarity is the opposite, the previous logic signal value is decremented by one unit . - b -
  • decoder 27 is seen to receive three-trim bits on line 26.
  • the three-trim bits also shown in Fig. 4, generate eight unique signal in decoder block 27.
  • Fig. 4 there is a logic arrangement wherein three parallel bits are translated to eight possible signals.
  • the eight possible logic signals appearing one at a time, are taken as logic output signals 32a-32h and their corresponding complements 34a- 34h.
  • the complementary output signals e.g., 32c and 34c, are delivered as simultaneous logical outputs.
  • the simultaneous logical outputs are split to drive corresponding CMOS driver transistors pairs of opposite conductivity types in resistor network 76.
  • p-channel CMOS transistor 38a has a control gate operated by logic signal 34a
  • the corresponding n-channel CMOS transistor 36a has a control gate operated by logic signal 32a.
  • Each p-channel transistor 38a, 38b, etc. delivers regulated bias voltage on line 70 to a lower level in the series of resistors R2.
  • Transistor 38a bypasses one resistor with bias voltage.
  • Transistor 38b bypasses two resistors, and so on.
  • resistor network 76 is selected to give V MED the proper voltage for a given regulated supply voltage applied across selected resistors in Rl and R2 groups. Resistor network 76 is seen in Fig.
  • V MED voltage output
  • the voltage level V MED is combined with a bandgap reference level from device 82 to adjust a supply transistor 84 to which external supply 86 is connected.
  • the regulated supply output voltage on line 88 is fed to resistor network 76, the node 38 associated with output pad 12 and an input line to comparator 20 in Fig. 1.
  • the circuit of Fig. 1 is not intended to be limited by any specific type of regulator nor any other specific circuit well known in the art.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Electromagnetism (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Direct Current Feeding And Distribution (AREA)
  • Control Of Voltage And Current In General (AREA)
  • Control Of Eletrric Generators (AREA)
  • Logic Circuits (AREA)

Abstract

A circuit adapting pin output levels to a reference level (60) in which a digital comparator (20) compares an output voltage (40) from an output pin of a device to a reference voltage level (60) . The comparator (20) , relying on the polarity of the comparator output (50, 52) as well as the registered polarity of the comparator output on the previous clock cycle, signals a state machine (22) , which sends a clocked signal to a sense circuit (21) and voltage regulator (30) . The sense circuit (21) may modify a resistance in a switched resistor network (28) , such that the output level is incrementally stepped at clocked intervals towards the reference voltage (60) until the polarity of the error signal reverses. When the output voltage (40) crosses the reference voltage (60) threshold, the comparator (20) flips states and continues to regulate output pin voltage to the reference voltage level (60) .

Description

Description
OUTPUT LEVEL VOLTAGE REGULATION
TECHNICAL FIELD
The invention relates to electrical interface circuits and, more particularly, to a circuit for matching an output voltage to a desired voltage.
BACKGROUND
Computer systems are comprised of a number of electronic components that must interoperate . To minimize the costs of various components, different components are made which operate at different voltages. If the output level is not compatible with an input level, the device may be damaged and interoperation thwarted.
In prior circuit design, a level shifter circuit commonly would be used to interconnect devices, for example by interconnecting sections of a bus system. Each section would have a different supply voltage and different logic level. In a typical example, each section would have a supply voltage; pull up resistors and devices connected to the supply voltage; and a serial data bus line and a serial clock bus line connected to the devices. An exemplary level shifter circuit would include a gate connected to the lower voltage supply, sources connected to the lower voltage bus lines, and drains connected to the higher voltage bus lines. One such level shifter circuit would be required for each different supply voltage.
Level shifter circuits are generally specific to specific voltage levels. Thus for each device or group of devices having a specific voltage operating level, the system requires specific circuitry to allow use of the devices .
SUMMARY OF THE INVENTION A circuit and method of adapting an output voltage level toward a target voltage level includes applying an output voltage from a pin or pad to an output line and applying a reference voltage to a reference voltage line for comparison by a comparator having a logical output, high or low. A state machine receives a signal from the comparator. The state machine generates a trim bus signal in response to the signal from the comparator and in response to the registered prior logic output. If the two polarities match, further corrective voltage feedback is required. If the two polarities do not match, corrective voltage feedback of the opposite sign is indicated by flipping the output state of the comparator. A clocked trim bus signal is sent to a sense circuit and voltage regulator, which changes a switched resistor value to step the output voltage one step towards the reference voltage. Thus if the output voltage was below the reference voltage, the resistor value (resistance) of the sense circuit and voltage regulator is changed to increase the output voltage one step towards the reference voltage. The comparison between the output voltage and the reference voltage would then be repeated on the next clock cycle, as will the subsequent steps effected by the comparator, the state machine, and the sense/resistor. Sequential voltage steps would be completed until the output voltage crossed the reference voltage threshold in polarity. At this point the comparator signal would flip states, signaling the state machine to save the trim bus value into a register. - ό -
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a circuit overview of an output adapter.
Fig. 2 is a graph of signal voltage over time using a circuit such as the circuit of Fig. 1.
Fig. 3 is a circuit diagram of the resistor network shown as a block in Fig. 1.
Fig. 4 is a circuit diagram of the decoder circuit shown as a block in Figs. 1 and 3. Fig. 5 is a circuit diagram of the regulator shown as a block in Fig. 1.
DETAILED DESCRIPTION OF THE INVENTION
With reference to Fig. 1, an output pad 12 produces an output voltage applied at output line 14. A reference supply, such as a tester 16, produces a stable and fixed reference voltage onto line 18. These are compared by comparator 20, an analog error amplifier that produces an output by sensing an error either above or below the reference threshold voltage. The resulting comparator output will be either a logic high or low, depending upon the polarity of the error.
Referring to Fig. 2, the initial output voltage level 40 is compared to the reference voltage level 60. Since initially the value of the voltage 40 at node 38 in
Fig. 1 is below the reference voltage level, in this example the state of the comparator output remains at low state 50.
Returning to Fig. 1, the comparator 20 sends a signal to the state machine 22, a logic device. The logic device has registered what it did on the previous cycle. If the error signal was of the same polarity on the previous clock cycle then the incremental output signal is set to be one step larger than the prior output signal. If the error signal has a reverse polarity, then the incremental output signal is one step of opposite polarity. The state machine 22 receives a clock signal from the clock 24, allowing clocking of logic signals and register of the state machine. The state machine sends a three-bit trim bus value signal to decoder 27 for establishing a correction voltage in a resistor network 28. The signal is sent on three-bit line 26, such that a three-bit word may be transmitted. A three-bit word may encode eight states of the trim bus value, or four bits and a sign bit, presenting a number of corresponding voltage step heights that are possible. The sense circuit 21 and voltage regulator 30 are part of a voltage feedback loop that may be changed to alter output voltage at node 38. This is done in defined increments corresponding to the eight step heights described above. The output signal is stepped up or down a maximum of one step per clock cycle until the polarity of the error signal in the comparator reverses.
Again with reference to Fig. 2, output signal 42 is shown stepped up one step per clock cycle compared to output level 40. At this voltage output level, the output voltage 42 is still below the reference voltage 60. Thus, as explained in Fig. 1, the comparator output logic level remains at low state 50. The state machine, a clocked logic device, adds one to the registered state of the trim bus value in a signal which is again transmitted to the sense circuit and voltage regulator. The regulator again incrementally changes the resistance of the feedback loop, again increasing the output voltage in a stepped manner so long as the error signal maintains its polarity.
In Fig. 2, the result of this is the output voltage level 44 is maintained at a one step increase for one clock cycle with clock intervals indicated by vertical dashed lines. This process is repeated. An increase, to output voltage 46, is compared in the comparator to reference voltage 60. At this point the output voltage is above the reference voltage 60 and the polarity of the error signal is reversed. The comparator output then flips states to high state 52. This signals the state machine to memorize the trim bus value into a memory.
In the example of Fig. 2, the output voltage is initially below the reference voltage. This voltage is incrementally stepped up at clocked intervals until the output voltages crosses the reference voltage threshold. The incremental stepping of the output voltage in the direction of the reference voltage is effected by modifying a switched resistor network described below with reference to Figs. 3 and 4. This is repeated in clocked cycles until the output voltage crosses the reference voltage threshold. It is also possible that the initial output voltage be above the reference voltage. In this case, the comparator logic level would start in the high state, indicating to the state machine that the output voltage level is above the reference voltage threshold. The trim bus logic signal value would then signal the switched resistor network to modify resistance for the output, incrementally stepping down the voltage. This would be repeated until the output voltage crossed the reference voltage threshold in polarity. At that time the comparator would flip state, in this instance from high to low. The trim bus logic signal value would again be saved into a register for comparison with polarity of the next logic signal value.
If the polarity is the same, the previous logic signal value is increased by one unit. If the polarity is the opposite, the previous logic signal value is decremented by one unit . - b -
With reference to Fig. 3, decoder 27 is seen to receive three-trim bits on line 26. The three-trim bits, also shown in Fig. 4, generate eight unique signal in decoder block 27. In Fig. 4 there is a logic arrangement wherein three parallel bits are translated to eight possible signals. The eight possible logic signals, appearing one at a time, are taken as logic output signals 32a-32h and their corresponding complements 34a- 34h. The complementary output signals, e.g., 32c and 34c, are delivered as simultaneous logical outputs.
Returning to Fig. 3, the simultaneous logical outputs are split to drive corresponding CMOS driver transistors pairs of opposite conductivity types in resistor network 76. For example, p-channel CMOS transistor 38a has a control gate operated by logic signal 34a, while the corresponding n-channel CMOS transistor 36a has a control gate operated by logic signal 32a. Each p-channel transistor 38a, 38b, etc. delivers regulated bias voltage on line 70 to a lower level in the series of resistors R2. Transistor 38a bypasses one resistor with bias voltage. Transistor 38b bypasses two resistors, and so on. On the other hand, each n-channel transistor 36a, 36b, etc. shorts resistors to ground 72 in the series of resistors Rl. The n-channel transistor 36a shorts one resistor to ground. Transistor 36b shorts two resistors, and so on. It is seen that the p-channel and n-channel transistors behave in a complementary manner to deliver an intermediate output voltage, VMED/ on output line 74 that may be half way, or some calculated value based upon selected resistor values, between the regulated supply voltage and ground. Resistor values in resistor network 76 are selected to give VMED the proper voltage for a given regulated supply voltage applied across selected resistors in Rl and R2 groups. Resistor network 76 is seen in Fig. 5 to deliver the voltage output, VMED to an operational amplifier 80 in regulator 30 which was discussed with reference to Fig. 1. The voltage level VMED is combined with a bandgap reference level from device 82 to adjust a supply transistor 84 to which external supply 86 is connected. The regulated supply output voltage on line 88 is fed to resistor network 76, the node 38 associated with output pad 12 and an input line to comparator 20 in Fig. 1. The circuit of Fig. 1 is not intended to be limited by any specific type of regulator nor any other specific circuit well known in the art.

Claims

Claims
1. A voltage regulation circuit for an output pin of a circuit comprising: means for comparing a first voltage from an output pad of a chip with a second reference voltage and generating an output comparison signal having a first polarity if the first voltage exceeds the second voltage and a second polarity if the second voltage exceeds the first voltage; a logic means for receiving the output comparison signal from the comparing means and for generating a correction signal level; a voltage generation means receiving the correction signal level from the logic means and outputting an corrected voltage level to the output pad; and a timing means for clocking the logic means for repeatedly generating sequential correction levels with a sequence clock cycles.
2. The circuit of claim 1 wherein the logic means includes a register for retaining a correction level from a prior clock cycle.
3. The circuit of claim 1 wherein the comparing means, the logic means and the voltage generator means are arranged in a loop.
4. A method for regulating voltage at an output pin of a circuit comprising: sensing a first voltage at the output pin of a chip; comparing the sensed first voltage from the output pin of a chip with a reference second voltage; repeatedly generating a comparison signal having a first polarity if the first voltage exceeds the second voltage and a second polarity if the second voltage exceeds the first voltage,- logically interpreting the state of the comparison signal with reference to the state of a prior comparison signal and generating a correction level in response thereto; and generating a corrected output voltage to the output pin in response to the correction level.
5. The method of claim 4 further defined by clocking the generation of comparison signals with clock pulses of equal duration.
6. The method of claim 4 further defined by applying the correction level to a switched resistor network.
7. The method of claim 6 further defined by generating the corrected output voltage using the switched resistor network .
PCT/US2006/020428 2005-06-06 2006-05-25 Output level voltage regulation WO2006132821A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2006800200904A CN101194216B (en) 2005-06-06 2006-05-25 Output level voltage regulation
JP2008515744A JP5058158B2 (en) 2005-06-06 2006-05-25 Output level voltage adjustment
EP06771283A EP1889134A2 (en) 2005-06-06 2006-05-25 Output level voltage regulation

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR05/05712 2005-06-06
FR0505712A FR2886746B1 (en) 2005-06-06 2005-06-06 REGULATION OF OUTPUT VOLTAGE LEVEL
US11/221,008 2005-09-07
US11/221,008 US7907002B2 (en) 2005-06-06 2005-09-07 Output level voltage regulation

Publications (2)

Publication Number Publication Date
WO2006132821A2 true WO2006132821A2 (en) 2006-12-14
WO2006132821A3 WO2006132821A3 (en) 2007-03-22

Family

ID=37498908

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/020428 WO2006132821A2 (en) 2005-06-06 2006-05-25 Output level voltage regulation

Country Status (3)

Country Link
EP (1) EP1889134A2 (en)
KR (1) KR20080017444A (en)
WO (1) WO2006132821A2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7907002B2 (en) 2005-06-06 2011-03-15 Atmel Corporation Output level voltage regulation
CN102435937A (en) * 2010-08-30 2012-05-02 马维尔以色列(M.I.S.L.)有限公司 Method and Apparatus for Testing Integrated Circuits
CN116613084A (en) * 2023-07-17 2023-08-18 深圳市思远半导体有限公司 Chip, test machine, calibration method of internal comparator of chip and related equipment

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100915830B1 (en) 2008-03-12 2009-09-07 주식회사 하이닉스반도체 Semiconductor integrated circuit
KR20170038977A (en) 2015-09-30 2017-04-10 에스케이하이닉스 주식회사 Semiconductor Memory Apparatus, and Method for Training of Reference Voltage

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6052770A (en) * 1993-06-08 2000-04-18 Theseus Logic, Inc. Asynchronous register
US6157206A (en) * 1998-12-31 2000-12-05 Intel Corporation On-chip termination
US20040150928A1 (en) * 2003-02-03 2004-08-05 Goodfellow John Ryan Digitally controlled voltage regulator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6052770A (en) * 1993-06-08 2000-04-18 Theseus Logic, Inc. Asynchronous register
US6157206A (en) * 1998-12-31 2000-12-05 Intel Corporation On-chip termination
US20040150928A1 (en) * 2003-02-03 2004-08-05 Goodfellow John Ryan Digitally controlled voltage regulator

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7907002B2 (en) 2005-06-06 2011-03-15 Atmel Corporation Output level voltage regulation
CN102435937A (en) * 2010-08-30 2012-05-02 马维尔以色列(M.I.S.L.)有限公司 Method and Apparatus for Testing Integrated Circuits
CN116613084A (en) * 2023-07-17 2023-08-18 深圳市思远半导体有限公司 Chip, test machine, calibration method of internal comparator of chip and related equipment
CN116613084B (en) * 2023-07-17 2024-02-23 深圳市思远半导体有限公司 Chip, test machine, calibration method of internal comparator of chip and related equipment

Also Published As

Publication number Publication date
EP1889134A2 (en) 2008-02-20
KR20080017444A (en) 2008-02-26
WO2006132821A3 (en) 2007-03-22

Similar Documents

Publication Publication Date Title
US7907002B2 (en) Output level voltage regulation
US7002500B2 (en) Circuit, apparatus and method for improved current distribution of output drivers enabling improved calibration efficiency and accuracy
US7525337B2 (en) On-die termination circuit and method for semiconductor memory apparatus
US9165666B2 (en) Charge pump apparatus, a memory integrated circuit and methods of power supply
US7482859B2 (en) Automatic current trimming method & circuits
US20060238399A1 (en) Successive approximation type A/D converter
KR100897255B1 (en) Circuit and method for on die termination of semiconductor memory apparatus
EP1889134A2 (en) Output level voltage regulation
US20080001668A1 (en) Impedance control device and impedance control method
KR100597633B1 (en) Impedance controller and method for control therefore
JP3905889B2 (en) Driver circuit
EP1286469A1 (en) An output driver for integrated circuits and a method for controlling the output impedance of an integrated circuit
KR20160060502A (en) Data transmitter
KR100430356B1 (en) Liquid crystal driving integrated circuit
KR20050021175A (en) Data driving circuit and semiconductor memory device using the same
KR100656461B1 (en) Apparatus and method for on die termination of semiconductor memory
US5710778A (en) High voltage reference and measurement circuit for verifying a programmable cell
CN101485089B (en) Electronic circuit and method therefor
US7009420B2 (en) Input circuit for receiving a signal at an input on an integrated circuit
JP2017126197A (en) Voltage conversion circuit and voltage conversion method
TW202013898A (en) Digital to analog converter device and current control method
US20190319455A1 (en) Device and method for generating duty cycle
KR101803465B1 (en) Majority decision circuit
KR100500947B1 (en) Apparatus for sensing voltage
KR20070116363A (en) On die termination apparatus of semiconductor memory

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200680020090.4

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application
DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2006771283

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2008515744

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 1020087000247

Country of ref document: KR