CN115480234A - Voltage calibration method, circuit, laser radar system and storage medium - Google Patents
Voltage calibration method, circuit, laser radar system and storage medium Download PDFInfo
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Abstract
A voltage calibration method, a circuit, a laser radar system and a storage medium are provided. The method comprises the following steps: in a calibration mode, obtaining a digital test signal with code values changing according to a preset sequence, and performing digital-to-analog conversion on the digital test signal to obtain an analog test signal corresponding to the digital test signal; comparing the voltage value of the analog test signal with a baseline voltage value to obtain a comparison result signal; and when the comparison result signal is inverted, storing a code value of the digital test signal corresponding to the inversion moment of the comparison result signal, so as to determine a detection threshold value in a detection mode based on the stored code value. By applying the scheme, the influence of temperature drift on the precision of the laser radar system can be reduced without temperature measurement.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a voltage calibration method, a voltage calibration circuit, a laser radar system and a storage medium.
Background
In a laser radar system, a laser radar emits laser pulses, which are reflected back by a target object, and by measuring the time of flight required for the pulses to reach the target object and return to the radar, the precise distance between the target object and the radar can be calculated. The lidar emits multiple laser pulses per second, and by collecting these distance measurements and object reflectivity, a three-dimensional environmental model, i.e., a point cloud, can be constructed. Based on the ranging principle of the laser radar, the accuracy and consistency of the quantized pulse flight time of the receiving end are of vital importance.
Wherein the time of flight is determined in relation to a threshold voltage of a comparator in the lidar system. Whether the threshold voltage of the comparator is accurate or not can be said to determine the accuracy of the laser radar system.
In practical application, the threshold voltage of the comparator can change along with temperature and process, so that the consistency and the accuracy of the extreme distance measurement capability of the laser radar receiving end under different illumination environment conditions are influenced, and the accuracy of a laser radar system is influenced finally.
Currently, the temperature of a lidar system can be measured to reduce the effect of temperature drift on the lidar system based on the temperature measurement.
However, in the above scheme, the temperature measurement needs to be performed in real time, the adjustment time is long, and the complexity of the scheme is high. In addition, in the process of temperature measurement, laser ranging needs to be stopped, so that the whole laser radar measurement dead zone is caused. In addition, the temperature measurement and calibration are required before the laser radar leaves the factory, which increases the cost to a great extent.
Disclosure of Invention
The invention aims to solve the problems that: a scheme without temperature measurement is provided to reduce the influence of temperature drift on the accuracy of the laser radar system.
In order to solve the above problem, an embodiment of the present invention provides a voltage calibration method, where the method includes: in a calibration mode, obtaining a digital test signal with code values changing according to a preset sequence, and performing digital-to-analog conversion on the digital test signal to obtain an analog test signal corresponding to the digital test signal; comparing the voltage value of the simulation test signal with a baseline voltage value to obtain a comparison result signal; and when the comparison result signal is inverted, storing a code value of the digital test signal corresponding to the inversion moment of the comparison result signal so as to determine a detection threshold value in a detection mode based on the stored code value.
An embodiment of the present invention further provides a voltage calibration circuit, where the voltage calibration circuit includes: a digital-to-analog converter, a comparator and a memory; the comparator comprises a first input end and a second input end; wherein:
the digital-to-analog converter is suitable for acquiring digital test signals with code values changing according to a preset sequence in a calibration mode, performing digital-to-analog conversion on the digital test signals to acquire analog test signals corresponding to the digital test signals, and inputting the analog test signals to a first input end of the comparator;
the comparator is connected with the digital-to-analog converter and is suitable for comparing the voltage value of the analog test signal with the baseline voltage value input by the second input end to obtain a comparison result signal;
the memory is connected with the comparator and is suitable for storing the code value of the digital test signal corresponding to the signal turning moment of the comparison result when the comparison result signal is turned; the stored code values are used to calibrate the detection threshold.
The embodiment of the invention also provides a laser radar system which comprises the voltage calibration circuit.
Embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to implement the steps of the above voltage calibration method.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
by applying the scheme of the invention, in the calibration mode, a digital test signal with code values changing according to a preset sequence is obtained, digital-to-analog conversion is carried out on the digital test signal to obtain an analog test signal corresponding to the digital test signal, a comparison result signal is obtained by comparing the voltage value of the analog test signal with a baseline voltage value, and when the comparison result signal is inverted, the code value of the digital test signal corresponding to the inversion moment of the comparison result signal is stored to determine the detection threshold value in the detection mode based on the stored code value, so that the calibration of the detection threshold value in the detection mode can be realized. The whole calibration process does not need temperature measurement, can directly complete calibration through simple triggering in the chip, cannot affect the measurement of the laser radar, can avoid temperature threshold value calibration before leaving a factory, and saves cost.
Furthermore, when the digital test signal stops changing, the difference between the code value corresponding to the digital test signal and the code value of the digital test signal corresponding to the comparison result signal turning moment is larger than the preset difference threshold value, so that the voltage value of the analog test signal can be far away from the reference voltage value as far as possible when the digital test signal stops changing, and the error turning of the comparator is reduced.
Furthermore, when the initial comparison result signal is obtained, the burr in the initial comparison result signal is filtered, and the filtered signal is used as the final comparison result signal, so that the error overturn of the comparison result signal caused by the burr can be avoided, and the calibration precision is improved.
Furthermore, by arranging the timing circuit, the threshold value determining circuit and the switching circuit, the receiving end of the laser radar system can multiplex the digital-to-analog converter and the comparator in a detection mode and a calibration mode, so that the structure of the receiving end of the laser radar system can be simplified, and the circuit area is further reduced.
Drawings
FIG. 1 is a schematic diagram of a receiving end of a laser radar system;
FIG. 2 is a flow chart of a voltage calibration method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a forward pulse and a reverse pulse;
FIG. 4 is a timing diagram illustrating a voltage calibration process according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a voltage calibration circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of another exemplary embodiment of a voltage calibration circuit;
FIG. 7 is a schematic diagram of a filtering circuit according to an embodiment of the present invention;
FIG. 8 is a diagram illustrating a memory structure according to an embodiment of the present invention;
FIG. 9 is a timing diagram illustrating another exemplary voltage calibration process according to the present invention.
Detailed Description
Fig. 1 is a schematic diagram of a receiving end of a laser radar system. The receiving end of the laser radar system consists of a detector 11, a comparator 12, a digital-to-analog converter 13 and a time-to-digital converter 14. The Start signal is a synchronization enable signal of the laser emission pulse.
The specific detection process is as follows: the detector 11 converts the reflected laser pulses into electrical analog signals. The dac 13 provides the detection threshold to the comparator 12 and inputs the detection threshold to an input of the comparator 12. The electrical analog signal is input to the other input of the comparator 12. The comparator 12 compares the electrical analog signal with a detection threshold to obtain a corresponding comparison result signal.
The comparison result signal is inverted when the electrical analog signal is larger than the detection threshold, so that the inversion time of the comparison result can be converted into the leading edge and the trailing edge of the digital pulse to obtain a corresponding digital comparison result signal. The time-to-digital converter 14 may locate the position of the object by quantifying the time-of-flight (ToF) between the transition edge of the Start signal to the leading edge of the digital pulse.
Wherein, the code value corresponding to the detection threshold value provided by the dac 13 for the comparator 12 is D vth It can be obtained by the following formula:
D vth ＝D off -D in (1)
in the formula (1), D in Is a system threshold, D, input to the digital-to-analog converter 13 off Is a reference parameter.
The receiving end of the lidar system is usually implemented by an Application Specific Integrated Circuit (ASIC) chip. The detection threshold value provided by the digital-to-analog converter 13 for the comparator 12 is determined based on the reference voltage inside the ASIC chip, but the reference voltages of different chips have deviations due to the process, and the relative value changes with the temperature, and after superposition, the temperature drift in the whole working temperature range (-45 to 120 ℃) can be greater than 20mV, which is equivalent to the maximum amplitude of tens of photons of the input optical pulse signal. Most of the input light pulses have peak amplitudes around 100 photons, and it can be seen that temperature drift calibration is necessary for lidar accurate to single photon measurement accuracy.
At present, the existing method for adjusting the temperature drift mainly changes the amplitude of an input signal by measuring the temperature of a system and adjusting the bias voltage of a detector according to the measured value of the temperature. Alternatively, the system threshold D input to the DAC 13 is adjusted based on the temperature measurement in Thereby resetting the detection threshold of the comparator 12.
However, by measuring the temperature of the system to adjust the temperature drift, the time is required to measure the temperature, the required period is long, and the laser ranging is stopped during the temperature measurement process, so that the whole laser radar measurement is dead-zone. Meanwhile, the temperature needs to be measured and calibrated before the radar leaves the factory, and the cost is increased to a great extent. At present, a simple and mature method which does not need a temperature sensor is not available for compensating the change of the internal threshold value of the chip caused by temperature drift.
In order to solve the problem, the invention provides a voltage calibration method, which is applied to obtain a digital test signal with code values changing according to a preset sequence in a calibration mode, then performs digital-to-analog conversion on the digital test signal to obtain an analog test signal corresponding to the digital test signal, and then compares the voltage value of the analog test signal with a baseline voltage value to obtain a comparison result signal. And if the comparison result signal is inverted, storing the code value of the digital test signal corresponding to the inversion moment of the comparison result signal, so that the detection threshold value in the detection mode can be determined based on the stored code value, and the calibration of the detection threshold value in the detection mode is realized. The whole calibration process does not need temperature measurement, can directly complete calibration through simple triggering inside the chip, cannot influence the measurement of the laser radar, can avoid the calibration of a temperature threshold before leaving a factory, and saves the cost.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 2, an embodiment of the present invention provides a voltage calibration method, and a reference parameter D closest to a reference voltage value can be obtained by applying the method off So that the obtained reference parameter D can be used off The detection threshold is updated.
In the embodiment of the invention, the receiving end of the laser radar system has two modes, one mode is a detection mode, and the other mode is a calibration mode.
In the detection mode, the structure shown in fig. 1 can be adopted to detect the reflected laser pulse and perform positioning. In the calibration mode, the reference parameter D closest to the reference voltage value can be obtained off So that the detection threshold can be calibrated before detection.
The voltage calibration method in the calibration mode is described in detail below:
specifically, the method may comprise the steps of:
and step 21, in the calibration mode, obtaining a digital test signal with code values changing according to a preset sequence, and performing digital-to-analog conversion on the digital test signal to obtain an analog test signal corresponding to the digital test signal.
In a specific implementation, the digital test signal is used for testing to obtain a reference parameter D which can update the detection threshold value off . The digital test signal may be a periodic signal. The code values of the digital test signals may be changed in a preset order in different periods. By setting the code value of the digital test signal to change according to a preset sequence, the required reference parameter D can be obtained through testing off 。
The preset sequence can be set according to the direction of the pulse actually required to be measured in the detection mode. In the detection mode, the actual pulse to be measured, that is, the direction of the laser pulse detected by the detector during the actual detection process, is detected.
For example, when the echo pulse direction is a reverse pulse, the counter may gradually decrease from a maximum value to a minimum value, such as 0, in steps according to the precision bit width of the digital-to-analog converter; alternatively, when the echo pulse direction is a forward pulse, the counter may be increased in steps from a minimum value, e.g., 0, to a maximum value allowed by the DAC precision, depending on the precision bit width of the digital-to-analog converter. Specifically, when the echo pulse detected by the detector is a reverse pulse, as shown in fig. 3 (a), the reverse pulse is a pulse downward from the baseline. At this time, the baseline voltage value is relatively high voltage, and the digital test signal is a digital signal whose code value gradually decreases with the periodic variation. Wherein, by relatively high voltage, it is meant that the baseline voltage value is above the detection threshold. For example, the digital test signal may be gradually reduced from a full "1" of 8-bit binary numbers to a full "0" of 8-bit binary numbers.
When the echo pulse detected by the detector is a forward pulse, as shown in fig. 3 (b), the forward pulse is a pulse from the baseline upward. At this time, the baseline voltage value is relatively low voltage, and the digital test signal is a digital signal with a code value gradually increasing along with the periodic variation. Wherein by relatively low voltage is meant that the baseline voltage value is below the detection threshold. For example, the digital test signal may be gradually increased from an 8-bit binary number of all "0" to an 8-bit binary number of all "1".
In an embodiment of the invention, the code value of the digital test signal corresponds to the voltage value of the analog test signal after the digital-to-analog conversion. When the code value of the digital test signal changes, the voltage value of the analog test signal also changes correspondingly.
It should be noted that, when the code value of the digital test signal changes, the step length of the voltage value change of the analog test signal can be set according to actual requirements. The smaller the step size of the voltage value change of the analog test signal is, the more accurate the detection threshold value obtained after final calibration is.
And step 22, comparing the voltage value of the analog test signal with the baseline voltage value to obtain a comparison result signal.
In a specific implementation, the analog-to-digital converter correspondingly outputs an analog test signal according to the code value of the received digital test signal. And comparing the obtained voltage value of each analog test signal with the baseline voltage value to obtain a comparison result signal.
When the digital test signal changes from large to small or from small to large, the analog test signal also changes from large to small or from small to large based on the preset step length. Wherein the step size of the analog test signal is determined based on the value of the Least Significant Bit (LSB) of the analog-to-digital converter itself.
Preferably, the comparison result signal transitions when the relative magnitude of the voltage value of the analog test signal to the baseline voltage value changes.
And step 23, when the comparison result signal is inverted, storing the code value of the digital test signal corresponding to the inversion moment of the comparison result signal, so as to determine the detection threshold value in the detection mode based on the stored code value.
In a specific implementation, the comparison result signal is used to characterize a change in a difference between the voltage value of the analog test signal and the baseline voltage value. When the difference between the voltage value of the analog test signal and the baseline voltage value does not change, the comparison result signal may always be a logic "0", or always be a logic "1". The comparison result signal toggles from a logic "0" to a logic "1" or from a logic "1" to a logic "0" upon a change in the difference between the voltage value of the analog test signal and the baseline voltage value.
In the embodiment of the invention, the code value of the digital test signal corresponding to the signal inversion time of the comparison result is used as the reference parameter D for updating the detection threshold value off . At this time, it can be considered that the voltage value of the analog test signal is closest to the reference voltage value, that is, the influence by the temperature drift is minimal.
For example, referring to fig. 4, when the calibration enable signal cal _ en is at a high levelAnd then, entering a calibration mode. At this time, the code value of the digital test signal is set to 2 n -1 is gradually reduced to 0, where n is the precision bit width of the analog-to-digital converter. Accordingly, the voltage value V _ TH of the analog test signal gradually decreases and approaches the reference voltage value V _ BL. When V _ TH is greater than V _ BL, the logic value of the comparison result signal is always logic "0". At time t1, V _ TH is smaller than V _ BL, and the logic value of the comparison result signal is inverted from logic "0" to logic "1".
At this time, the code value of the digital test signal corresponding to the time t1, that is, the reference parameter D for updating the detection threshold value is considered off 。
By the method, the voltage value of the analog test signal is compared with the baseline voltage value, and the code value of the digital test signal at the time of jumping is kept as the new reference parameter D off It can be ensured that the baseline voltage across the comparator is relatively close in the actual detection, i.e. the baseline voltage V _ BL is closer to the reference voltage V Doff The voltage difference between the two should be smaller than the voltage value of one minimum output unit of the digital-to-analog converter.
Generally speaking, the step size of the output voltage of the digital-to-analog converter according to the present scheme is a few millivolts, i.e., the calibrated baseline voltage V _ BL and the reference voltage V Doff The voltage difference between them will be less than a few tenths of a millivolt, a great improvement over before calibration.
In an embodiment of the invention, when the digital test signal stops changing, a voltage value difference between a code value corresponding to the digital test signal and a code value of the digital test signal corresponding to the comparison result signal inversion time is greater than a preset difference threshold.
In particular implementations, the preset difference threshold may correspond to a step size, such as a predetermined number of analog test signals; alternatively, it may correspond to a predetermined voltage value, such as x millivolts, etc.
For example, for a digital test signal that is gradually decreased from a high level, when the analog test voltage corresponding to the digital test signal is changed from being greater than the baseline voltage to being less than the baseline voltage, so as to cause the comparison result signal to flip, the digital test signal is continuously decreased one by one, and is decreased N times, that is, the analog test signal corresponding to the digital test signal at this time is stopped after the step size of N LSBs is decreased.
For another example, for a digital test signal that gradually decreases from a high level, when the analog test voltage corresponding to the digital test signal changes from greater than the baseline voltage to less than the baseline voltage, so as to cause the comparison result signal to flip, the digital test signal continues to gradually decrease, and each time it is determined whether the difference between the analog test signal corresponding to the digital test signal and the baseline voltage is greater than x millivolts, the jump is stopped when the difference is greater than x millivolts.
Therefore, the difference value between the analog test voltage and the baseline voltage when jumping is stopped is larger, and error jumping of the comparator caused by burrs or jitters and the like can be reduced.
The preset difference threshold may be set to be greater than a change step of the digital-to-analog converter, that is, greater than a change step of the voltage value of the analog test signal, for example, the preset difference threshold may be an integer multiple of the change step of the digital-to-analog converter, so that when the change is stopped, the voltage value of the analog test signal is far away from the reference voltage value, and the false inversion of the comparator is reduced.
More preferably, referring to fig. 4, the digital test signal may be gradually reduced from all 1 s to all 0 s, and accordingly, the analog test voltage is gradually reduced from the full scale voltage of the digital-to-analog converter to 0 s, so as to minimize the occurrence probability of false flip. Moreover, the implementation logic of the method is simple, and an additional judging or counting module is not required to be added.
In an embodiment of the present invention, comparing the voltage value of the analog test signal with the baseline voltage value to obtain a comparison result signal, may further include: comparing the voltage value of the analog test signal with a baseline voltage value to obtain an initial comparison result signal; and filtering the burrs in the initial comparison result signal to obtain the comparison result signal.
The burr in the initial comparison result signal is filtered, and the comparison result signal after filtering the burr is used as a final comparison result signal, so that the error upset of the comparison result signal can be further reduced, and the calibration precision is improved.
In specific implementation, the voltage calibration method can be implemented by adopting various structures, and is not limited in particular.
In an embodiment of the present invention, referring to fig. 5, there is provided a voltage calibration circuit, which may include: a digital-to-analog converter 51, a comparator 52 and a memory 53. The comparator 52 includes a first input terminal and a second input terminal.
Specifically, the digital-to-analog converter 51 is adapted to, in the calibration mode, obtain a digital test signal whose code value changes according to a preset sequence, perform digital-to-analog conversion on the digital test signal to obtain an analog test signal corresponding to the digital test signal, and input the analog test signal to a first input end of the comparator 52.
The comparator 52 is connected to the digital-to-analog converter 51, and is adapted to compare the voltage value of the analog test signal with the baseline voltage value input by the second input terminal to obtain a comparison result signal;
the memory 53 is connected with the comparator 52 and is adapted to store the code value of the digital test signal corresponding to the signal inversion time of the comparison result when the comparison result signal is inverted; the stored code values are used to calibrate the detection threshold.
In an embodiment of the invention, when the echo pulse detected by the detector is a reverse pulse, the baseline voltage value is a relatively high voltage, and the digital test signal is a digital signal with a code value gradually decreasing with a period change. Wherein, by relatively high voltage, it is meant that the baseline voltage value is above the detection threshold.
In another embodiment of the present invention, when the echo pulse detected by the detector is a forward pulse, the baseline voltage value is relatively low, and the digital test signal is a digital signal with a code value gradually increasing with a period change. Wherein by relatively low voltage is meant that the baseline voltage value is below the detection threshold.
In particular embodiments, comparisonsFor example, referring to fig. 9, the input time of the digital-to-analog converter 51 is shifted to generate a glitch in V _ TH, noise may jitter V _ TH and V _ BL with a certain probability, and overshoot or undershoot may be generated when V _ TH changes, which may cause the comparator 52 to flip over the threshold. After the comparator 52 triggers sampling by false inversion, a false reference parameter D is obtained off And will be a few LSBs of the DAC (LSB is the minimum output of the DAC) from the actual value, as shown in figure 9, it can be seen that the greater the probability that the comparator 52 will output a spur 91 where V _ TH and V _ BL are close.
In an embodiment of the present invention, in order to reduce false inversion of the comparator 52 as much as possible and improve the calibration accuracy, referring to fig. 6, the comparator 52 may include: a comparator circuit 521 and a filter circuit 522.
Wherein:
the comparison circuit 521, connected to the digital-to-analog converter 51, is adapted to compare the voltage value V _ TH of the analog test signal with the baseline voltage value V _ BL to obtain an initial comparison result signal CMP _ OUT;
a filtering circuit 522, connected to the comparing circuit 521, adapted to filter glitches in the initial comparison result signal CMP _ OUT to obtain the comparison result signal S _ EN.
In a specific implementation, the filtering circuit 522 may be an RC filter circuit. The RC filter circuit may filter out a pulse having a pulse width smaller than a preset width threshold from the initial comparison result signal to obtain the comparison result signal.
Specifically, referring to fig. 7, the filtering circuit 522 may be composed of a first inverting module 71, a second inverting module, a resistor R and a capacitor C. One end of the first inverting module 71 is connected to the output end of the comparing circuit. The resistor R is connected to the first inverter module 71. The capacitor C is connected to the resistor R and the second inverting module 72. One end of the second inverting module 72 is used as the output end of the filtering circuit 522 and the memory.
The filtering by the RC filter circuit can filter OUT the pulses that are erroneously inverted in the initial comparison result signal CMP _ OUT. As shown in fig. 4. Compared with the initial comparison result signal CMP _ OUT and the comparison result signal S _ EN, the pulse smaller than a certain width is filtered, and the pulse with a large width is also reduced to a certain extent.
In specific implementations, the memory 53 may be implemented by various circuit structures, and is not limited in particular.
In an embodiment of the present invention, referring to fig. 8, the memory 53 may include: a period division sub-circuit 531, a clock signal generation sub-circuit 532, and a sampling control sub-circuit 533; wherein:
the period dividing sub-circuit 531 is connected to the Clock signal input terminal of the memory, and is adapted to count the period of the Clock signal Clock input from the Clock signal input terminal;
the clock signal generation sub-circuit 532, connected to the period division sub-circuit 531, is adapted to generate a frequency-divided clock signal CK dcnt And in the frequency-divided clock signal CK dcnt Generates a storage clock signal s _ clk for each cycle of (a); the period of the storage clock signal is also the length of the extended time window; the code value of the digital test signal jumps according to the period of the frequency division clock signal;
the storage control sub-circuit 533, connected to the clock signal generating sub-circuit 532, is adapted to store a code value of the digital test signal corresponding to the inversion time of the comparison result signal S _ EN at a preset storage time corresponding to the storage clock signal S _ clk and when the comparison result signal S _ EN is inverted, so as to obtain a sampling result corresponding to each period of the storage clock signal S _ clk.
In a specific implementation, the frequency-divided clock signal CK dcnt The period of (c) may be an integral multiple of the Clock signal Clock period input to the Clock signal input terminal; wherein the frequency-divided clock signal CK dcnt A count trigger signal for the digital test signal; a period of the storage clock signal s _ clk is a length of the extended time window. The adjusting clock signal CK en For controlling the growth ofTo the storage clock signal s _ clk. The extended time window may be an integer multiple of the Clock signal Clock period.
In a specific implementation, the clock signal CK is divided based on dcnt The adjusted clock signal CK can be generated in various ways en And are not particularly limited. For example, it can be based directly on the frequency-divided clock signal CK dcnt Generating an adjusted clock signal CK en And as the storage clock signal s _ clk.
As a preferred embodiment, the adjusting clock signal CK can also be generated en Then, an Integrated Clock Gating (ICG) circuit is triggered to generate the storage Clock signal s _ clk, making it more suitable for digital circuit design.
In an embodiment of the present invention, referring to fig. 8, the storage control sub-circuit 533 may include: a selection module MUX and a storage module register, wherein:
the selection module MUX is connected with the storage module register and is adapted to rewrite the originally stored sampling result in the memory 53 into the storage module register when the comparison result signal S _ EN is not inverted; and when the comparison result signal S _ EN is inverted, storing the code value of the digital test signal corresponding to the inversion moment of the comparison result signal S _ EN into a storage module register.
FIG. 9 is a timing diagram of the voltage calibration circuit according to the embodiment of the present invention. Referring to fig. 8 and 9, in particular, the period dividing sub-circuit 531 may be a counter to count the period of the Clock signal Clock. The period of the frequency-divided clock signal is positively correlated with the settling time of the output voltage of the digital-to-analog converter.
Frequency-divided clock signal CK dcnt And adjusting the clock signal CK en The Clock signal CK may be divided by the frequency of the Clock signal Clock dcnt And adjusting the clock signal CK en And the frequency is the same. For example, the frequency-divided Clock signal CK is generated at 0 cycle of the Clock signal Clock dcnt Generating the adjusted Clock signal CK at the 5 th Clock cycle of the Clock signal Clock en 。
When CK en In the case of =1, the integrated clock gating circuit may generate a storage clock signal S _ clk, and only when a rising edge of the storage clock signal S _ clk and a comparison result signal S _ EN =1 output by the filtering circuit are simultaneously active (i.e., simultaneously at a high level), the code value D corresponding to the digital test signal at this time may be set dcnt And sampling to a memory module register for storage.
When the storage clock signal S _ clk is not rising or the comparison result signal S _ EN =0 outputted by the filtering circuit, the selection module MUX rewrites the originally stored sampling result in the memory 53 into the storage module register.
Therefore, when the digital test signal stops changing, the difference between the code value corresponding to the digital test signal and the code value of the digital test signal corresponding to the comparison result signal turning moment is larger than a preset difference threshold value, so that the voltage value corresponding to the analog test signal is far away from the baseline voltage value when the digital test signal stops changing, and the probability of sampling caused by error turning of the comparator due to noise is reduced.
In specific implementation, the voltage calibration circuit provided by the invention can start voltage calibration in two adjacent scanning gaps of the laser radar to obtain an updated reference parameter D off . Reference parameter D that can be obtained last time when switching from calibration mode to probing mode off And calibrating the detection threshold. It is also possible to obtain a plurality of code values, i.e. a plurality of reference parameters D, by a plurality of calibration processes of the voltage calibration circuit off And counting the code values to obtain a code value for calibrating the voltage to be calibrated.
For example, the voltage calibration circuit performs 5 calibration processes to obtain 5 reference parameters Doff, and the five reference parameters D are used off And averaging, and using the averaged result as a code value for calibrating the detection threshold so as to further improve the calibration accuracy.
In an embodiment of the present invention, with continued reference to fig. 6, the voltage calibration circuit may further include: a timing circuit 54, a threshold determination circuit 55, and a switching circuit 56. Wherein:
the timing circuit 54, connected to the clock signal generation sub-circuit and the switching circuit 56, is adapted to generate a frequency-divided clock signal CK according to the clock signal generation sub-circuit dcnt Generating the digital test signal, the digital test signal and the frequency-divided clock signal CK dcnt The periods of the same;
the threshold determination circuit 55, connected to the switching circuit 56 and the memory 53, is adapted to obtain a code value D for calibrating the detection threshold dcnt And based on the code value D for calibrating the detection threshold dcnt Obtaining the detection threshold value;
the switching circuit 56, connected to the timing circuit 54, the dac 51 and the memory 53, is adapted to connect the output of the threshold determination circuit 55 to the dac 51 under the control of the calibration enable signal cal _ en so that the voltage calibration circuit enters the probing mode, or to connect the output of the timing circuit 54 to the dac 51 so that the voltage calibration circuit is in the calibration mode.
In a specific implementation, the calibration enable signal cal _ en may be made high between two adjacent laser radar scan gaps. When the calibration enable signal cal _ en is at a high level, the digital test signal output by the timer circuit 54 is input to the dac 51 through the switch circuit 56, and the dac 51 performs dac conversion on the digital test signal to obtain the voltage value V _ TH of the analog test signal. The comparison circuit 521 compares the voltage value V _ TH of the analog test signal with the baseline voltage value V _ BL to obtain an initial comparison result signal CMP _ OUT. The initial comparison result signal CMP _ OUT is filtered by the filtering circuit 522 to obtain the comparison result signal S _ EN. The memory 53 stores a code value D of the digital test signal under the control of the comparison result signal S _ EN dcnt Sampling is performed.
After the calibration is completed, the calibration enable signal cal _ en may be set to a low level, and at this time, the threshold determination circuit 55 reads the reference parameter D stored in the memory 53 off Reuse of input System threshold D in According toThe code value corresponding to the obtained detection threshold is D in the formula (1) vth . The code value corresponding to the detection threshold value is D vth The signal is input to the digital-to-analog converter 51 through the switching circuit 56, and the obtained corresponding detection threshold is input to the in + input terminal of the comparison circuit 521. At this time, the in-input terminal of the comparison circuit 521 inputs the electrical analog signal generated by the detector. The comparison circuit 521 compares the electrical analog signal generated by the detector with a detection threshold to locate the position of the object.
By arranging the timing circuit 54, the threshold value determining circuit 55 and the switching circuit 56, the digital-to-analog converter 51 and the comparator 52 can be multiplexed by the receiving end of the laser radar system in the detection mode and the calibration mode, so that the structure of the receiving end of the laser radar system can be simplified, and the circuit area can be further reduced.
It should be noted that, in some embodiments, the receiving end of the lidar system may also use a separate digital-to-analog converter 51 and a separate comparator 52 in the detection mode and the calibration mode, which is not limited herein.
By adopting the scheme of the embodiment of the invention, the detection threshold is calibrated, and the voltage error Verr (N) of the detection threshold after final calibration is as follows:
V err (N)＝V dac_lsb +V dac_INL (N)+V n (N) (2)
wherein N is the input D in Numerical values in the range of 0 to 2 n -1, n is the total DAC bit width. V daa_lsb Is the analog voltage value of the smallest step of the digital-to-analog converter, which is a known quantity. V dac_INL Is the linearity (INL) of the digital-to-analog converter and the Root Mean Square (RMS) value of the comparator noise, which can be measured. V n The Root Mean Square (RMS) value of the digital to analog converter comparator noise may also be measured. V dac_INL And V n Are all associated with input N.
From V dac_lsb 、V dac_INL (N) and V n The voltage error Verr (N) formed by the three parts (N) is far less than the temperature drift of the actual V _ BL and V _ TH voltages, and the temperature drift of the sum of the V _ BL and the V _ TH voltages is also less than one V dac_sb . Thus, in the calibration mode, the embodiments of the present invention are utilizedAfter the detection threshold is calibrated by the scheme, the detection threshold can be accurate to less than one photon amplitude, the influence of noise and non-ideality in a circuit on calibration is reduced, and the measurement accuracy of the laser radar is obviously improved.
In some embodiments, the error after calibration can be controlled within 2mV, which is an order of magnitude higher than the previous temperature drift state.
As can be seen from the above, the voltage calibration method and the voltage calibration circuit in the embodiments of the present invention do not calibrate the absolute value of the voltage value of the analog test signal, only need to simulate the voltage difference between the voltage value of the test signal and the reference voltage, and do not need an additional temperature measurement feedback process, and can directly complete temperature calibration or deviation caused by other non-ideal factors through simple triggering inside the chip, so that the measurement of the laser radar is not affected, and meanwhile, calibration of the temperature threshold before leaving the factory is avoided, and the cost is saved.
The embodiment of the invention also provides a laser radar system which comprises the voltage calibration circuit.
In an embodiment, the lidar system may further include: and a detector. Wherein: the detector can be connected with the digital-to-analog converter and is suitable for detecting a laser pulse signal reflected by a target object and converting the laser pulse signal into an electrical analog signal.
The digital-to-analog converter is further adapted to acquire a preset system threshold value and a code value stored in the memory in a detection mode, obtain a corresponding detection threshold value, and output the detection threshold value to the comparator.
The comparator is connected with the digital-to-analog converter and is also suitable for comparing the electrical analog signal output by the detector with the detection threshold value and outputting a corresponding comparison result signal.
In specific implementation, the voltage calibration circuit may calibrate a detection threshold of the comparator before the detector is started each time, so as to reduce an influence of factors such as temperature drift on the detection threshold and improve positioning accuracy.
In an embodiment of the present invention, referring to fig. 4, the voltage calibration circuit may be controlled to calibrate the detection threshold of the comparator by using the calibration enable signal cal _ en. The calibration enable signal cal _ en is a periodic trigger signal or an event trigger signal.
In a specific embodiment, the period of the calibration enable signal cal _ en may be a time for the laser radar to scan one or several frames; in another specific embodiment, the calibration enable signal cal _ en may be a periodic signal of the order of milliseconds.
Preferably, the calibration enable signal cal _ en may trigger the voltage calibration circuit to calibrate the detection threshold of the comparator within a dead time of the lidar system (i.e. a time when detection is not performed), that is, when the lidar system stops detecting, the calibration enable signal cal _ en is controlled to jump to a high level to trigger the voltage calibration circuit according to the present invention to enter a calibration mode to perform calibration using the dead time of the lidar system, so that the detector does not need to spend additional calibration time, i.e. detection does not need to be delayed, and an influence on a detection process is reduced.
In a preferred embodiment, the calibration enable signal cal _ en can be set as at least two frequency periodic trigger signals, the calibration enable signal cal _ en of each frequency is matched with the ambient temperature, and the trigger voltage calibration circuit calibrates the detection threshold of the comparator at different ambient temperatures by using the corresponding calibration enable signal cal _ en, for example, when the ambient temperature is low, the calibration enable signal cal _ en with high frequency is used for calibration, and when the ambient temperature is high, the calibration enable signal cal _ en with low frequency is used for calibration, so that the overall power consumption of the lidar system can be reduced.
An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform any step of the voltage calibration method in the foregoing embodiments, which is not described herein again.
In particular implementations, the computer-readable storage medium may include: ROM, RAM, magnetic or optical disks, and the like.
Each module/unit included in each apparatus and product described in the above embodiments may be a software module/unit, or may also be a hardware module/unit, or may also be a part of a software module/unit and a part of a hardware module/unit. For example, for each apparatus and product applied to or integrated into a chip, each module/unit included in the apparatus and product may all be implemented by hardware such as a circuit, or at least a part of the modules/units may be implemented by a software program running on a processor integrated within the chip, and the remaining (if any) part of the modules/units may be implemented by hardware such as a circuit; for each device or product applied to or integrated with the chip module, each module/unit included in the device or product may be implemented by using hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components of the chip module, or at least some of the modules/units may be implemented by using a software program running on a processor integrated within the chip module, and the rest (if any) of the modules/units may be implemented by using hardware such as a circuit; for each device and product applied to or integrated in the terminal, each module/unit included in the device and product may be implemented by using hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal, or at least part of the modules/units may be implemented by using a software program running on a processor integrated in the terminal, and the rest (if any) part of the modules/units may be implemented by using hardware such as a circuit.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (22)
1. A method of voltage calibration, comprising:
in a calibration mode, obtaining a digital test signal with code values changing according to a preset sequence, and performing digital-to-analog conversion on the digital test signal to obtain an analog test signal corresponding to the digital test signal;
comparing the voltage value of the analog test signal with a baseline voltage value to obtain a comparison result signal;
and when the comparison result signal is inverted, storing a code value of the digital test signal corresponding to the inversion moment of the comparison result signal so as to determine a detection threshold value in a detection mode based on the stored code value.
2. The voltage calibration method of claim 1, wherein the digital test signal is a periodically varying signal, the baseline voltage value is a relatively high voltage, and the digital test signal is a digital signal having a code value that gradually decreases with the periodic variation.
3. The voltage calibration method of claim 1, wherein the digital test signal is a periodically varying signal, the baseline voltage value is a relatively low voltage, and the digital test signal is a digital signal having a code value that gradually increases with the periodic variation.
4. The voltage calibration method according to claim 1, wherein when the digital test signal stops changing, a difference between a code value corresponding to the digital test signal and a code value corresponding to a signal inversion time of the comparison result is greater than a preset difference threshold.
5. The voltage calibration method of claim 1, wherein comparing the voltage value of the analog test signal with a baseline voltage value to obtain a comparison result signal further comprises:
comparing the voltage value of the analog test signal with a baseline voltage value to obtain an initial comparison result signal;
and filtering the burrs in the initial comparison result signal to obtain the comparison result signal.
6. A voltage calibration circuit, comprising: a digital-to-analog converter, a comparator and a memory;
the comparator comprises a first input end and a second input end; wherein:
the digital-to-analog converter is suitable for acquiring digital test signals with code values changing according to a preset sequence in a calibration mode, performing digital-to-analog conversion on the digital test signals to acquire analog test signals corresponding to the digital test signals, and inputting the analog test signals to a first input end of the comparator;
the comparator is connected with the digital-to-analog converter and is suitable for comparing the voltage value of the analog test signal with the baseline voltage value input by the second input end to obtain a comparison result signal;
the memory is connected with the comparator and is suitable for storing the code value of the digital test signal corresponding to the signal turning moment of the comparison result when the comparison result signal is turned; the stored code values are used to calibrate the detection threshold.
7. The voltage calibration circuit of claim 6, wherein the digital test signal is a periodic signal, the baseline voltage value is a relatively high voltage, and the digital test signal is a digital signal having a code value that gradually decreases with period.
8. The voltage calibration circuit of claim 6, wherein the digital test signal is a periodic signal, the baseline voltage value is a relatively low voltage, and the digital test signal is a digital signal with a code value that gradually increases with period.
9. The voltage calibration circuit according to claim 6, wherein when the digital test signal stops changing, a difference between a code value corresponding to the digital test signal and a code value of the digital test signal corresponding to a signal inversion time of the comparison result is greater than a preset difference threshold.
10. The voltage calibration circuit of claim 6, wherein the comparator comprises:
the comparison circuit is connected with the digital-to-analog converter and is suitable for comparing the voltage value of the analog test signal with the baseline voltage value to obtain an initial comparison result signal;
and the filtering circuit is connected with the comparison circuit and is suitable for filtering the burrs in the initial comparison result signal to obtain the comparison result signal.
11. The voltage calibration circuit of claim 10, wherein the filtering circuit is adapted to filter out pulses having a pulse width less than a predetermined width threshold from the initial comparison result signal to obtain the comparison result signal.
12. The voltage calibration circuit of claim 10, wherein the filtering circuit comprises:
the first inverting module, the resistor, the capacitor and the second inverting module; wherein:
the first inverting module is connected with the output end of the comparison circuit;
the resistor is connected with the first inverting module;
the capacitor is connected with the resistor and the second inverting module;
the second inverting module is connected with the memory.
13. The voltage calibration circuit of claim 10, wherein the memory comprises: a periodic dividing sub-circuit, a clock signal generating sub-circuit and a sampling control sub-circuit; wherein:
the period dividing sub-circuit is connected with a clock signal input end of the memory and is suitable for counting the period of the clock signal input by the clock signal input end;
the clock signal generating sub-circuit is connected with the periodic dividing sub-circuit and is suitable for generating a frequency dividing clock signal with the period being the length of the extended time window and generating a storage clock signal in each period of the frequency dividing clock signal; the period of the storage clock signal is also the length of the extended time window;
the code value of the digital test signal jumps according to the period of the frequency division clock signal;
the storage control sub-circuit is connected with the clock signal generating sub-circuit and is suitable for storing the code value of the digital test signal corresponding to the turnover time of the comparison result signal at the preset storage time corresponding to the storage clock signal when the comparison result signal is turned over, so that the sampling result corresponding to each period of the storage clock signal is obtained.
14. The voltage calibration circuit of claim 13, wherein the storage control sub-circuit comprises: selection module and storage module, wherein:
the selection module is connected with the storage module and is suitable for rewriting the sampling result originally stored in the memory into the storage module when the comparison result signal is not turned over; and when the comparison result signal is turned over, storing the code value of the digital test signal corresponding to the turning moment of the comparison result signal into the storage module.
15. The voltage calibration circuit of claim 13, wherein the digital test signal is a periodic signal and the extended time window is any integer number of cycles of the clock signal.
16. The voltage calibration circuit of claim 13, wherein a plurality of code values obtained through a plurality of calibration processes of the voltage calibration circuit are counted to obtain a code value for calibrating the detection threshold.
17. The voltage calibration circuit of claim 13, further comprising: the circuit comprises a timing circuit, a threshold value determining circuit and a switching circuit; wherein:
the timing circuit is connected with the clock signal generating sub-circuit and the switching circuit and is suitable for generating the digital test signal according to the frequency division clock signal generated by the clock signal generating sub-circuit, and the period of the digital test signal is the same as that of the frequency division clock signal;
the threshold value determining circuit is connected with the switching circuit and the memory, is suitable for acquiring a code value for calibrating the detection threshold value, and obtains the detection threshold value based on the code value for calibrating the detection threshold value;
the switching circuit is connected with the timing circuit, the digital-to-analog converter and the memory, and is suitable for connecting the output of the threshold value determining circuit with the digital-to-analog converter under the control of a calibration enabling signal so that the voltage calibration circuit enters a detection mode, or connecting the output of the timing circuit with the digital-to-analog converter so that the voltage calibration circuit is in a calibration mode.
18. A lidar system comprising the voltage calibration circuit of any of claims 6 to 17.
19. The lidar system of claim 18, further comprising: a detector; wherein:
the detector is connected with the digital-to-analog converter and is suitable for detecting a laser pulse signal reflected by a target object and converting the laser pulse signal into an electrical analog signal;
the digital-to-analog converter is also suitable for acquiring a preset system threshold value and a code value stored in the memory in a detection mode to obtain a corresponding detection threshold value and outputting the detection threshold value to the comparator;
the comparator is connected with the digital-to-analog converter and is also suitable for comparing the electrical analog signal output by the detector with the detection threshold value and outputting a corresponding comparison result signal.
20. The lidar system of claim 19, wherein the voltage calibration circuit calibrates the detection threshold of the comparator before each activation of the detector.
21. The lidar system of claim 19, wherein the voltage calibration circuit is controlled to calibrate a detection threshold of the comparator using a calibration enable signal; the calibration enable signal is a periodic trigger signal or an event trigger signal.
22. A computer-readable storage medium, on which a computer program is stored, which computer program is executable by a processor for carrying out the steps of the method according to any one of claims 1 to 5.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116540074A (en) * | 2023-05-09 | 2023-08-04 | 武汉芯必达微电子有限公司 | Method and device for calibrating internal voltage source of chip in factory |
| CN116613084A (en) * | 2023-07-17 | 2023-08-18 | 深圳市思远半导体有限公司 | Chip, test machine, calibration method of internal comparator of chip and related equipment |
-
2021
- 2021-06-15 CN CN202110663079.6A patent/CN115480234A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116540074A (en) * | 2023-05-09 | 2023-08-04 | 武汉芯必达微电子有限公司 | Method and device for calibrating internal voltage source of chip in factory |
| CN116613084A (en) * | 2023-07-17 | 2023-08-18 | 深圳市思远半导体有限公司 | Chip, test machine, calibration method of internal comparator of chip and related equipment |
| CN116613084B (en) * | 2023-07-17 | 2024-02-23 | 深圳市思远半导体有限公司 | Chip, test machine, calibration method of internal comparator of chip and related equipment |
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