CN116612801B - Erasing method and decoding circuit of small-capacity storage array - Google Patents
Erasing method and decoding circuit of small-capacity storage array Download PDFInfo
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Abstract
The application discloses an erasing method and a decoding circuit of a small-capacity storage array, and relates to the technical field of semiconductor integrated circuits. The method is used for erasing a memory array, and comprises the following steps: detecting whether the redundant protection enable is started or not when the memory array is in an erasing step; if yes, establishing a mapping relation, wherein the mapping relation is used for mapping the processing operation of the word line address of the redundant memory cell into the processing operation of the word line address of the configuration memory cell; performing erasing operation on the small-capacity storage array according to the mapping relation; the erasing method establishes the mapping relation between the word line address of the redundant memory cell and the word line address of the configuration memory cell, so that when the small-capacity memory array is erased and the address is addressed to the redundant memory cell, the word line address of the redundant memory cell is not selected in logic processing, and the protection redundant information is not erased.
Description
Technical Field
The present application relates to the field of semiconductor integrated circuits, and more particularly, to an erasing method and decoding circuit for a small-capacity memory array.
Background
For NOR flash, a small-capacity storage array is generally adopted to store configuration information and redundant information required by the operation of a chip, part of storage units of the storage array are used for storing the configuration information, and the other part of storage units are used for storing the redundant information; the minimum unit erased is 1 sector, so that all information is erased when configuration information is changed by erasing operation on the memory array; however, the redundant information is recorded by the chip circuit detection stage and related to whether the memory cells in the main area are good or bad or not and the redundant memory cells are replaced, and the redundant information is not changed generally unless the bad memory cells are found in the main area later. The configuration information is changed frequently in the chip debugging stage, and if the redundant information is changed when the configuration information is changed, repeated work is brought, and the working efficiency is reduced.
In view of the above problems, no effective technical solution is currently available.
Disclosure of Invention
The application aims to provide an erasing method and a decoding circuit of a small-capacity storage array, which are used for protecting redundant information from being erased by establishing a mapping relation between word line addresses of redundant storage units and word line addresses of configuration storage units.
In a first aspect, the present application provides an erase method of a small capacity storage array for erasing the storage array, the erase method comprising the steps of:
detecting whether the redundant protection enable is started or not when the memory array is in an erasing step;
if yes, establishing a mapping relation, wherein the mapping relation is used for mapping the processing operation of the word line address of the redundant storage unit into the processing operation of the word line address of the configuration storage unit, the redundant storage unit is used for storing redundant information, and the configuration storage unit is used for storing configuration information;
and performing erasing operation on the small-capacity storage array according to the mapping relation.
According to the erasing method of the small-capacity storage array, the mapping relation between the word line address of the redundant storage unit and the word line address of the configuration storage unit is established, so that when the small-capacity storage array is subjected to erasing operation and the address is addressed to the redundant storage unit, the word line address of the redundant storage unit is not selected in logic processing, and the redundant information is protected from being erased.
In a second aspect, the present application also provides a decoding circuit of a small capacity storage array for word line decoding of memory cells, the small capacity storage array for storing configuration information and redundancy information, the decoding circuit comprising:
The output ends of the first word line decoders are connected with the word line addresses of the partial configuration storage units;
a plurality of mapping circuits for decoding word line addresses of redundant memory cells and for decoding word line addresses of remaining configuration memory cells, and mapping the word line addresses of the redundant memory cells to the word line addresses of the remaining configuration memory cells when redundancy protection enable is turned on;
the first word line decoder and the mapping circuit are both connected to the same address line for word line decoding.
The decoding circuit of the small-capacity storage array of the application utilizes the mapping circuit to establish mapping resolution, and maps the word line address of the redundant storage unit to the word line address of the configuration storage unit, so that when the small-capacity storage array is subjected to erasing operation and the address is addressed to the redundant storage unit, the word line address of the redundant storage unit is not selected in logic processing, thereby protecting redundant information from being erased.
Optionally, in the decoding circuit of the present application, the mapping circuit includes:
a second word line decoder for decoding word line addresses of the remaining configuration memory cells;
A redundant word line decoder for decoding word line addresses of the redundant memory cells;
a first mapper for mapping the word line address of the redundant memory cell to the word line address of the remaining configuration memory cell when the redundancy protection enable is turned on.
In the decoding circuit, the first mapper can map an operation originally performed on the word line address of the redundant memory cell to an operation performed on the word line address of the remaining configuration memory cell, and can also hold an operation originally performed on the word line address of the remaining configuration memory cell to an operation performed on the word line address of the remaining configuration memory cell.
Optionally, in the decoding circuit of the present application, the first mapper includes:
a redundant word line processing module for processing word line addresses of the redundant memory cells;
and the configuration word line processing module is used for processing the word line addresses of the rest configuration memory cells.
In the decoding circuit, the redundant word line processing module can not output the decoding result of the word line address of the redundant memory cell when the memory array is in the erasing step, and the configuration word line processing module can output the decoding result of the corresponding word line address of the rest configuration memory cell when the memory array is in the erasing step.
Optionally, in the decoding circuit of the present application, the redundant word line processing module includes:
and the protection detection module is used for detecting whether the redundant protection enabling is started or not.
Optionally, in the decoding circuit of the present application, the redundant word line processing module further includes:
and the stage detection module is used for detecting whether the small-capacity storage array is in an erasing stage.
Optionally, in the decoding circuit of the present application, the redundant word line processing module includes:
an input end of the first NOR gate is connected with an erasing stage enabling signal;
the input end of the first NOT gate is connected with a redundancy protection enabling signal;
the two input ends of the first AND gate are respectively connected with the output end of the first NOT gate and the erasing step enabling signal;
the two input ends of the second NOR gate are respectively connected with the output end of the first NOR gate and the output end of the first AND gate, and the output end of the second NOR gate is connected with the word line address of the redundant memory cell;
an output of the redundant word line decoder is connected to another input of the first nor gate.
In the decoding circuit, the redundant word line processing module sets the first NOR gate, the first AND gate and the second NOR gate to establish processing logic for the word line address of the redundant memory cell, and simultaneously, the first AND gate is used for acquiring an erasure step enabling signal, the first NOR gate is used for acquiring a redundant protection enabling signal and the first NOR gate is used for acquiring an erasure stage enabling signal, so that the decoding circuit of the application can output or not output a decoding result of the word line address of the redundant memory cell according to the erasure stage enabling signal, the redundant protection enabling signal and the erasure stage enabling signal.
Optionally, in the decoding circuit of the present application, the configuration word line processing module includes:
the second AND gate, an input end of the second AND gate is connected with a redundant erasing inversion signal, and the redundant erasing inversion signal is an output signal of the first AND gate;
an input end of the first OR gate is connected with an output end of the second AND gate, and an output end of the first OR gate is connected with the word line address of the rest configuration memory unit;
an output end of the second word line decoder is connected with the other input end of the first OR gate;
an output of the redundant word line decoder is connected to the other input of the second AND gate.
In the decoding circuit, the configuration word line processing module is provided with a second AND gate and a first OR gate, so that processing logic for the word line addresses of the rest configuration memory cells is established, and meanwhile, the second AND gate is utilized to acquire a redundancy erasure inversion signal, so that the decoding circuit can establish or cancel the mapping relation between the word line addresses of the redundancy memory cells and the word line addresses of the rest configuration memory cells according to the redundancy erasure inversion signal.
Optionally, in the decoding circuit of the present application, the redundant word line processing module includes:
A second NOT gate;
the two input ends of the third NOR gate are respectively connected with the output end of the second NOR gate and the enabling signal of the erasing step, and the output end of the third NOR gate is connected with the word line address of the redundant memory cell;
an output of the redundant word line decoder is coupled to an input of the second NOT gate.
In the decoding circuit, the redundant word line processing module is provided with a second NOT gate and a third NOT gate, so that processing logic for the word line address of the redundant memory cell is established, and meanwhile, an erasing step enabling signal is acquired by the third NOT gate, so that the decoding circuit can output or not output a decoding result of the word line address of the redundant memory cell according to the erasing step enabling signal.
Optionally, in the decoding circuit of the present application, the configuration word line processing module includes:
the input end of the third AND gate is connected with the erasing step enabling signal;
an input end of the second OR gate is connected with an output end of the third AND gate, and an output end of the second OR gate is connected with the word line address of the rest configuration memory unit;
an output end of the second word line decoder is connected with the other input end of the second OR gate;
An output of the redundant word line decoder is connected to the other input of the third AND gate.
In the decoding circuit, the configuration word line processing module is provided with a third AND gate and a second OR gate, so that processing logic for the word line addresses of the rest configuration memory cells is established, and meanwhile, an erasure step enabling signal is acquired by utilizing the first AND gate, so that the decoding circuit can establish or cancel the mapping relation between the word line addresses of the redundant memory cells and the word line addresses of the rest configuration memory cells according to the erasure step enabling signal.
In view of the foregoing, the present application provides an erasing method and a decoding circuit for a small capacity memory array, where the erasing method provided by the present application establishes a mapping relationship between a word line address of a redundant memory cell and a word line address of a configuration memory cell, so that when the small capacity memory array is erased and an address is addressed to the redundant memory cell, the word line address of the redundant memory cell is not selected in logic processing, thereby protecting redundant information from being erased.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
Fig. 1 is a flowchart of an erasing method of a small capacity storage array according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a decoding circuit embodiment 1 of a small-capacity storage array according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a decoding circuit embodiment 2 of a small-capacity storage array according to an embodiment of the present application.
Fig. 4 is a schematic diagram of a decoding circuit embodiment 3 of a small-capacity storage array according to an embodiment of the present application.
Description of the reference numerals: 100. a first word line decoder; 200. a second word line decoder; 300. a redundant word line decoder; 411. a first nor gate; 412. a first NOT gate; 413. a first AND gate; 414. a second nor gate; 421. a second NOT gate; 422. a third nor gate; 511. a second AND gate; 512. a first OR gate; 521. a third AND gate; 522. a second or gate.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
In a small capacity storage array, a portion of the storage units are used to store configuration information and another portion of the storage units are used to store redundancy information. For NOR flash, the minimum unit of erasing is 1 sector, so when the configuration information is changed by the erasing operation of the memory array, all information is erased; however, the redundant information is recorded by the chip circuit detection stage and related to whether the memory cells in the main area are good or bad or not and the redundant memory cells are replaced, and the redundant information is not changed generally unless the bad memory cells are found in the main area later. The configuration information is changed frequently in the chip debugging stage, and if the redundant information is changed when the configuration information is changed, repeated work is brought, and the working efficiency is reduced.
Referring to fig. 1, fig. 1 is an erasing method of a small capacity memory array according to some embodiments of the present application, for erasing a memory array, the method includes the steps of:
a1, detecting whether redundancy protection enabling is started or not when the memory array is in an erasing step;
a2, if so, establishing a mapping relation, wherein the mapping relation is used for mapping the processing operation of the word line address of the redundant storage unit into the processing operation of the word line address of the configuration storage unit, the redundant storage unit is used for storing redundant information, and the configuration storage unit is used for storing configuration information;
a3, erasing the small-capacity storage array according to the mapping relation.
In step A1, the erasing step refers to a step of performing an erasing operation on the small-capacity storage array, and includes an erase verification phase, a pre-programming phase, an erasing phase, and the like.
In step A2, the word line address of the redundant memory cell is the word line address of the memory cell in the small-capacity memory array where the redundant information is placed, and the word line address of the configuration memory cell is the word line address of the memory cell in the small-capacity memory array where the configuration information is placed. And after detecting that the redundancy protection enabling is started, establishing a mapping relation. After the mapping relation is established, the processing operation performed on the word line addresses of the redundant memory cells in the mapping relation is mapped into the processing operation performed on the word line addresses of the corresponding configuration memory cells in the mapping relation; if the mapping relationship between the address 1111 and the address 1001 is established, the processing operation command executed on the address 1111 will be mapped into the processing operation command executed on the address 1001. The mapping relation does not affect the direction of the word line address of the configuration memory unit, namely after the mapping relation is established, the processing operation of the word line address of the configuration memory unit in the mapping relation is the processing operation normally carried out on the word line address of the configuration memory unit.
In step A3, after the mapping relationship is established, the erase operation performed on the wordline address of the configuration memory cell is still the erase operation performed on the wordline address of the corresponding configuration memory cell, and the erase operation performed on the wordline address of the redundant memory cell is the erase operation performed on the wordline address of the corresponding configuration memory cell under the mapping relationship.
In some preferred embodiments, the word line addresses of the redundant memory cells may be mapped to the word line addresses of the same configuration memory cells, which simplifies the mapping circuit logic by mapping the erase operation performed on the word line address of each redundant memory cell to the erase operation performed on the word line address of the same configuration memory cell.
In other embodiments, the word line addresses of the redundant memory cells may also be mapped to word line addresses of different configuration memory cells, and the erase operation performed on the word line address of each redundant memory cell is mapped to the erase operation performed on the word line address of the different configuration memory cell.
As can be seen from the above, in the erasing method of the small capacity memory array provided by the embodiment of the application, the mapping relation between the word line address of the redundant memory cell and the word line address of the configuration memory cell is established, so that when the small capacity memory array is erased and the address is addressed to the redundant memory cell, the word line address of the redundant memory cell is not selected in logic processing, thereby protecting the redundant information from being erased.
Referring to fig. 2, fig. 2 is a decoding circuit of a small capacity memory array for word line decoding of memory cells according to some embodiments of the present application, where the small capacity memory array is used for storing configuration information and redundancy information, and the decoding circuit includes:
a plurality of first word line decoders 100 for decoding word line addresses of the partial configuration memory cells, the output ends of the first word line decoders 100 being connected to the word line addresses of the partial configuration memory cells;
a plurality of mapping circuits for decoding the word line address of the redundant memory cell and for decoding the word line address of the remaining configuration memory cell, and mapping the word line address of the redundant memory cell to the word line address of the remaining configuration memory cell when the redundancy protection enable is turned on;
the first word line decoder 100 and the mapping circuit are both connected to the same address line for word line decoding.
In a specific application, the first word line decoders 100 and the mapping circuit are connected to the same number of address lines, and the word lines are determined by determining the decoding of the word line addresses by distinguishing the level of the address lines, that is, when the address lines completely meet the level high-low characteristics, the corresponding first word line decoders 100 or the mapping circuit are turned on to determine the word lines, and taking a four-bit word line address 0011 as an example, the level characteristics only meet the conduction requirement of the first word line decoders 100 corresponding to the word lines WL <3>, and only the first word line decoders 100 corresponding to the word lines WL <3> are turned on at this time, so that the decoding of the word line addresses is completed; in FIG. 2, addrb <0> -addrb <3> indicates that the address line is low, and addr <0> -addr <3> indicates that the address line is high.
More specifically, the word line addresses of the remaining configuration memory cells are the word line addresses of a plurality of configuration memory cells divided in the small-capacity memory array for establishing a mapping relationship; for a small capacity memory array, a plurality of consecutive memory cells with high-order addresses in the array are generally used to store redundancy information, and the remaining consecutive memory cells are used to store configuration information, so that the number of word line addresses of the configuration memory cells is greater than that of the redundant memory cells, and therefore, the mapping relationship is not required to be established by using the word line addresses of all the configuration memory cells.
More specifically, since the word line addresses of different redundant memory cells can be mapped on the word line addresses of the same configuration memory cell, the number of the word line addresses of the redundant memory cells is greater than or equal to the number of the word line addresses of the remaining configuration memory cells, and the number of the word line addresses of part of the configuration memory cells is determined by the number of the word line addresses of the remaining configuration memory cells, that is, the number of the word line addresses of the configuration memory cells that do not establish a mapping relationship is computationally determined by the number of the word line addresses of the configuration memory cells that participate in establishing a mapping relationship; in general, the number of word line addresses for a partially configured memory cell is an integer multiple of the number of word line decoder bits, such as: taking a memory array with a capacity of 16 x 32bits (48 bytes) as an example, the memory array has 16 word lines, 4 bit word line addresses are required to be set for decoding, if the number of word line addresses of redundant memory cells is 4, the number of word line addresses of the rest configuration memory cells is required to be less than or equal to 4, and the number of word line addresses of the part configuration memory cells is ensured to be an integral multiple of 4, so that the number of word line addresses of the rest configuration memory cells is determined to be 4, and the number of word line addresses of the part configuration memory cells is determined to be 8.
More specifically, the number of the word line addresses of the remaining configuration memory cells may be determined to be 1, and the word line addresses of all the redundant memory cells may be mapped to the word line addresses of the remaining configuration memory cells, thereby simplifying the mapping circuit logic.
More specifically, the first word line decoder 100 is used to decode the word line address of a part of the configuration memory cells, and the mapping circuit is used to decode the word line address of the remaining configuration memory cells and the word line address of the redundancy memory cells, and map the word line address of the redundancy memory cells to the word line address of the remaining configuration memory cells when the redundancy protection enable is turned on.
More specifically, when the redundancy protection enable is on and the array is in the erasing step, the first word line decoder 100 decodes the word line address of the partially configured memory cell, the mapping circuit decodes the word line address of the remaining configured memory cell and the word line address of the redundant memory cell, and maps the word line address of the redundant memory cell to the word line address of the remaining configured memory cell, then the erasing operation performed on the word line address of the redundant memory cell is mapped to the erasing operation performed on the word line address of the configured memory cell, and the redundant information stored by the redundant memory cell is protected; when the redundancy protection enable is turned off and the array is in the erasing step, the first word line decoder 100 decodes the word line address of the partially configured memory cell, and the mapping circuit outputs the decoding result of the word line address of the corresponding configured memory cell and the decoding result of the word line address of the corresponding redundant memory cell, so that the erasing operation is performed normally, and the redundant information is erased together with the configuration information.
The decoding circuit of the small-capacity storage array of the embodiment of the application utilizes the mapping circuit to establish mapping resolution, maps the word line address of the redundant storage unit to the word line address of the rest configuration storage units, so that when the small-capacity storage array is processed and the address is addressed to the redundant storage unit, the word line address of the redundant storage unit is not selected in logic processing, thereby protecting redundant information from being erased.
In some preferred embodiments, the mapping circuit comprises:
a second word line decoder 200 for decoding word line addresses of the remaining configuration memory cells;
a redundancy word line decoder 300 for decoding word line addresses of the redundancy memory cells;
a first mapper for mapping the word line address of the redundant memory cell to the word line address of the remaining configuration memory cells when the redundancy protection enable is turned on.
In a specific application, the output terminal of the second word line decoder 200 and the output terminal of the redundant word line decoder 300 are both connected to the input terminal of the first mapper. The first mapper is configured to obtain decoding results of the second word line decoder 200 and the redundant word line decoder 300, and when the redundancy protection is enabled and the decoding of the second word line decoder 200 or the redundant word line decoder 300 is successful, the first mapper correspondingly outputs decoding results of the word line addresses of the remaining configuration memory cells; such as: the second word line decoder 200 is used for decoding the word line <11>, and the redundant word line decoder 300 is used for decoding the word line <15>, and the first mapper is used for mapping the word line <15> to <11>, so that when the decoder for decoding the word line <11> successfully decodes, the first mapper outputs the decoding result of the word line <11>, and when the redundant word line decoder 300 for decoding the word line <15> successfully decodes, the first mapper also outputs the decoding result of the word line <11>, thereby realizing the mapping of the word line <15> to the word line <11 >; in the case where redundancy protection is enabled, the first mapper outputs a decoding result of the word line <11> when the decoder for the word line <11> is successfully decoded, and the first mapper outputs a decoding result of the word line <15> when the redundancy word line decoder 300 for the word line <15> is successfully decoded, and the corresponding decoding is normally performed.
More specifically, the first mapper can map an operation originally performed on the word line address of the redundant memory cell to an operation performed on the word line address of the remaining configuration memory cell when the redundancy protection enable is turned on, can hold an operation originally performed on the word line address of the remaining configuration memory cell to an operation performed on the word line address of the remaining configuration memory cell, and can also hold an operation performed on the word line address of the redundant memory cell to an operation performed on the word line address of the redundant memory cell when the redundancy protection enable is turned off.
In some preferred embodiments, the first mapper comprises:
the redundant word line processing module is used for processing word line addresses of the redundant memory cells;
the configuration word line processing module is used for processing the word line addresses of the rest configuration memory cells.
In a specific application, the output end of the redundant word line decoder 300 is connected to the input end of the redundant word line processing module, and the output end of the second word line decoder 200 and the output end of the redundant word line decoder 300 are both connected to the input end of the configuration word line processing module. The redundant word line processing module is configured to obtain the decoding result of the redundant word line decoder 300, and the word line processing module is configured to obtain the decoding results of the second word line decoder 200 and the redundant word line decoder 300. When the redundancy protection enable is turned on and the memory array is in the erasing step and the redundancy word line decoder 300 decodes successfully, the redundancy word line processing module will not output the decoding result of the word line address of the corresponding redundancy memory cell. When the redundancy protection enable is turned on and the memory array is in the erasing step and the second word line decoder 200 or the redundancy word line decoder 300 decodes successfully, the configuration word line processing module outputs the decoding result of the word line address of the corresponding remaining configuration memory cell. Such as: the second word line decoder 200 is used for decoding the word line <11>, and the redundant word line decoder 300 is used for decoding the word line <15>, and when the redundancy protection is enabled and the memory array is in the erasing step and the second word line decoder 200 for decoding the word line <11> is successfully decoded, the configuration word line processing module outputs the decoding result of the word line <11 >; when the redundancy protection enable is on and the memory array is in an erase step and the redundant word line decoder 300 for decoding word line <15> successfully decodes, the redundant word line processing module does not output the decoding result of word line <15>, and the configured word line processing module outputs the decoding result of word line <11>, thereby achieving the mapping of word line <15> to word line <11 >.
More specifically, when the redundancy protection enable is turned off or the memory array is not in the erasing step and the redundancy word line decoder 300 decodes successfully, the redundancy word line processing module outputs the decoding result of the word line address of the corresponding redundancy memory cell, and the configuration word line processing module does not output the decoding result of the word line address of the corresponding remaining configuration memory cell accordingly. Such as: the redundant word line decoder 300 is used for decoding the word line <15>, and when the redundancy protection enable is turned off or the memory array is not in an erase step and the decoder for decoding the word line <15> successfully decodes, the redundant word line processing module outputs the decoding result of the word line <15>, and accordingly the configuration word line processing module does not output the decoding result of the word line <11>, thereby achieving normal decoding of the word line address of the redundant memory cell.
More specifically, the redundant word line processing module is capable of not outputting a decoding result of a word line address of a redundant memory cell when the redundancy protection enable is turned on and the memory array is in an erase step, and the configuration word line processing module is capable of outputting a decoding result of a word line address of a corresponding remaining configuration memory cell when the redundancy protection enable is turned on and the memory array is in an erase step.
In some preferred embodiments, the redundant word line processing module includes:
and the protection detection module is used for detecting whether the redundant protection enabling is started or not.
In a specific application, the redundant word line processing module and the configuration word line processing module only establish a corresponding mapping relation when the redundant protection enabling is started, so that whether the redundant protection enabling is started or not can be detected based on a protection detection module in the redundant word line processing module. When the memory array is in an erasing step, the protection detection module detects that the redundancy protection is enabled to be started, and the redundancy word line decoder 300 decodes successfully, the redundancy word line processing module does not output a decoding result of the word line address of the corresponding redundancy memory cell; when the memory array is in the erasing step, the protection detection module detects that the redundancy protection is enabled, and the second word line decoder 200 or the redundancy word line decoder 300 decodes successfully, the configuration word line processing module outputs the decoding result of the word line address of the remaining configuration memory cells correspondingly. When the protection detection module detects that the redundancy protection is enabled to be turned off and the redundancy word line decoder 300 decodes successfully, the redundancy word line processing module outputs a decoding result of the word line address of the corresponding redundancy memory cell, and the configuration word line processing module does not output a decoding result of the word line address of the corresponding remaining configuration memory cell; when the protection detection module detects that the redundancy protection is enabled and the second word line decoder 200 decodes successfully, the configuration word line processing module outputs the decoding result of the word line address of the corresponding remaining configuration memory cell.
More specifically, the protection detection module can be used to detect whether the redundant protection enable is turned on, and to determine whether a mapping relationship between the word line address of the redundant memory cell and the word line address of the remaining configuration memory cell needs to be established.
In some preferred embodiments, the redundant word line processing module further comprises:
and the stage detection module is used for detecting whether the small-capacity storage array is in an erasing stage.
In particular, the erase phase refers to the phase of the erase operation performed on the small-capacity storage array in the erase step. When the memory array is in the erasing step, the protection detection module detects that the redundancy protection is enabled to be turned off, the stage detection module detects that the memory array is in the erasing stage, and the redundancy word line decoder 300 decodes successfully, the redundancy word line processing module outputs the decoding result of the word line address of the corresponding redundancy memory cell.
More specifically, the phase detection module can be used to detect whether the capacity storage array is in an erase phase and to determine whether the redundant word line processing module needs to output the decoding result of the word line address of the redundant memory cell.
In some preferred embodiments, the redundant word line processing module includes:
The first nor gate 411, an input terminal of the first nor gate 411 is connected to the erase phase enable signal;
the input end of the first NOT gate 412 is connected with a redundancy protection enabling signal;
the first and gate 413, two input ends of the first and gate 413 are respectively connected with the output end of the first not gate 412 and the erasing step enabling signal;
the two input ends of the second nor gate 414 are respectively connected with the output end of the first nor gate 411 and the output end of the first and gate 413, and the output end of the second nor gate 414 is connected with the word line address of the redundant memory cell;
an output of a redundant word line decoder 300 is coupled to the other input of the first nor gate 411.
In particular applications, the erase step enable signal is used to indicate whether the memory array is in an erase step, e.g., the erase step enable signal is cmd_sector_erase, and when cmd_sector_erase is 1, it indicates that the memory array is in an erase step; when cmd_sector_erase is 0, this indicates that the memory array is in a step other than the erase step.
More specifically, the Erase phase enable signal is used to indicate whether the memory array is in the Erase phase of the Erase step, for example, the Erase phase enable signal is erase_en, and when erase_en is 1, it indicates that the memory array is in the Erase phase of the Erase step; when erase_en is 0, it indicates that the memory array is in a phase other than the Erase phase of the Erase step or in a step other than the Erase step.
More specifically, the redundancy protection enable signal is used to indicate whether the redundancy information is erased together with the configuration information in the Erase stage, for example, the redundancy protection enable signal is erase_reduce_en, and when the erase_reduce_en is 1, it indicates that the redundancy information is erased together with the configuration information in the Erase stage; when erase_reduce_en is 0, it indicates that the redundant information is not erased together with the configuration information in the Erase phase. The redundancy protection enable on state is Erase_reduce_en 0, and the redundancy protection enable off state is Erase_reduce_en 1.
More specifically, when erase_reduce_en is 0 and cmd_sector_erase is 1, the output of the first nor gate 412 is 1, the output of the first and gate 413 is also 1, and the output of the second nor gate 414 is necessarily 0, so that the decoding result of the word line address of the redundant memory cell is not output; when erase_reduce_en is 0, cmd_sector_erase is 0, and the decoding of the redundant word line decoder 300 is successful, the output result of the first not gate 412 is 1, the output result of the first and gate 413 is 0, the output result of the first nor gate 411 is 0, and the result of the second nor gate 414 is 1, thereby outputting the decoding result of the word line address of the redundant memory cell; therefore, the decoding circuit of the embodiment of the application can output or not output the decoding result of the word line address of the redundant memory cell according to the redundancy protection enable signal and the erasure step enable signal.
More specifically, when the erase_reduce_en is 1, the erase_en is 1, and the decoding of the redundant word line decoder 300 is successful, the output result of the first not gate 412 is 0, the output result of the first and gate 413 is 0, the output result of the first nor gate 411 is 0, and the result of the second nor gate 414 is 1, thereby outputting the decoding result of the word line address of the redundant memory cell; therefore, the decoding circuit of the embodiment of the application can output or not output the decoding result of the word line address of the redundant memory cell according to the redundancy protection enable signal and the erasure phase enable signal.
More specifically, the redundant word line processing module sets the first nor gate 411, the first nor gate 412, the first and gate 413, and the second nor gate 414 to establish processing logic for the word line address of the redundant memory cell, while acquiring the erase step enable signal with the first and gate 413, the redundancy protection enable signal with the first nor gate 412, and the erase phase enable signal with the first nor gate 411, so that the decoding circuit of the present application can output or not output the decoding result of the word line address of the redundant memory cell according to the erase phase enable signal, the redundancy protection enable signal, and the erase phase enable signal.
In some preferred embodiments, configuring the wordline processing module comprises:
The second and gate 511, one input end of the second and gate 511 is connected with a redundant erasing inversion signal, and the redundant erasing inversion signal is an output signal of the first and gate 413;
the first or gate 512, an input end of the first or gate 512 is connected to an output end of the second or gate 511, and an output end of the first or gate 512 is connected to a word line address of the remaining configuration memory cells;
an output terminal of a second word line decoder 200 is connected to the other input terminal of the first or gate 512;
an output of a redundant word line decoder 300 is coupled to the other input of the second AND gate 511.
In a specific application, the redundancy erasure inverted signal is an output signal of the first and gate 413, and is used for judging whether the two situations of the memory array in an erasure step and the redundancy protection enabling opening are satisfied at the same time, for example, the redundancy erasure inverted signal is redujerase, and when redujerase is 1, it indicates that the memory array is in the erasure step and the redundancy protection enabling opening; when Redun_erase is 0, it indicates that the memory array is in a step other than the erase step or the redundancy protection enable is turned off or both.
More specifically, when the redundant word line decoder 300 is successfully decoded and the reduce_erase is 1, the output result of the second and gate 511 is 1, and the output result of the first or gate 512 is also 1, thereby outputting the decoding result of the word line address of the corresponding remaining configuration memory cell; when the decoding of the second word line decoder 200 is successful, the output result of the first or gate 512 is 1, thereby outputting the decoding result of the corresponding word line address of the remaining configuration memory cells; when the redundant word line decoder 300 decodes successfully and the redundant word line decoder has the redundant word line decoder 0, the output result of the second and gate 511 is 0, and the output result of the first or gate 512 is also 0, so that the decoding result of the corresponding word line address of the remaining configuration memory cell is not output; therefore, the decoding circuit of the embodiment of the application can output or not output the decoding result of the corresponding word line address of the residual configuration memory cell according to the redundant erasure inversion signal.
More specifically, the configuration word line processing module sets the second and gate 511 and the first or gate 512, establishes processing logic for the word line addresses of the remaining configuration memory cells, and acquires the redundancy erasure inversion signal using the second and gate 511 at the same time, so that the decoding circuit of the present application can establish or cancel the mapping relationship of the word line addresses of the redundancy memory cells and the word line addresses of the remaining configuration memory cells according to the redundancy erasure inversion signal.
In some preferred embodiments, the redundant word line processing module includes:
a second NOT gate 421;
the two input ends of the third nor gate 422 are respectively connected with the output end of the second nor gate 421 and the erasing step enabling signal, and the output end of the third nor gate 422 is connected with the word line address of the redundant memory cell;
an output of a redundant word line decoder 300 is coupled to an input of a second NOT gate 421.
In a specific application, when it is determined that the redundancy information placed in the redundancy memory cell needs to be protected from being erased in the erasing step, the logic circuit of the redundancy word line processing module may be simplified to be composed of only the second nor gate 421 and the third nor gate 422.
More specifically, when cmd_sector_erase is 1 and the decoding of the redundant word line decoder 300 is successful, the output result of the third nor gate 422 must be 0 so that the decoding result of the word line address of the redundant memory cell is not output; when cmd_sector_erase is 0 and the decoding of the redundant word line decoder 300 is successful, the output result of the second not gate 421 is 0 and the result of the third nor gate 422 is 1, thereby outputting the decoding result of the word line address of the redundant memory cell; therefore, the decoding circuit of the embodiment of the application can output or not output the decoding result of the word line address of the redundant memory cell according to the erasing stage enabling signal.
More specifically, the redundant word line processing module sets the second nor gate 421 and the third nor gate 422, establishes processing logic for the word line address of the redundant memory cell, and simultaneously acquires the erase step enable signal using the third nor gate 422, so that the decoding circuit of the present application can output or not output the decoding result of the word line address of the redundant memory cell according to the erase step enable signal.
In some preferred embodiments, configuring the wordline processing module comprises:
the third AND gate 521, an input terminal of the third AND gate 521 is connected to the erasing step enabling signal;
the second or gate 522, one input end of the second or gate 522 is connected to the output end of the third and gate 521, and the output end thereof is connected to the word line address of the remaining configuration memory cells;
an output terminal of a second word line decoder 200 is connected to the other input terminal of the second or gate 522;
an output of a redundant word line decoder 300 is connected to the other input of the third AND gate 521.
In a specific application, when cmd_sector_erase is 1 and the redundant word line decoder 300 decodes successfully, the output of the third and gate 521 is 1, and the output of the second or gate 522 is also 1, so as to output the decoding result of the word line address of the corresponding remaining configuration memory cell; when the decoding of the second word line decoder 200 is successful, the second or gate 522 outputs 1, thereby outputting a decoding result of the corresponding word line address of the remaining configuration memory cells; when cmd_sector_erase is 0 and the decoding of the redundant word line decoder 300 is successful, the output of the third and gate 521 is 0 and the output of the second or gate 522 is also 0, so that the decoding result of the corresponding word line address of the remaining configuration memory cells is not output; therefore, the decoding circuit of the embodiment of the application can output or not output the decoding result of the corresponding word line address of the residual configuration memory cell according to the erasing stage enabling signal.
More specifically, the configuration word line processing module sets the third and gate 521 and the second or gate 522, establishes processing logic for the word line addresses of the remaining configuration memory cells, and simultaneously acquires the erase step enable signal using the third and gate 521, so that the decoding circuit of the present application can establish or cancel the mapping relationship of the word line addresses of the redundant memory cells and the word line addresses of the remaining configuration memory cells according to the erase step enable signal.
Example 1
When decoding a 16 x 32bits (64 bytes) memory array, the memory array has 16 word lines, so a 4 bit word line address needs to be set, wherein WL <0> -WL <11> place configuration information and WL <12> -WL <15> place redundancy information.
In the operation process, the redundant information needs to be protected from being erased in the erasing step, since the number of the word line addresses of the redundant memory cells is 4, the number of the word line addresses of the rest configuration memory cells needs to be ensured to be smaller than or equal to 4, and the number of the word line addresses of the part configuration memory cells is ensured to be integral multiple of 4, so that the number of the word line addresses of the rest configuration memory cells can be determined to be 4, and the number of the word line addresses of the part configuration memory cells is 8, and the decoding circuit shown in fig. 2 is adopted for decoding the memory array; in fig. 2, 8 four-input and gates are used as the first word line decoder 100 for decoding word lines WL <0> -WL <7>, corresponding to the word line addresses 0000-0111; 4 four-input AND gates are employed as the second word line decoder 200 for outputting WL_pre <8> -WL_pre <11> (abbreviated as WL_pre <11:8 >); 4 four-input AND gates are employed as the redundant word line decoder 300 for outputting WL_pre <12> -WL_pre <15> (abbreviated as WL_pre <15:12 >); 4 redundant word line processing modules consisting of a second NOT gate 421 and a third NOT gate 422 are adopted for rejecting the output WL <12> -WL <15> (abbreviated as WL <15:12 >); 4 configuration word line processing modules consisting of a third AND gate 521 and a second OR gate 522 are used to output WL <8> -WL <11> (abbreviated as WL <11:8 >), where cmd_sector_erase is the erase step enable signal.
As a result of the analysis, the addresses 0000-0111 can be successfully decoded into WL <0> -WL <7>, regardless of the erase step enable signal cmd_sector_erase.
When the erase step enable signal cmd_sector_erase is 1, the address 1000-1111 decoding case and the truth table are as follows:
TABLE 1 Erasing step Enable signal cmd_sector_erase=1, address 1000-1111 decoding table
| Addr | WL_pre | WL |
| 1000 | <8> | <8> |
| 1001 | <9> | <9> |
| 1010 | <10> | <10> |
| 1011 | <11> | <11> |
| 1100 | <12> | <8> |
| 1101 | <13> | <9> |
| 1110 | <14> | <10> |
| 1111 | <15> | <11> |
TABLE 2 truth table for addresses 1000-1111 with erasure step Enable signal cmd_sector_erase=1
| Addr | WL_pre<11:8> | WL<11:8> | WL_pre<15:12> | WL<15:12> |
| 1000 | 1 | 1 | / | / |
| 1001 | 1 | 1 | / | / |
| 1010 | 1 | 1 | / | / |
| 1011 | 1 | 1 | / | / |
| 1100 | / | 1 | 1 | 0 |
| 1101 | / | 1 | 1 | 0 |
| 1110 | / | 1 | 1 | 0 |
| 1111 | / | 1 | 1 | 0 |
Where Addr is a word line address, when the erase step enable signal cmd_sector_erase is 1, the word line wl_pre <12> -wl_pre <15> outputted by the redundant word line decoder 300 is rejected as WL <12> -WL <15>, and mapped as the word line WL <8> -WL <11>.
Therefore, as can be seen from the above table, when the memory array is in the erasing step, the word line decoding result corresponding to the word line address of the redundant memory cell can be mapped onto the word line decoding result corresponding to the word line address of the configuration memory cell, thereby protecting the redundant information from being erased.
When the erase step enable signal cmd_sector_erase is 0, the address 1000-1111 decoding case and the truth table are as follows:
TABLE 3 Erasing step Enable signal cmd_sector_erase=0, address 1000-1111 decoding table
| Addr | WL_pre | WL |
| 1000 | <8> | <8> |
| 1001 | <9> | <9> |
| 1010 | <10> | <10> |
| 1011 | <11> | <11> |
| 1100 | <12> | <12> |
| 1101 | <13> | <13> |
| 1110 | <14> | <14> |
| 1111 | <15> | <15> |
TABLE 4 Enable to erase step signal cmd_sector_erase=0, address 1000-1111 truth table
| Addr | WL_pre<11:8> | WL<11:8> | WL_pre<15:12> | WL<15:12> |
| 1000 | 1 | 1 | / | / |
| 1001 | 1 | 1 | / | / |
| 1010 | 1 | 1 | / | / |
| 1011 | 1 | 1 | / | / |
| 1100 | / | 0 | 1 | 1 |
| 1101 | / | 0 | 1 | 1 |
| 1110 | / | 0 | 1 | 1 |
| 1111 | / | 0 | 1 | 1 |
Wherein, when the erase step enable signal cmd_sector_erase is 0, the word lines wl_pre <8> -wl_pre <15> outputted from the second word line decoder 200 and the redundant word line decoder 300 are kept outputted as WL <8> -WL <15>.
Thus, as can be seen from the above table, when the memory array is in a step other than the erasing step, the mapping relationship between the word line addresses of the redundant memory cells and the word line addresses of the configuration memory cells is canceled.
Example 2
When decoding a 16 x 32bits (64 bytes) memory array, the memory array has 16 word lines, so a 4 bit word line address needs to be set, wherein WL <0> -WL <11> place configuration information and WL <12> -WL <15> place redundancy information.
In the operation process, whether the redundant information is protected from being erased is determined according to the redundant protection enabling signal in the erasing step, because the number of the word line addresses of the redundant memory cells is 4, the number of the word line addresses of the rest configuration memory cells is less than or equal to 4, and the number of the word line addresses of the part configuration memory cells is ensured to be integral multiple of 4, the number of the word line addresses of the rest configuration memory cells can be determined to be 4, and the number of the word line addresses of the part configuration memory cells is 8, and the decoding circuit shown in fig. 3 is adopted for decoding the memory array; in fig. 3, 8 four-input and gates are used as the first word line decoder 100 for decoding word lines WL <0> -WL <7>, corresponding to the word line addresses 0000-0111; 4 four-input AND gates are employed as the second word line decoder 200 for outputting WL_pre <8> -WL_pre <11> (abbreviated as WL_pre <11:8 >); 4 four-input AND gates are employed as the redundant word line decoder 300 for outputting WL_pre <12> -WL_pre <15> (abbreviated as WL_pre <15:12 >); 4 redundant word line processing modules consisting of a first NOR gate 411, a first NOR gate 412, a first AND gate 413 and a second NOR gate 414 are adopted for rejecting the output WL <12> -WL <15> (the integration is abbreviated as WL <15:12 >); 4 configuration word line processing modules composed of a second AND gate 511 and a first OR gate 512 are used to output WL <8> -WL <11> (WL <11:8> (abbreviated in the integration), wherein Erase_reduce_en is a redundancy protection enable signal, cmd_sector_erase is an erasure step enable signal, erase_en is an erasure phase enable signal (Era in the following tables), and Redun_erase is a redundancy erasure inversion signal.
As a result of analysis, the addresses 0000-0111 can be successfully decoded into WL <0> -WL <7>, regardless of the redundancy protection enable signal Erase_reduce_en, the erasure step enable signal cmd_sector_erase, and the erasure step enable signal Erase_en.
When the redundancy protection enable signal Erase_reduce_en is 0 and the Erase step enable signal cmd_sector_erase is 1, then the redundancy Erase inversion signal address Redur_erase is 1, the 1000-1111 decoding condition and the truth table are as follows:
table 5 address 1000-1111 decoding table when redundancy protection enable signal erase_reduce_en=0 and Erase step enable signal cmd_sector_erase=1
| Addr | WL_pre | WL |
| 1000 | <8> | <8> |
| 1001 | <9> | <9> |
| 1010 | <10> | <10> |
| 1011 | <11> | <11> |
| 1100 | <12> | <8> |
| 1101 | <13> | <9> |
| 1110 | <14> | <10> |
| 1111 | <15> | <11> |
TABLE 6 redundancy protection Enable signal Erase_reduce_en=0 and Erase step Enable signal cmd_sector_erase=1, addresses 1000-1111 truth table
| Addr | Era | WL_pre<11:8> | WL<11:8> | WL_pre<15:12> | WL<15:12> |
| 1000 | 1 | 1 | 1 | / | / |
| 1001 | 1 | 1 | 1 | / | / |
| 1010 | 1 | 1 | 1 | / | / |
| 1011 | 1 | 1 | 1 | / | / |
| 1100 | 1 | / | 1 | 1 | 0 |
| 1101 | 1 | / | 1 | 1 | 0 |
| 1110 | 1 | / | 1 | 1 | 0 |
| 1111 | 1 | / | 1 | 1 | 0 |
| 1000 | 0 | 1 | 1 | / | / |
| 1001 | 0 | 1 | 1 | / | / |
| 1010 | 0 | 1 | 1 | / | / |
| 1011 | 0 | 1 | 1 | / | / |
| 1100 | 0 | / | 1 | 1 | 0 |
| 1101 | 0 | / | 1 | 1 | 0 |
| 1110 | 0 | / | 1 | 1 | 0 |
| 1111 | 0 | / | 1 | 1 | 0 |
Where Addr is a word line address, when the redundancy protection enable signal Erase_reduce_en is 0 and the Erase step enable signal cmd_sector_erase is 1, the word line WL_pre <12> -WL_pre <15> output by the redundancy word line decoder 300 is rejected as WL <12> -WL <15>, and mapped as WL <8> -WL <11>.
Therefore, as can be seen from the above table, when the redundancy protection enable is turned on and the memory array is in the erasing step, the word line decoding result corresponding to the word line address of the redundancy memory cell can be mapped onto the word line decoding result corresponding to the word line address of the configuration memory cell, thereby protecting the redundancy information from being erased.
When the redundancy protection enable signal Erase_reduce_en is 0 and the Erase step enable signal cmd_sector_erase is 0, then the redundancy Erase inversion signal address Redur_erase is 0, the address 1000-1111 decoding condition and the truth table are as follows:
table 7 address 1000-1111 decoding table when redundancy protection enable signal erase_reduce_en=0 and Erase step enable signal cmd_sector_erase=0
| Addr | WL_pre | WL |
| 1000 | <8> | <8> |
| 1001 | <9> | <9> |
| 1010 | <10> | <10> |
| 1011 | <11> | <11> |
| 1100 | <12> | <12> |
| 1101 | <13> | <13> |
| 1110 | <14> | <14> |
| 1111 | <15> | <15> |
Table 8 truth table for addresses 1000-1111 when redundancy protection enable signal Erase_reduce_en=0 and Erase step enable signal cmd_sector_erase=0
| Addr | Era | WL_pre<11:8> | WL<11:8> | WL_pre<15:12> | WL<15:12> |
| 1000 | 0 | 1 | 1 | / | / |
| 1001 | 0 | 1 | 1 | / | / |
| 1010 | 0 | 1 | 1 | / | / |
| 1011 | 0 | 1 | 1 | / | / |
| 1100 | 0 | / | 0 | 1 | 1 |
| 1101 | 0 | / | 0 | 1 | 1 |
| 1110 | 0 | / | 0 | 1 | 1 |
| 1111 | 0 | / | 0 | 1 | 1 |
Wherein, when the redundancy protection enable signal erase_reduce_en=0 and the Erase step enable signal cmd_sector_erase is 0, the word lines wl_pre <8> -wl_pre <15> outputted from the second word line decoder 200 and the redundancy word line decoder 300 are kept outputted as WL <8> -WL <15>.
Thus, as can be seen from the above table, when the redundancy protection enable is turned on and the memory array is in a step other than the erasing step, the mapping relationship of the word line address of the redundant memory cell and the word line address of the configuration memory cell is canceled.
When the redundancy protection enable signal Erase_reduce_en is 1, then the redundancy erasure inversion signal address Redun_erase is 0, the 1000-1111 decoding case and truth table are as follows:
table 9 address 1000-1111 decoding table when redundancy protection enable signal erase_reduce_en=1
| Addr | WL_pre | WL |
| 1000 | <8> | <8> |
| 1001 | <9> | <9> |
| 1010 | <10> | <10> |
| 1011 | <11> | <11> |
| 1100 | <12> | <12> |
| 1101 | <13> | <13> |
| 1110 | <14> | <14> |
| 1111 | <15> | <15> |
Table 10 truth table for addresses 1000-1111 when redundancy protection enable signal Erase_reduce_en=1
| Addr | Cmd | Era | WL_pre<11:8> | WL<11:8> | WL_pre<15:12> | WL<15:12> |
| 1000 | 1 | 1 | 1 | 1 | / | / |
| 1001 | 1 | 1 | 1 | 1 | / | / |
| 1010 | 1 | 1 | 1 | 1 | / | / |
| 1011 | 1 | 1 | 1 | 1 | / | / |
| 1100 | 1 | 1 | / | 0 | 1 | 1 |
| 1101 | 1 | 1 | / | 0 | 1 | 1 |
| 1110 | 1 | 1 | / | 0 | 1 | 1 |
| 1111 | 1 | 1 | / | 0 | 1 | 1 |
| 1000 | 1 | 0 | 1 | 1 | / | / |
| 1001 | 1 | 0 | 1 | 1 | / | / |
| 1010 | 1 | 0 | 1 | 1 | / | / |
| 1011 | 1 | 0 | 1 | 1 | / | / |
| 1100 | 1 | 0 | / | 0 | 1 | 1 |
| 1101 | 1 | 0 | / | 0 | 1 | 1 |
| 1110 | 1 | 0 | / | 0 | 1 | 1 |
| 1111 | 1 | 0 | / | 0 | 1 | 1 |
| 1000 | 0 | 0 | 1 | 1 | / | / |
| 1001 | 0 | 0 | 1 | 1 | / | / |
| 1010 | 0 | 0 | 1 | 1 | / | / |
| 1011 | 0 | 0 | 1 | 1 | / | / |
| 1100 | 0 | 0 | / | 0 | 1 | 1 |
| 1101 | 0 | 0 | / | 0 | 1 | 1 |
| 1110 | 0 | 0 | / | 0 | 1 | 1 |
| 1111 | 0 | 0 | / | 0 | 1 | 1 |
Wherein, when the redundancy protection enable signal erase_reduce_en=1, the word lines wl_pre <8> -wl_pre <15> outputted from the second word line decoder 200 and the redundancy word line decoder 300 are kept outputted as WL <8> -WL <15>.
Thus, as can be seen from the above table, when redundancy protection is turned off, the mapping relationship of the word line address of the redundant memory cell and the word line address of the configuration memory cell is canceled.
Example 3
For decoding a 9 x 32bits (36 bytes) memory array, there are 9 word lines in the memory array, so a 4 bit word line address needs to be set, where WL <0> -WL <7> place configuration information and WL <8> -WL <9> place redundancy information.
In the operation process, the number of the word line addresses of the rest configuration memory cells can be determined to be 1, and the word line addresses of all the redundant memory cells and the word line addresses of the rest configuration memory cells are in a mapping relation, so that the logic of a mapping circuit is simplified, and since the WL <8> -WL <9> is used for placing redundant information, whether the word line addresses are used for placing redundant information or placing configuration information can be judged directly through the leftmost bit level, a decoding circuit shown in fig. 4 is adopted for decoding the memory array; wherein, 7 four-input AND gates are adopted as the first word line decoder 100 in FIG. 4 for decoding word lines WL <0> -WL <6>, corresponding to word line addresses 0000-0110; 1 four-input AND gate is employed as the second word line decoder 200 for outputting WL_pre <7>; since the middle two-bit level of the word line address of the redundant memory cell is 0 in the present embodiment, it is omitted in the AND gate, so that 2 two-input AND gates are employed as the redundant word line decoder 300 for outputting WL_pre <8> -WL_pre <9> (abbreviated as WL_pre <9:8 >); employing 2 redundant word line processing modules consisting of a first nor gate 411, a first nor gate 412, a first and gate 413 and a second nor gate 414 for rejecting WL <8> -WL <9> (abbreviated as WL <9:8 >); 1 configuration word line processing module composed of a second and gate 511 and a first or gate 512 is used to output WL <7>, wherein an input terminal of the second and gate 511 is used to obtain the leftmost bit level, erase_reduce_en is a redundancy protection enable signal, cmd_sector_erase is an erasure step enable signal, erase_en is an erasure phase enable signal (abbreviated as Era in the following tables), and reduce_erase is a redundancy erasure inversion signal.
As a result of analysis, the addresses 0000-0110 can be successfully decoded into WL <0> -WL <6>, regardless of the redundancy protection enable signal Erase_reduce_en, the erasure step enable signal cmd_sector_erase, and the erasure step enable signal Erase_en.
When the redundancy protection enable signal Erase_reduce_en is 0 and the Erase step enable signal cmd_sector_erase is 1, then the redundancy Erase inversion signal address Redur_erase is 1, the decoding conditions and truth table for 0111-1001 are as follows:
table 11 addresses 0111-1001 decode tables when redundancy protection enable signal erase_reduce_en=0 and Erase step enable signal cmd_sector_erase=1
| Addr | WL_pre | WL |
| 0111 | <7> | <7> |
| 1000 | <8> | <7> |
| 1001 | <9> | <7> |
Table 12 truth table for addresses 0111-1001 when redundancy protection enable signal Erase_reduce_en=0 and Erase step enable signal cmd_sector_erase=1
| Addr | Era | WL_pre<7> | WL<7> | WL_pre<9:8> | WL<9:8> |
| 0111 | 1 | 1 | 1 | / | / |
| 1000 | 1 | / | 1 | 1 | 0 |
| 1001 | 1 | / | 1 | 1 | 0 |
| 0111 | 0 | 1 | 1 | / | / |
| 1000 | 0 | / | 1 | 1 | 0 |
| 1001 | 0 | / | 1 | 1 | 0 |
Where Addr is a word line address, when the redundancy protection enable signal Erase_reduce_en is 0 and the Erase step enable signal cmd_sector_erase is 1, the word line WL_pre <8> -WL_pre <9> output by the redundancy word line decoder 300 is rejected as WL <8> -WL <9> and mapped as WL <7>.
Therefore, as can be seen from the above table, when the redundancy protection enable is turned on and the memory array is in the erasing step, the word line decoding result corresponding to the word line address of the redundancy memory cell can be mapped onto the word line decoding result corresponding to the word line address of the configuration memory cell, thereby protecting the redundancy information from being erased.
When the redundancy protection enable signal Erase_reduce_en is 0 and the Erase step enable signal cmd_sector_erase is 0, then the redundancy Erase inversion signal address Redur_erase is 0, the decoding cases and truth table for addresses 0111-1001 are as follows:
table 13 addresses 0111-1001 decode tables when redundancy protection enable signal erase_reduce_en=0 and Erase step enable signal cmd_sector_erase=0
| Addr | WL_pre | WL |
| 0111 | <7> | <7> |
| 1000 | <8> | <8> |
| 1001 | <9> | <9> |
Table 14 truth table for addresses 0111-1001 when redundancy protection enable signal Erase_reduce_en=0 and Erase step enable signal cmd_sector_erase=0
| Addr | Era | WL_pre<7> | WL<7> | WL_pre<9:8> | WL<9:8> |
| 1000 | 0 | 1 | 1 | / | / |
| 1001 | 0 | / | 0 | 1 | 1 |
| 1010 | 0 | / | 0 | 1 | 1 |
Wherein, when the redundancy protection enable signal erase_reduce_en=0 and the Erase step enable signal cmd_sector_erase is 0, the word lines wl_pre <7> -wl_pre <9> outputted from the second word line decoder 200 and the redundancy word line decoder 300 are kept outputted as WL <7> -WL <9>.
Thus, as can be seen from the above table, when the redundancy protection enable is turned on and the memory array is in a step other than the erasing step, the mapping relationship of the word line address of the redundant memory cell and the word line address of the configuration memory cell is canceled.
When the redundancy protection enable signal Erase_reduce_en is 1, then the redundancy erasure inversion signal address Redun_erase is 0, the decoding cases and truth tables of 0111-1001 are as follows:
table 15 redundancy protection enable signal erase_reduce_en=1, addresses 0111-1001 decode table
| Addr | WL_pre | WL |
| 0111 | <7> | <7> |
| 1000 | <8> | <8> |
| 1001 | <9> | <9> |
Table 16 truth table for addresses 0111-1001 when redundancy protection enable signal Erase_reduce_en=1
| Addr | Cmd | Era | WL_pre<7> | WL<7> | WL_pre<9:8> | WL<9:8> |
| 0111 | 1 | 1 | 1 | 1 | / | / |
| 1000 | 1 | 1 | / | 0 | 1 | 1 |
| 1001 | 1 | 1 | / | 0 | 1 | 1 |
| 0111 | 1 | 0 | 1 | 1 | / | / |
| 1000 | 1 | 0 | / | 0 | 1 | 1 |
| 1001 | 1 | 0 | / | 0 | 1 | 1 |
| 0111 | 0 | 0 | 1 | 1 | / | / |
| 1000 | 0 | 0 | / | 0 | 1 | 1 |
| 1001 | 0 | 0 | / | 0 | 1 | 1 |
Wherein, when the redundancy protection enable signal erase_reduce_en=1, the word lines wl_pre <7> -wl_pre <9> outputted from the second word line decoder 200 and the redundancy word line decoder 300 are kept outputted as WL <7> -WL <9>.
Thus, as can be seen from the above table, when redundancy protection is turned off, the mapping relationship of the word line address of the redundant memory cell and the word line address of the configuration memory cell is canceled.
In summary, the embodiments of the present application provide an erasing method and a decoding circuit for a small capacity memory array, where the erasing method establishes a mapping relationship between a word line address of a redundant memory cell and a word line address of a configuration memory cell, so that when the small capacity memory array is erased and an address is addressed to the redundant memory cell, the word line address of the redundant memory cell is not selected in logic processing, thereby protecting redundant information from being erased.
In the embodiments provided herein, it should be understood that the disclosed circuits and methods may be implemented in other ways. The above-described circuit embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, circuit or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (2)
1. A decoding circuit for a small capacity memory array for word line decoding of memory cells, the small capacity memory array for storing configuration information and redundancy information, the decoding circuit comprising:
a plurality of first word line decoders (100) for decoding word line addresses of the partial configuration memory cells, the output ends of the first word line decoders (100) being connected to the word line addresses of the partial configuration memory cells;
a plurality of mapping circuits;
the first word line decoder (100) and the mapping circuit are both connected to the same address line for word line decoding;
the mapping circuit includes:
a second word line decoder (200) for decoding word line addresses of the remaining configuration memory cells;
a redundant word line decoder (300) for decoding word line addresses of redundant memory cells;
a first mapper for mapping the word line address of the redundant memory cell to the word line address of the remaining configuration memory cell when a redundancy protection enable is turned on;
the first mapper comprises:
a redundant word line processing module for processing word line addresses of the redundant memory cells;
a configuration word line processing module for processing word line addresses of the remaining configuration memory cells;
The redundant word line processing module includes:
a first nor gate (411), wherein an input end of the first nor gate (411) is connected with an erasing stage enabling signal;
the input end of the first NOT gate (412) is connected with a redundancy protection enabling signal;
the first AND gate (413), two input ends of the first AND gate (413) are respectively connected with the output end of the first NOT gate (412) and the erasing step enabling signal;
the two input ends of the second NOR gate (414) are respectively connected with the output end of the first NOR gate (411) and the output end of the first AND gate (413), and the output ends of the second NOR gate are connected with the word line address of the redundant memory cell;
an output of the redundant word line decoder (300) is connected to the other input of the first nor gate (411).
2. The decoding circuit of claim 1, wherein the configuration word line processing module comprises:
the second AND gate (511), an input end of the second AND gate (511) is connected with a redundant erasing inversion signal, and the redundant erasing inversion signal is an output signal of the first AND gate (413);
a first or gate (512), wherein an input end of the first or gate (512) is connected to an output end of the second or gate (511), and an output end of the first or gate is connected to a word line address of the remaining configuration memory cells;
An output of the second word line decoder (200) is connected to the other input of the first or gate (512);
an output of the redundant word line decoder (300) is connected to the other input of the second AND gate (511).
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