CN1416139A - Nonvolatile semiconductor memory having backup memory block - Google Patents
Nonvolatile semiconductor memory having backup memory block Download PDFInfo
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- CN1416139A CN1416139A CN02141133A CN02141133A CN1416139A CN 1416139 A CN1416139 A CN 1416139A CN 02141133 A CN02141133 A CN 02141133A CN 02141133 A CN02141133 A CN 02141133A CN 1416139 A CN1416139 A CN 1416139A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
Abstract
Defect information about a defective memory block is stored into a large capacity memory block having a low rewrite frequency and a block select circuit is provided that selects a backup memory block when the stored defect information is referred and the defective memory block is selected.
Description
(1) technical field
The present invention relates to nonvolatile semiconductor memory, particularly relate to bad the remedying of flash (flash) storer.
(2) background technology
In recent years, more and more noticeable as the flash memory of nonvolatile semiconductor memory.This flash memory has following advantage: it is a nonvolatile memory, but can rewrite, and in addition, because its component structure is simple, can reduce its chip area so compare with DRAM (dynamic RAM), improves integrated level etc. easily.In addition, because flash memory is nonvolatile memory, so do not need the work that refreshes of battery backup etc.Thereby, also can reduce power consumption.In addition, because chip area is little,, can make at an easy rate so be easy to a large amount of productions.
Data in the flash memory are read, and are same with DRAM, can carry out with reading out of little data unit as byte or word unit.On the other hand, write, because the cause of the configuration aspects of present flash memory element, have restriction aspect the number of times rewriting, so in general, make and be decided to be block unit to cut down the structure of rewriting number of times rewriting unit about data.
Figure 10 is the memory block layout that each memory block is carried out address assignment in general flash memory.
At this,, respectively each memory block is distributed between the 000000～FFFFFF of address as an example.
But for example the zone of the information of the management data file as the boot section is compared with other zone, and it is more that it rewrites number of times.At this, if will starting the memory block M1 of address, supposition distributes to the boot section, then only in memory block M1, cause rewriting continually, this zone is compared with other zone, the rewriting number of times of flash memory surpasses limits value quickly, under the situation that has surpassed the limits value of rewriting number of times, element function takes place to worsen to wait and causes unfavorable condition, can not carry out correctly sometimes that data are read or data write.Thereby, become unacceptable product the whole out of use problem of nonvolatile semiconductor memory takes place owing to just rewriting the high specific memory device piece of frequency.
(3) summary of the invention
The objective of the invention is to solve that above-mentioned problem prolongs with the flash memory is the life-span of the nonvolatile semiconductor memory of representative.
Nonvolatile semiconductor memory of the present invention possesses: memory array, comprise a plurality of the 1st memory blocks, the 2nd memory block and redundant memory blocks, wherein, the 1st memory block comprises the high storage unit of rewriting frequency of data, the 2nd memory block comprises the low storage unit of rewriting frequency of data, and redundant memory blocks is used for replacing the bad memory block in a plurality of the 1st memory blocks; Control circuit, be used for writing to judge whether produced each a plurality of the 1st memory block bad that writes object as data when handling in data for each a plurality of the 1st memory block, simultaneously detecting under the condition of poor flame that the bad memory block of storage representation is used in the 1st zone of the 2nd memory block; And the selection circuit, be used for selection information according to the selection usefulness of the flame of in the 1st zone of the 2nd memory block, having stored and each a plurality of the 1st memory block of expression, follow the selection of bad memory block to select redundant memory blocks.Thereby, main advantage of the present invention is, the flame of a plurality of the 1st memory blocks of storage in the 2nd memory block, according to the selection information of this flame of having stored with the selection usefulness of each a plurality of the 1st memory block of expression, select redundant memory blocks by the selection of following bad memory block, particularly get final product, so can prolong the life-span of nonvolatile semiconductor memory simply owing to only remedying the high bad memory block of data rewriting frequency.
Comparatively it is desirable to, the 2nd memory block also has the 2nd zone, the 2nd zone has the releasing of following reset mode and the information that becomes the object of access, control circuit is after reset mode has been disengaged, according to the indicator signal of importing from the outside with the access in the 2nd zone, read out in the flame of having stored in the 1st zone of the 2nd memory block, again flame is exported to the selection circuit.In addition, another advantage of the present invention is, because control circuit is after reset mode is removed, according to the working signal from the outside, read flame and export to the selection circuit from the 2nd memory block, so can only utilize the sequential adjustment of working instruction signal to control simply.
Comparatively it is desirable to, also possesses decision circuit, decision circuit is used for according to the flame of having stored in the 1st zone of the 2nd memory block, export bad signal to selecting circuit, select circuit according to some selection signals and the bad signal selected in a plurality of the 1st memory blocks, select some in a plurality of the 1st memory blocks and the redundant memory blocks.
Particularly, decision circuit the work of control circuit stopped during in, read out in the flame of having stored in the 1st zone of the 2nd memory block, according to the flame of having read bad signal is exported to the selection circuit again, select circuit the work of control circuit stop to be disengaged after, according to the bad signal of having imported with select signal, follow the selection of bad memory block and select redundant memory blocks.In addition, another advantage of the present invention is flame can be passed to the selection circuit in during the work that has stopped control circuit, so control circuit needn't be read flame after starting working, so improved the efficient of exploitation aspect.
Comparatively it is desirable to, the data storage capacity of each a plurality of the 1st memory block is littler than the data storage capacity of the 2nd memory block.In addition, another advantage of the present invention is, because the data storage capacity of each a plurality of the 1st memory block is littler than the data storage capacity of the 2nd memory block, so can dwindle can be shared with each redundant memory blocks of replacing of a plurality of the 1st memory blocks the zone, dwindle the shared ratio of chip of memory array integral body.
Comparatively it is desirable to the data that storage unit writes and wipes in the mode of electricity with non-volatile mode stored energy.
(4) description of drawings
Fig. 1 is the circuit structure diagram of the nonvolatile semiconductor memory 100 of embodiments of the invention 1.
Fig. 2 is the memory block layout of memory array 10.
Fig. 3 is the figure that the mass storage piece L of the flame of having stored the small-capacity memory piece is shown.
Fig. 4 is the figure that the mass storage piece L of the flame that has write each small-capacity memory piece is shown.
Fig. 5 is the process flow diagram that writes processing that illustrates for the small-capacity memory piece.
Fig. 6 is the process flow diagram of circuit working that the nonvolatile semiconductor memory 100 of the bad memory block of remedying embodiments of the invention 1 is shown.
Fig. 7 A utilizes structure of the present invention backup of memory piece BC and bad memory block to be replaced and carried out the memory block layout of address assignment.
Fig. 7 B utilizes structure of the present invention backup of memory piece BC and bad memory block to be replaced and carried out another memory block layout of address assignment.
Fig. 8 is the circuit structure diagram of the nonvolatile semiconductor memory of remedying bad memory block 110 of embodiments of the invention 2.
Fig. 9 is illustrated in the process flow diagram that in the bad sign register 21 bad signal ES is carried out set.
Figure 10 is the memory block layout that each memory block is carried out address assignment in general flash memory.
Embodiment
On one side with reference to accompanying drawing, Yi Bian explain embodiments of the invention.Have again, be marked with prosign, do not repeat its explanation for part same or suitable among the figure.
(embodiment 1)
With reference to Fig. 1, nonvolatile semiconductor memory 100 possesses: memory array 10; Piece commutation circuit 14; Block selection circuit 20; Control circuit 30; Decision circuit 40; And internal bus IBS.
In general, even rewritable storer, the major part of its content has also been stored program, and the data volume that can rewrite in the work of system is less.
Thereby in the present invention, in the design phase, the few information (data, program etc.) of frequency is rewritten in storage in the zone of the mass storage piece of having been cut apart 12.In addition, the many information (data, program etc.) of frequency is rewritten in storage in the zone of the small-capacity memory piece of having been cut apart 11.
By making such structure, get final product because the small-capacity memory piece of the limits value that surpassed the number of times of rewriting remedied, so can dwindle the chip area of backup of memory piece 13, can dwindle memory array integral body.
Internal bus IBS and each internal circuit carry out giving and accepting of address information and data message etc.
With reference to Fig. 2, at this,, use the address area of address 000000～FFFFFF as an example, distributed respectively and rewritten the many small-capacity memory piece B0～B3 of frequency and rewrite the few mass storage piece L of frequency.In addition, identical by the capacity that makes backup of memory piece BC with the capacity of small-capacity memory piece, can with do not change other the address assignment of each small-capacity memory piece that is not bad as the displacement of bad small-capacity memory piece.
Referring again to Fig. 1, control circuit 30 by through internal bus IBS with reference to the address information that is dispensed on the small-capacity memory piece in the address area respectively, the processing that can write, read and wipe the small-capacity memory piece of regulation etc.Control circuit 30 will pass to block selection circuit 20 from the block selection signal BS that the address information of each small-capacity memory piece has carried out deciphering.
With reference to Fig. 3,, the some of small-capacity memory piece B0～B3 of remedying in the memory array 10 and the structure of replacing with backup of memory piece BC are described at this.At this, piece selects to determine that signal DBS0～DBS3 is respectively a signal of selecting small-capacity memory piece B0～B3, and piece selects to determine that signal DBS4 is a signal of selecting backup of memory piece BC.Above-mentioned piece selects to determine that signal DBS is the general name that piece selects to determine signal DBS0～DBS3.When piece was selected to determine that signal DBS0～DBS3 is high level, the selection of small-capacity memory piece B0～B3 had been determined in expression respectively.In addition, when piece was selected to determine that signal DBS0～DBS3 is low level, the non-selection of small-capacity memory piece B0～B3 had been determined in expression respectively.When piece was selected to determine that signal DBS4 is high level, the selection of backup of memory piece BC had been determined in expression.In addition, when piece was selected to determine that signal DBS4 is low level, the non-selection of backup of memory piece BC had been determined in expression.
Have again, there is no need to be defined in small-capacity memory piece B0～B3, also can make small-capacity memory piece or the mass storage piece structure of replacing with other.In addition,, also there is no need to be limited to 1, can make the structure that a plurality of backup of memory pieces are replaced is set even for backup of memory piece BC.
For example, the example that block selection circuit 20 is replaced small-capacity memory piece B0 and backup of memory piece BC now is described.
Block selection signal BS0～BS3 is a signal of selecting corresponding small-capacity memory piece B0～B3 respectively.Suppose that each block selection signal BS0～BS3 is a high level when the piece selection mode.On the other hand, suppose when the piece nonselection mode to be low level.Above-mentioned block selection signal BS is the general name of each block selection signal BS0～BS3.In addition, bad signal ES0～ES3 is a signal of representing the defective mode of corresponding small-capacity memory piece B0～B3 respectively.Suppose that each bad signal ES0～ES3 is a high level when defective mode.On the other hand, suppose when normal condition to be low level.The general name that above-mentioned bad signal ES is each block selection signal BS0～BS3.
At this, when small-capacity memory piece B0 was defective mode, bad signal ES0 was a high level.Under the situation of having selected piece B0, be that block selection signal is under the situation of high level because the reverse signal that is input to the bad signal in the AND circuit 55 is a low level, be low level so piece is selected definite signal DBS0.Thereby, because small-capacity memory piece B0 is a defective mode, so not selected.On the other hand, because bad signal ES0 and block selection signal BS0 are high level, so the output signal of AND circuit 51 is a high level.Thereby, select to determine that as the piece of the output signal of OR circuit 59 signal DBS4 is a high level, piece B0 and backup of memory piece BC are replaced.Under each small-capacity memory piece B1～B3 and the backup of memory piece BC situation of replacing with other, also be same, according to each the bad signal ES1～ES3 that is transfused to, whether decision replaces with backup of memory piece BC.Because for circuit working is same, so do not repeat its detailed explanation.
At this, illustrate that such as shown in Figure 4 flame with each small-capacity memory piece is written to the mode among the mass storage piece L.At this, why flame is written among the mass storage piece L, be because by being written to the problem of avoiding among the few mass storage piece L of frequency above the flash memory of the limits value of writing indegree that writes.
With reference to Fig. 5, in Fig. 5,, writing for small-capacity memory piece B0 is shown as an example.
If control circuit 30 is accepted write command, just carry out and write processing (step S0).Secondly, control circuit 30 is obtained the address information (step S1) of the small-capacity memory piece B0 that writes data through internal bus IBS.Secondly, 30 pairs of small-capacity memory pieces of control circuit B0 writes data message (step S2).Secondly, control circuit 30 judgements write whether failed (step S3).At this, do not fail if write, just finish (step S6).In step S3, be judged as under the situation that writes failure at control circuit 30, obtain the address information (step S4) of the mass storage piece L that writes flame.Secondly, control circuit 30 finishes to write processing (step S6) through internal bus IBS writes small-capacity memory piece B0 in mass storage piece L flame (step S5).
The process flow diagram of use Fig. 1 and Fig. 6 illustrates the circuit working of the nonvolatile semiconductor memory of remedying bad memory block 100 of embodiments of the invention 1.
At this, suppose and in mass storage piece L, stored flame.
At first, control circuit 30 is received in the bad input (for example, high level) (step S10) that makes the systematic reset signal SRT that entire system resets when judging back or power connection.Control circuit 30 is because such input and temporarily quit work (step S11).Secondly, decision circuit 40 is accepted the input (for example, high level) (step S12) of bad reset signal FRT.Decision circuit 40 is accepted such input and be activated (step S13).Secondly, decision circuit 40 reads out in the flame of having stored among the mass storage piece L in the memory array 10 (step S14).Secondly, the flame that decision circuit 40 will have been read is exported to the bad sign register 21 (step S15) of block selection circuit 20 as bad signal ES.Secondly, in bad sign register 21, the bad signal ES that has been transmitted is carried out set (step S16).Secondly, decision circuit 40 is accepted the input (for example, low level) (step S17) of bad reset signal FRT.Decision circuit 40 is owing to such input and by non-activation (step S18).Secondly, control circuit 30 is accepted the input (for example, low level) (step S19) of systematic reset signal SRT.Remove temporarily the stopping of control circuit 30 (step S20), generate the block selection signal BS of the selection of instruction memory piece, export to block selection circuit 20 (step S21).
Thus, block selection circuit 20 as mentioned above, according to bad signal ES that has been set in bad sign register 21 and the block selection signal BS that is transfused to, IOB selects to determine signal DBS.
Thereby when bad memory block became access object, block selection circuit 20 can be remedied this bad memory block by selecting backup of memory piece BC.In addition, utilization is in bad systematic reset signal SRT that is transfused to when judging back or power connection etc. and the input of bad reset signal FRT, entire system be reset during in, because flame is read out, bad signal ES is set in bad sign register 21, so, carried out the preparation of switching bad memory block and backup of memory piece resetting when being disengaged.
Among Fig. 7 (A), distributed the address in the mode that changes to backup of memory piece BC in response to the flame of small-capacity memory piece B0.In Fig. 7 (B), distributed the address in the mode that changes to backup of memory piece BC in response to the flame of small-capacity memory piece B1.
Utilize structure of the present invention, writing under the kaput situation for the small-capacity memory piece, in writing the few mass storage piece L of frequency, write flame, by bad memory block and backup of memory piece being replaced according to such information, remedy write the high small-capacity memory piece of frequency in, can prolong life-span of nonvolatile semiconductor memory.
In addition, because when entire system is reset, in bad sign register 21, the bad signal based on the flame of each small-capacity memory piece is carried out set, can carry out the preparation of remedying bad memory block, needn't make special program work so can improve the efficient of exploitation aspect.
(embodiment 2)
With reference to Fig. 8, nonvolatile semiconductor memory 110 is compared with nonvolatile semiconductor memory 100, bad signal ES is exported on bad sign register 21 this point different not possessing decision circuit 40 moreover control circuit 30.
In embodiment 1, illustrated the input that utilizes systematic reset signal SRT make entire system reset, before being disengaged during in bad sign register 21, bad signal ES is carried out set structure.In embodiments of the invention 2, illustrate in the input that utilizes systematic reset signal SRT and removed the structure of in bad sign register 21, bad signal ES being carried out set after the resetting of entire system.
In general, select the possibility of small-capacity memory piece little in the firm back of removing that resets of entire system.This be because, after the firm releasing that resets of entire system, the cause that the low mass storage piece of rewriting frequency of having stored program is carried out access in the ordinary course of things.Thereby after the firm releasing that resets of entire system, there is no need to make becomes bad not stored program small-capacity memory piece and backup of memory piece and replaces.
The process flow diagram of application drawing 9 illustrates the structure of in bad sign register 21 bad signal ES being carried out set.
The input (, being high level) (step S30) of the systematic reset signal SRT that imports when at first, control circuit 30 is received in bad judgement back or power connection at this.Control circuit 30 is because such input and temporarily quit work (step S31).
Secondly, the input (, being low level) (step S32) of the systematic reset signal SRT of the work usefulness of control circuit 30 acceptance beginning internal circuits at this.Control circuit 30 is accepted such inputs and is removed temporarily and stop (step S33).At this, though not shown, carry out from the CPU of the management system integral body of the outer setting of nonvolatile semiconductor memory access (step S34) the mass storage piece of having stored program information.But, suppose that these are different with the mass storage piece L that has stored flame by the mass storage piece of access.In addition, follow this access, through internal bus IBS control circuit 30 is imported bad sign register asserts signal RE (step S35) from CPU.Secondly, control circuit 30 is accepted the input of bad sign register asserts signal RE, reads flame (step S36) from mass storage piece L.Secondly, control circuit 30 is judged bad from the flame of each small-capacity memory piece of having read, bad signal ES is exported to bad sign register 21 (step S37).The bad signal ES that 21 pairs of bad sign registers have been imported carries out set (step S38).
Usually, after the releasing that resets of entire system, the mass storage piece that 30 pairs of control circuits have been stored program information carries out access.Thereby after the bad sign register asserts signal RE that control circuit 30 is transfused to accepting to follow such access, even in bad sign register 21 bad signal ES is carried out set, the possibility that becomes problem in work is also less.
In addition, when secondarily the small-capacity memory piece being carried out access,, carried out the preparation of switching backup of memory piece and bad memory block owing in bad sign register 21, bad signal ES has been carried out set.
Utilize such structure, under the situation that decision circuit 40 is not set, can obtain effect similarly to Example 1.
Claims (6)
1. nonvolatile semiconductor memory is characterized in that possessing:
Memory array (10), comprise a plurality of the 1st memory blocks (11), the 2nd memory block (12) and redundant memory blocks (13), wherein, above-mentioned the 1st memory block (11) comprises the high storage unit of rewriting frequency of data, above-mentioned the 2nd memory block (12) comprises the low storage unit of rewriting frequency of data, and above-mentioned redundant memory blocks (13) is used for replacing the bad memory block in above-mentioned a plurality of the 1st memory block;
Control circuit (30), be used for writing to judge whether produced each above-mentioned a plurality of the 1st memory block bad that writes object as data when handling in data for each above-mentioned a plurality of the 1st memory block, detecting under the condition of poor flame that the above-mentioned bad memory block of storage representation is used in the 1st zone of above-mentioned the 2nd memory block; And
Select circuit (20), be used for selection information according to the selection usefulness of the above-mentioned flame of in above-mentioned the 1st zone of above-mentioned the 2nd memory block, having stored and each above-mentioned a plurality of the 1st memory block of expression, follow the selection of above-mentioned bad memory block to select above-mentioned redundant memory blocks.
2. the nonvolatile semiconductor memory described in claim 1 is characterized in that:
Above-mentioned the 2nd memory block (12) also has the 2nd zone, and above-mentioned the 2nd zone has the releasing of following reset mode and the information that becomes the object of access,
Above-mentioned control circuit (30) is after above-mentioned reset mode has been disengaged, according to the indicator signal of importing from the outside with the access in above-mentioned the 2nd zone, read out in the above-mentioned flame of having stored in above-mentioned the 1st zone of above-mentioned the 2nd memory block, more above-mentioned flame is exported to above-mentioned selection circuit (20).
3. the nonvolatile semiconductor memory described in claim 1 is characterized in that:
Also possess decision circuit (40), above-mentioned decision circuit (40) is used for according to the above-mentioned flame of having stored above-mentioned selection circuit (20) being exported bad signal in above-mentioned the 1st zone of above-mentioned the 2nd memory block (12),
Above-mentioned selection circuit is according to some selection signals and the above-mentioned bad signal selected in above-mentioned a plurality of the 1st memory blocks (11), selects some in above-mentioned a plurality of the 1st memory block and the above-mentioned redundant memory blocks (13).
4. the nonvolatile semiconductor memory described in claim 3 is characterized in that:
Above-mentioned decision circuit the work of above-mentioned control circuit stopped during in, read out in the above-mentioned flame of having stored in above-mentioned the 1st zone of above-mentioned the 2nd memory block, according to the above-mentioned flame of having read above-mentioned bad signal is exported to above-mentioned selection circuit again
Above-mentioned selection circuit the work of above-mentioned control circuit stop to be disengaged after, according to above-mentioned bad signal of having imported and above-mentioned selection signal, follow the selection of above-mentioned bad memory block and select above-mentioned redundant memory blocks.
5. the nonvolatile semiconductor memory described in claim 1 is characterized in that:
The data storage capacity of each above-mentioned a plurality of the 1st memory block is littler than the data storage capacity of above-mentioned the 2nd memory block.
6. the nonvolatile semiconductor memory described in claim 1 is characterized in that:
The data that said memory cells writes and wipes in the mode of electricity with non-volatile mode stored energy.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP330762/2001 | 2001-10-29 | ||
| JP2001330762A JP2003132693A (en) | 2001-10-29 | 2001-10-29 | Nonvolatile semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1416139A true CN1416139A (en) | 2003-05-07 |
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ID=19146439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN02141133A Pending CN1416139A (en) | 2001-10-29 | 2002-07-05 | Nonvolatile semiconductor memory having backup memory block |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6754115B2 (en) |
| JP (1) | JP2003132693A (en) |
| KR (1) | KR100485550B1 (en) |
| CN (1) | CN1416139A (en) |
| DE (1) | DE10230132A1 (en) |
| TW (1) | TWI254940B (en) |
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| CN101499317B (en) * | 2008-02-03 | 2011-12-21 | 力晶半导体股份有限公司 | Memory device and data reading method |
| US9275742B2 (en) | 2007-04-30 | 2016-03-01 | Samsung Electronics Co., Ltd. | Memory system, program method thereof, and computing system including the same |
| CN116612801A (en) * | 2023-07-19 | 2023-08-18 | 芯天下技术股份有限公司 | Erasing method and decoding circuit of small-capacity storage array |
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| KR100463199B1 (en) * | 2002-03-04 | 2004-12-23 | 삼성전자주식회사 | Semiconductor memory device with flexible redundancy scheme |
| US6876579B2 (en) * | 2003-08-04 | 2005-04-05 | Phison Electronics Corp. | Method writing data to a large block of a flash memory cell |
| JP2006073111A (en) * | 2004-09-02 | 2006-03-16 | Fujitsu Ltd | Semiconductor memory capable of testing redundant memory cell |
| JP5014125B2 (en) * | 2005-05-30 | 2012-08-29 | スパンション エルエルシー | Semiconductor device and program data redundancy method |
| JP2010282369A (en) * | 2009-06-03 | 2010-12-16 | Toshiba Corp | Memory system |
| US20110010485A1 (en) * | 2009-07-08 | 2011-01-13 | Hou-Yuan Lin | Flash Memory Control Device |
| CN102682845B (en) * | 2012-05-09 | 2018-10-16 | 上海华虹宏力半导体制造有限公司 | EEPROM memory cell and eeprom memory |
| CN105518799B (en) | 2013-09-04 | 2018-11-02 | 东芝存储器株式会社 | Semiconductor storage |
| KR20190056862A (en) * | 2017-11-17 | 2019-05-27 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
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2001
- 2001-10-29 JP JP2001330762A patent/JP2003132693A/en active Pending
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2002
- 2002-03-20 US US10/101,317 patent/US6754115B2/en not_active Expired - Fee Related
- 2002-03-29 TW TW091106434A patent/TWI254940B/en not_active IP Right Cessation
- 2002-07-04 DE DE10230132A patent/DE10230132A1/en not_active Withdrawn
- 2002-07-05 CN CN02141133A patent/CN1416139A/en active Pending
- 2002-07-10 KR KR10-2002-0039926A patent/KR100485550B1/en not_active IP Right Cessation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9275742B2 (en) | 2007-04-30 | 2016-03-01 | Samsung Electronics Co., Ltd. | Memory system, program method thereof, and computing system including the same |
| US9460796B2 (en) | 2007-04-30 | 2016-10-04 | Samsung Electronics Co., Ltd. | Memory system, program method thereof, and computing system including the same |
| CN103632722B (en) * | 2007-04-30 | 2017-01-11 | 三星电子株式会社 | Memory system, program method thereof, and computing system including the same |
| CN101499317B (en) * | 2008-02-03 | 2011-12-21 | 力晶半导体股份有限公司 | Memory device and data reading method |
| CN116612801A (en) * | 2023-07-19 | 2023-08-18 | 芯天下技术股份有限公司 | Erasing method and decoding circuit of small-capacity storage array |
| CN116612801B (en) * | 2023-07-19 | 2023-10-13 | 芯天下技术股份有限公司 | Erasing method and decoding circuit of small-capacity storage array |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100485550B1 (en) | 2005-04-28 |
| US20030081478A1 (en) | 2003-05-01 |
| US6754115B2 (en) | 2004-06-22 |
| JP2003132693A (en) | 2003-05-09 |
| KR20030035810A (en) | 2003-05-09 |
| TWI254940B (en) | 2006-05-11 |
| DE10230132A1 (en) | 2003-05-15 |
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