JPH07312096A - Nonvolatile memory - Google Patents

Abstract

PURPOSE:To enable defective memory to be equivalent in its use to nondefective memory by allocating a defective memory block in the user memory region to the memory block in the spare memory region using a substitution table. CONSTITUTION:The substitution table 1 previously stores substitution address data or nonsubstitution address data in accordance with each memory block in the user memory region 4. It outputs substitution address data or nonsubstitution address data in accordance with input address data A8 to A15. When the substitution table 1 outputs nonsubstitution address data, a selector 2 outputs input address data A8 to A15, and when the substitution table 1 outputs substituion address data, the selector 2 outputs substitution address data. Consequently the nonvolatile memory 6 conducts data access to the memory block directed by the address data which the selector 2 outputs.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a non-volatile memory.

[0002]

2. Description of the Related Art Flash memory (EEPROM) is
As the density of memory cells has increased, a memory cell having a large memory capacity has been provided. However, the yield of memory chips is still low, and defective memory cells are often partially generated during manufacturing. Memory chip makers
Even if it contains some defective memory cells,
The current situation is to supply memory chips to users.

[0003]

Since the defective memory cells in the memory chip cannot be used, it is necessary to avoid the physical addressing of the defective memory cells.

It is an object of the present invention to provide a non-volatile memory which can use a non-volatile memory having defective memory cells as an equivalent to a non-defective non-volatile memory.

[0005]

The nonvolatile memory of the present invention is provided with input address data (A8 to A8) supplied from the outside.
15) A non-volatile memory for accessing data according to 15), a user memory area having a plurality of memory blocks capable of storing data, and a spare to be used in place of the memory block in the user memory area. A memory block array having a spare memory area having a memory block, and alternative address data indicating a memory block in the spare memory area for replacing the memory block in the user memory area according to the input address data, or A substitute table (1) that outputs one of the substitute data of the non-replacement address data indicating that the replacement of the memory block is not performed, and outputs the input address data when the substitute data output by the substitute table is the non-replacement address data. , If the alternative data is alternative address data, And a selector for outputting the address data, and accesses the memory block array in accordance with the address data selector outputs.

[0006]

In the alternative table, alternative address data or non-alternative address data is stored in advance for each memory block in the user memory area. For example, when the memory block of the corresponding user memory area is defective, the address data indicating the memory block of the spare memory area to be used in place of the memory block is registered in the alternative table as alternative address data, and the corresponding user is registered. When the memory block in the memory area is normal, non-replacement address data indicating that the memory block is used without replacement is registered in the replacement table.

The substitute table outputs substitute address data or non-replacement address data according to input address data supplied from the outside. The selector outputs the input address data when the alternative table outputs the non-alternative address data, and outputs the alternative address data when the alternative table outputs the alternative address data. In the nonvolatile memory, data access is performed to the memory block designated by the address data output from the selector.

[0008]

1 is a block diagram showing the structure of a flash memory chip according to an embodiment of the present invention.

The flash memory 6 is an EEPROM and has memory areas of a user area 4 and a spare area 5. The user area 4 is a memory area that a user can normally use. The spare area 5 is a memory area for use when a defective memory cell exists in the user area 4 instead of the memory block including the defective memory cell.

Both the user area 4 and the spare area 5 have a plurality of memory block areas. Each memory block has a memory area of 256 bytes, for example. The flash memory 6 including the user area 4 and the spare area 5 is
A physical address is designated by the address signals A0 to A7 and Y8 to Y15.

Address signals Y8 to Y15 are address signals for designating one of a plurality of memory blocks in flash memory 6, and address signals A0 to A7.
Is an address signal for designating a memory cell in a memory block.

When there is a memory block containing a defective memory cell in the user area 4, the memory block in the spare area 5 is used instead of the memory block.
That is, the memory is replaced in memory block units.

The defective memory cell in the user area 4 is found by an inspection performed at the time of manufacturing the flash memory chip. Information on the found defective memory cell is registered in the substitution table 1. The substitution table 1 is composed of, for example, a byte-rewritable EEPROM.

FIG. 2A is a schematic diagram showing a configuration example of the flash memory 6 shown in FIG. Flash memory 6
Has a user area 4 and a spare area 5. The user area 4 includes, for example, memory blocks 21, 22, 23, ...
.. and the spare area 5 has the memory block 31 ,.
・ Has

Memory block 21 in the user area 4
Is an initial physical address at address 0000h.
Here, h at the end of the address means hexadecimal notation. The memory block 22 has an address of 0100h.
Starting from the memory block 23, the address 0200
Start from h.

These addresses are 16-bit physical addresses, and the upper 8 bits are address signals Y8 to Y15.
The lower 8 bits are specified by the address signals A0 to A
Specified by 7.

Therefore, the memory block address indicated by the address signals Y8 to Y15 indicates 00h in the memory block 21 and 01h in the memory block 22.
, And the memory block 23 shows 02h.

First memory block 31 of spare area 5
Starts from address F000h, and then a plurality of memory blocks are arranged in the upper direction. As a result of the inspection of the flash memory 6, it is assumed that the memory blocks 21 and 22 in the user area 4 are normal without any defective memory cells, and the memory block 23 is determined to be defective including the defective memory cells. The memory cell 31 in the spare area 5 is assumed to be normal.

The contents of the substitute table 1 generated based on the above inspection results are shown below. FIG. 2B is a schematic diagram showing alternative block addresses stored in the alternative table 1.

The alternative table 1 includes a flash memory 6
The substitute block address corresponding to each memory block in the user area 4 is stored. The alternative block address stored in the alternative table 1 is FFh (all 1) because replacement is not required if the memory block in the user area 4 is normal, and is set in the spare area 5 if the memory block is defective. The block address of the memory block.

The alternative block address column 41 located at the head of the alternative table 1 stores an alternative block address corresponding to the memory block 21 of FIG. Since the corresponding memory block 21 is normal, FFh is stored in the alternative block address column 41. Similarly, since the memory block 22 in FIG. 2A is also normal, FFh is stored in the alternative block address column 42.

On the other hand, since the memory block 23 in FIG. 2A is defective, the substitute block address column 43 stores the block address F0h of the memory block 31 in the spare area 5.

Thus, in FIG. 2A, when the physical addresses 0000h and 0100h are designated, the memory blocks 21 and 22 are used, respectively, and when the physical address 0200h is designated, the memory block 23 is replaced by the memory block 23. 31 is used.

Next, the procedure for generating the substitution table 1 will be described. First, the entire area of the substitution table 1 is erased. When erasing is performed, all areas of the substitution table 1 are all 1 (FF
h). Next, the block address in the spare area 5 is written only in the table column corresponding to the memory block including the defective memory cell found by the inspection of the flash memory 6.

Writing to this table is performed by writing the lowest block (for example, block address = F) in the spare area 5.
This is performed by sequentially allocating the alternative memory blocks from 0h) and registering the block address. In addition,
The allocation order of the memory blocks does not have to be from the lowest block, and may be in any other order.

In the substitution table 1, the block address in the spare area 5 is written in the memory block to be replaced, and the normal memory block in which the substitution is not executed is not written and remains in FFh. .

Next, the procedure for addressing the flash memory 6 using the substitution table 1 will be described. In FIG. 1, an address signal A is input from the outside of the flash memory chip.
0 to A15 are supplied. Address signals A0 to A15
Is a logical address, and the upper 8-bit block address signals A8-A15 and the intra-block address signals A0-
It is composed of A7.

The substitution table 1 receives the input block address signals A8 to A15 and outputs the substitution block address signals B8 to B15 stored in the table. For example, if the address signals A8 to A15 = 00h are input, the address signals B8 to B15 = FFh are output, if the address signals A8 to A15 = 01h are input, the address signals B8 to B15 = FFh are output, and the address signals When A8 to A15 = 02h is input, address signals B8 to B15 = F0h are output.

When the alternative block address signals B8 to B15 are FFh, it means that the memory block need not be replaced, and when the address signals B8 to B15 are not FFh, it means that the memory block needs to be replaced.

The AND circuit 3 receives the alternative block address signals B8 to B15 and the signal S0 as input signals and outputs a logical product of the input signals. Input signal S0 is always "1"
(“H”), and the AND circuit 3 outputs the address signal B8 ...
"1" is output only when 8 bits of B15 are all 1 (FFh). The output signal of the AND circuit 3 is supplied to the selection terminal SEL of the selector 2.

The selector 2 has two input terminals A and B. Block address signals A8 to A15 supplied from the outside of the flash memory chip are supplied to the input terminal A, and block address signals B8 to B15 supplied from the substitution table 1 are supplied to the input terminal B.

When "1" is supplied to the selection terminal SEL of the selector 2, the address signals A8 to A15 of the input terminal A are output from the output terminal Y, and when "0" is supplied to the selection terminal SEL, the input signal is input. The address signals B8 to B15 of the terminal B are output from the output terminal Y.

When the output block address signals B8 to B15 of the alternative table 1 are FFh, the selector 2 outputs "1" to the selection terminal SEL and therefore outputs the input block address signals A8 to A15 of the input terminal A. .

On the other hand, output block address signals B8 to B
If 15 is other than FFh, "0" is supplied to the selection terminal SEL, so the block address signal B8 of the input terminal B
~ B15 is output. Hereinafter, the outputs of the selector 2 will be referred to as address signals Y8 to Y15.

The block address signals Y8 to Y15 and the intra-block address signals A0 to A7 output from the selector 2 are supplied to the flash memory 6 as physical addresses.

In the flash memory 6, the memory block in the memory is designated by the block address signals Y8 to Y15, and the address in the memory block is designated by the in-block address signals A0 to A7.

As a result, if the memory block in the user area 4 is normal, that memory block is designated,
If the memory block in the user area 4 is defective, the memory block in the spare area 5 is designated instead of the memory block.

When the memory block is normal,
The case where FFh data is registered in the substitution table 1 has been described above.
It becomes impossible to specify the physical address of Fh.

Therefore, when the memory block is normal, instead of FFh (all 1), 00h (all 0).
May be registered in the substitution table 1. In that case, the AND circuit 3 is used as an OR circuit, and the input signal S
It is sufficient to always set 0 to “0” (“L”). The OR circuit is
Only when the address signals B8 to B15 are all 0 (00h), "0" is output to the selector 2.

In that case, the selector 2 has a selection terminal SEL.
The address signals A8 to A15 of the input terminal A are output when "0" is supplied to the input terminal, and the address signals B8 to B15 of the input terminal B are output when "1" is supplied to the selection terminal SEL.

FIG. 3 is a block diagram showing the structure of a flash memory chip according to another embodiment. The flash memory 6 is the same as that of the above-described embodiment, but the substitution table 11 is different.

The alternative table 1 of FIG. 1 receives 8-bit input address signals A8 to A15 and outputs 8-bit input address signals A8 to A15. , 8-bit input address signals A8-A15 are received, and 9-bit alternative address signals B8-B16 are output.

The substitute table 11 corresponds to each memory block in the user area 4 of the flash memory 6,
A 9-bit alternative address is stored. FIG. 4 is a schematic diagram showing the contents of the substitution table 11 generated corresponding to the flash memory 6 shown in FIG. The alternative address columns 51, 52, 53 store the alternative addresses corresponding to the memory blocks 21, 22, 23 of the flash memory 6, respectively.

Alternative address columns 51 (1FFh), 52
(1FFh) and 53 (0F0h) are the alternative address columns 41 (FFh), 42 (FFh), and 43 (F) of FIG. 2B.
0h), a selection bit B16 of 1 bit is added to the highest order. The selection bit B16 is a bit which becomes "1" when the memory block is normal and becomes "0" when the memory block is defective.

In the alternative address columns 51 and 52, since the corresponding memory block is normal, "1" is placed at the top of FFh.
1FFh to which the bit is added is stored. Since the corresponding memory block is defective, the alternative address column 53 stores 0F0h in which a "0" bit is added to the uppermost position of the memory block address F0h in the spare area 5.

In FIG. 3, the substitution table 11 receives the input address signals A8 to A15 and outputs the 9-bit substitution addresses B8 to B16 stored in the table. For example, when the address signals A8 to A15 = 00h are input, the address signals B8 to B16 = 1FFh are output, and when the address signals A8 to A15 = 01h are input, the address signals B8 to B16 = 1FFh are output, and the address signals When A8 to A15 = 02h is input, address signals B8 to B16 = 0F0h are output.

When 1 is supplied to the selection terminal SEL, the selector 2 outputs the address signals A8 to A15 of the input terminal A from the output terminal Y, and the selection terminal S
If 0 is supplied to EL, the address signal B of the input terminal B
8 to B15 are output from the output terminal Y.

Alternative address signals B8 to B1 output from the alternative table 11 are applied to the selection terminal SEL of the selector 2.
Since the most significant bit signal B16 of 6 is supplied, when the corresponding memory block is normal, the input address signal A
8 to A15 are output, and when the corresponding memory block is defective, alternative address signals B8 to B15 are output.

Here, the address signals B8 to B15 are lower 8-bit signals of the signals B8 to B16 output from the substitution table 11. The flash memory 6 is addressed by block address signals Y8 to Y15 output from the output terminal Y of the selector 2 and in-block address signals A0 to A7 supplied from the outside.

The block address signals Y8 to Y15 specify a memory block in the flash memory 6, and the in-block address signals A0 to A7 specify an address in the memory block.

As described above, by registering the alternative addresses B8 to B16 to which the selection bit B16 is added in the alternative table 11, the memory block can be replaced without using the AND circuit.

Further, there is no memory block (FFh) that cannot be used as in the above-described embodiment, and it is possible to use the memory blocks in all spare areas.

The selection bit B16 registered in the alternative table 11 does not necessarily have to be set to the most significant bit of the alternative addresses B8 to B16, but may be set to the least significant bit, for example. The selection signal B16 does not have to be 1 bit.

In the above embodiments, the case where the block address signals A8 to A15 or Y8 to Y15 have 8 bits and the intra-block address signals A0 to A7 have 8 bits has been described as an example, but the present invention is not limited to this. It can be applied to address signals having various numbers of bits.

Further, the flash memory and the substitution table may be constituted by a non-volatile memory other than the EEPROM such as the EPROM. As in this embodiment, by providing a circuit for replacing a memory block having a defective memory cell in the flash memory chip, the user can perform a normal flash operation without taking any measures against the defective memory cell. It can be used as memory.

Further, by replacing the memory block having the defective memory cell in the user area with the memory block in the spare area, a continuous logical address space can be secured and specified from the outside.

By using the selector, one of the input logical block address signals A8 to A15 or the alternative block address signals B8 to B15 is transferred to the block address signal Y8.
By supplying Y15 to the flash memory, it is not necessary to register the substitution destination block addresses for all the memory blocks in the substitution table, and it is sufficient to register the substitution destination block addresses only for the defective memory blocks. It is easy to create a substitute table.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0059]

As described above, according to the present invention,
By using the substitution table, even if a memory block in the user memory area is defective, for example, a memory block in the spare memory area can be allocated instead of the memory block, so that a continuous logical address space is secured. be able to.

Further, it is not necessary to register the physical addresses for all the memory blocks of the user memory area in the substitution table, but the physical addresses only for the memory blocks to be substituted are registered to perform the substitution. Since it is not necessary to register a physical address for a memory block that does not exist, it is easy to create a substitute table.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory chip according to an exemplary embodiment of the present invention.

FIG. 2A is a schematic diagram showing a configuration example of the flash memory shown in FIG. FIG. 2B is a schematic diagram showing alternative block addresses stored in the alternative table shown in FIG.

FIG. 3 is a block diagram showing a configuration of a memory chip according to another embodiment.

FIG. 4 is a schematic diagram showing contents of a substitution table according to another embodiment generated corresponding to the flash memory shown in FIG.

[Explanation of symbols]

 1, 11 Alternative table 2 Selector 3 AND circuit 4 User area 5 Spare area 6 Flash memory

Claims (2)

[Claims] 1. A non-volatile memory for accessing data according to input address data (A8 to A15) supplied from the outside, and a user memory area having a plurality of memory blocks capable of storing data ( 4) and a memory block array (6) having a spare memory area (5) having a spare memory block for use in place of the memory block in the user memory area, and the user memory according to input address data. Outputs either alternative address data indicating a memory block in the spare memory area that substitutes for a memory block in the area or non-replacement address data indicating that the memory block is not substituted. The substitute table (1) and the substitute data output by the substitute table are non-substitute addresses. A selector (2) which outputs the input address data when the substitute data is the substitute data and outputs the substitute address data when the substitute data is the substitute address data. Non-volatile memory for access. 2. A user memory area (4) having a plurality of memory blocks capable of storing data, and a spare memory area (4) having a spare memory block for replacing the memory block in the user memory area. A method of accessing data according to input address data (A8 to A15) supplied from the outside, to a nonvolatile memory having 5), wherein the user memory area in the user memory area is Outputting alternative data of either alternative address data indicating a memory block in the spare memory area that substitutes for the memory block or non-replacement address data indicating that the memory block is not substituted; When the alternative data is non-alternative address data, input address data is output address To the non-volatile memory, which includes a step of outputting the alternative address data as output address data when the alternative data is alternative address data, and a step of accessing the non-volatile memory according to the output address data. Data access method.