CN116565026A - Thin film transistor and preparation method thereof - Google Patents

Thin film transistor and preparation method thereof Download PDF

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Publication number
CN116565026A
CN116565026A CN202310528523.2A CN202310528523A CN116565026A CN 116565026 A CN116565026 A CN 116565026A CN 202310528523 A CN202310528523 A CN 202310528523A CN 116565026 A CN116565026 A CN 116565026A
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China
Prior art keywords
electrode
region
thin film
film transistor
diffusion channel
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CN202310528523.2A
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Inventor
薛兴坤
崔相弦
脱穷
顾婷婷
李泽伦
徐汉东
王朝辉
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202310528523.2A priority Critical patent/CN116565026A/en
Publication of CN116565026A publication Critical patent/CN116565026A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The embodiment of the disclosure provides a thin film transistor and a preparation method thereof, and relates to the field of semiconductors. The thin film transistor includes a first electrode, a second electrode, an oxide semiconductor layer, and a hydrogen diffusion channel. The first electrode is a source electrode or a drain electrode of the thin film transistor. The second electrode is a drain electrode or a source electrode of the thin film transistor. The oxide semiconductor layer includes a first region and a second region electrically connected to the first electrode and the second electrode, respectively. The first region and/or the second region includes a hydrogen element. The hydrogen diffusion channel is in contact with a portion of the first region and/or a portion of the second region for diffusing hydrogen gas to the first region and/or the second region. The embodiment of the disclosure is at least beneficial to reducing the contact resistance between the source electrode and/or the drain electrode of the thin film transistor and the oxide semiconductor layer and improving the performance of the thin film transistor.

Description

Thin film transistor and preparation method thereof
Technical Field
The disclosure belongs to the field of semiconductors, and particularly relates to a thin film transistor and a preparation method thereof.
Background
Thin film transistors (Thin Film Transistor, TFT) are widely used in electronic devices such as integrated circuits and image devices (display devices). In performing TFT fabrication, it is necessary to reduce contact resistance between a source (source electrode), a drain (drain electrode) and a semiconductor layer (e.g., an oxide semiconductor layer) in order to improve TFT performance.
Disclosure of Invention
The embodiment of the disclosure provides a thin film transistor and a preparation method thereof, which can at least reduce the contact resistance between a source electrode and/or a drain electrode and an oxide semiconductor layer, thereby improving the performance of the TFT.
The embodiment of the disclosure provides a thin film transistor, comprising: a first electrode which is a source electrode or a drain electrode of the thin film transistor; a second electrode which is a drain electrode or a source electrode of the thin film transistor; an oxide semiconductor layer including a first region and a second region electrically connected to the first electrode and the second electrode, respectively, the first region and/or the second region including a hydrogen element therein; and a hydrogen diffusion channel in contact with a portion of the first region and/or a portion of the second region for diffusing hydrogen to the first region and/or the second region.
In some exemplary embodiments of the present disclosure, the thin film transistor further includes: an interlayer insulating layer on a surface of a first side of the first hydrogen diffusion channel, the first side of the first hydrogen diffusion channel being a side of the first hydrogen diffusion channel remote from the substrate. The second electrode is located on the surface of the first side of the interlayer insulating layer, and the first side of the interlayer insulating layer is the side, away from the substrate, of the interlayer insulating layer.
In some exemplary embodiments of the present disclosure, the thin film transistor further includes: a trench penetrating the second electrode, the interlayer insulating layer, and the first hydrogen diffusion channel and extending into the first electrode; wherein the oxide semiconductor layer is positioned on the inner wall of the groove and the surface of the first side of the second electrode, and the first side of the second electrode is the side, away from the substrate, of the second electrode; the grid dielectric layer is positioned on the outer surface of the oxide semiconductor layer on the inner wall of the groove; and the gate electrode is filled in the groove containing the oxide semiconductor layer and the gate dielectric layer.
In some exemplary embodiments of the present disclosure, the oxide semiconductor layer includes IGZO (Indium Gallium Zinc Oxide ).
The disclosed embodiment provides a semiconductor device, including: a thin film transistor as in any of the embodiments of the present disclosure.
The embodiment of the disclosure provides a preparation method of a thin film transistor, which comprises the following steps: forming a first electrode which is a source electrode or a drain electrode of the thin film transistor; forming a second electrode which is a drain electrode or a source electrode of the thin film transistor; forming an oxide semiconductor layer including a first region and a second region electrically connected to the first electrode and the second electrode, respectively; forming a hydrogen diffusion channel in contact with a portion of the first region and/or a portion of the second region; and performing annealing treatment to diffuse hydrogen to the first region and/or the second region through the hydrogen diffusion channel so that the first region and/or the second region comprises hydrogen.
In some exemplary embodiments of the present disclosure, the method further comprises: a trench is formed through the second electrode, the interlayer insulating layer, and the first hydrogen diffusion channel and extends into the first electrode.
Wherein forming the oxide semiconductor layer includes: the oxide semiconductor layer is formed on the inner wall of the trench and the surface of the first side of the second electrode, which is the side of the second electrode away from the substrate.
Wherein the method further comprises: forming a gate dielectric layer, wherein the gate dielectric layer is positioned on the outer surface of the oxide semiconductor layer on the inner wall of the groove; and forming a gate electrode, wherein the gate electrode is filled in the groove containing the oxide semiconductor layer and the gate dielectric layer.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages: and diffusing hydrogen into the first region and/or the second region of the oxide semiconductor layer through a hydrogen diffusion channel which is in contact with part of the first region and/or part of the second region of the oxide semiconductor layer, so that the first region and/or the second region of the oxide semiconductor layer contains hydrogen, and meanwhile, the first region and the second region of the oxide semiconductor layer are respectively and electrically connected with a source electrode and a drain electrode of the thin film transistor, thereby reducing the contact resistance between the source electrode and/or the drain electrode of the thin film transistor and the oxide semiconductor layer and improving the performance of the thin film transistor.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
Fig. 1 is a schematic structural diagram corresponding to a step in a method for manufacturing a thin film transistor according to an embodiment of the disclosure.
Fig. 2 is a schematic structural diagram corresponding to another step in the method for manufacturing a thin film transistor according to an embodiment of the disclosure.
Fig. 3 is a schematic structural diagram corresponding to another step in the method for manufacturing a thin film transistor according to an embodiment of the disclosure.
Fig. 4 is a schematic structural diagram corresponding to another step in the method for manufacturing a thin film transistor according to an embodiment of the disclosure.
Fig. 5 is a schematic structural diagram corresponding to another step in the method for manufacturing a thin film transistor according to an embodiment of the disclosure.
Fig. 6 is a schematic structural diagram corresponding to another step in the method for manufacturing a thin film transistor according to an embodiment of the disclosure.
Fig. 7 is a schematic structural diagram corresponding to another step in the method for manufacturing a thin film transistor according to an embodiment of the disclosure.
Fig. 8 is a schematic structural diagram corresponding to another step in the method for manufacturing a thin film transistor according to an embodiment of the disclosure.
Fig. 9 is a schematic structural diagram corresponding to another step in the method for manufacturing a thin film transistor according to an embodiment of the disclosure.
Fig. 10 is a schematic structural diagram corresponding to another step in the method for manufacturing a thin film transistor according to an embodiment of the disclosure.
Fig. 11 is a schematic structural diagram corresponding to another step in the method for manufacturing a thin film transistor according to an embodiment of the disclosure.
Fig. 12 is a schematic structural diagram corresponding to another step in the method for manufacturing a thin film transistor according to an embodiment of the disclosure.
Fig. 13 is a schematic structural diagram corresponding to another step in the method for manufacturing a thin film transistor according to an embodiment of the disclosure.
Fig. 14 is a schematic structural diagram corresponding to another step in the method for manufacturing a thin film transistor according to an embodiment of the disclosure.
Fig. 15 shows a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
Detailed Description
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the present disclosure is not limited to the following description, and its modes and details may be changed into various forms without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure should not be construed as limited to the description of the embodiments shown below.
For ease of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like may not indicate actual positions, sizes, ranges, and the like. Accordingly, the disclosed invention is not necessarily limited to the disclosed positions, sizes, ranges, etc. of the drawings, etc.
In this specification and the like, for convenience, first, second, and the like ordinal numbers are appended, and the order of steps and the order of lamination may not be represented. Therefore, for example, the description may be given by appropriately replacing "first" with "second" or "third" or the like. Further, the ordinal words described in the specification and the like may not coincide with the ordinal words used to designate one embodiment of the present disclosure.
In this specification, for convenience, terms such as "upper" and "lower" are used to describe positional relationships of constituent elements with reference to the drawings. In addition, the positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the present specification, and may be replaced as appropriate.
Note that in this specification and the like, when the structure of the invention is described using drawings, a symbol indicating the same portion may be commonly used in different drawings.
In the embodiment of the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain and a source, and current can flow through the drain, the channel region, and the source. The channel region refers to a region through which current mainly flows. In an embodiment of the present disclosure, the thin film transistor is a field effect transistor.
In addition, in the case of using transistors having different polarities, the case of changing the current direction during circuit operation, or the like, the functions of the source and the drain may be exchanged with each other. Thus, in embodiments of the present disclosure, the source and drain may be interchanged.
Note that the channel length refers to, for example, a region where a semiconductor layer (or a portion where current flows in the semiconductor layer) and a gate electrode overlap each other in a top view of the transistor (or a distance between a source and a drain in a region where a channel is formed when the transistor is in an on state).
In the presently disclosed embodiments, "electrically connected" includes the case of being connected by "an element having some electrical action". Here, the "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the connection objects. For example, the "element having a certain electric action" includes not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.
The present disclosure provides a thin film transistor that may include a first electrode, a second electrode, an oxide semiconductor layer, and a hydrogen diffusion channel. The first electrode may be a source electrode or a drain electrode of the thin film transistor. The second electrode may be a drain electrode or a source electrode of the thin film transistor. The oxide semiconductor layer may include a first region that may be electrically connected to the first electrode and a second region that may be electrically connected to the second electrode. The first region and/or the second region in the oxide semiconductor layer may include a hydrogen element (H). The hydrogen diffusion channel is in contact with a part of the first region and/or a part of the second region of the oxide semiconductor layer for diffusing hydrogen into the first region and/or the second region of the oxide semiconductor layer such that hydrogen element (H) is included in the first region and/or the second region in the oxide semiconductor layer.
In the embodiments of the present disclosure, the oxide semiconductor layer refers to a semiconductor layer made of an oxide semiconductor (oxide semiconductor). The oxide semiconductor is an oxide having semiconductor characteristics, and may be, for example, any one or a combination of two or more of In2O3 (indium oxide), znO (zinc oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), IZTO (indium tin zinc oxide), znON (zinc oxynitride), and the like, and IGZO is exemplified In the following embodiments, but the present disclosure is not limited thereto.
In the embodiment of the present disclosure, the hydrogen diffusion channel (H2 diffusion channel) refers to a channel that can be used to diffuse (Hydrogen diffusion) hydrogen into the first region and/or the second region in the oxide semiconductor layer, and may or may not include a solid substance (for example, siO2 (silicon dioxide) is illustrated below) that can achieve hydrogen diffusion, that is, air in the hydrogen diffusion channel. The hydrogen diffusion channel may realize doping of H in the first region and/or the second region in the oxide semiconductor layer by heat treatment under a mixed gas containing hydrogen.
According to the thin film transistor provided by the embodiment of the disclosure, the hydrogen is diffused into the first region and/or the second region of the oxide semiconductor layer through the hydrogen diffusion channel which is in contact with the part of the first region and/or the part of the second region of the oxide semiconductor layer, so that the first region and/or the second region of the oxide semiconductor layer contain hydrogen elements, and meanwhile, the first region and the second region of the oxide semiconductor layer are respectively electrically connected with the source electrode and the drain electrode of the thin film transistor, so that the contact resistance between the source electrode and/or the drain electrode of the thin film transistor and the oxide semiconductor layer can be reduced, and the performance of the thin film transistor is improved.
The method of manufacturing the thin film transistor according to the embodiments of the present disclosure is illustrated below with reference to fig. 1 to 14, but the present disclosure is not limited thereto. It will be appreciated that fig. 1-14 are partial schematic views of thin film transistors.
Referring to fig. 1, a substrate 101 is provided.
The material of the substrate is not particularly limited in the embodiments of the present disclosure. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate using silicon or silicon carbide as a material, a compound semiconductor substrate using silicon germanium or the like as a material, an SOI (Silicon On Insulator ) substrate, or the like can also be used, and a substrate provided with a semiconductor element can also be used as the substrate.
Referring to fig. 2, a first electrode 102 is formed on a part of the surface of a first side of a substrate 101, and here, it is assumed that the first electrode 102 is a source electrode (hereinafter denoted by S) of a thin film transistor.
In the embodiment of the present disclosure, the first sides may be denoted as upper sides, but are not limited thereto.
In an exemplary embodiment, the hydrogen diffusion channel may include a first hydrogen diffusion channel.
In an exemplary embodiment, the first hydrogen diffusion channel may include silicon dioxide.
Referring to fig. 3, a first hydrogen diffusion channel 103 is formed on a surface of a first side of the first electrode 102 and another part of a surface of the first side of the substrate 101.
Wherein the first side of the first electrode 102 is a side of the first electrode 102 away from the substrate 101. Another part of the surface of the first side of the substrate 101 refers to the surface of the first side of the substrate 101 that is not covered by the first electrode 102, which is exposed.
Referring to fig. 4, an interlayer insulating layer 104 is formed on the surface of the first side of the first hydrogen diffusion channel 103. Wherein the first side of the first hydrogen diffusion channel 103 is a side of the first hydrogen diffusion channel 103 away from the substrate 101.
In the embodiment of the present disclosure, the interlayer insulating layer may be made of any material having insulating properties, here SiN (silicon nitride) is taken as an example, but the present disclosure is not limited thereto.
Referring to fig. 5, a second electrode 105 of the thin film transistor is formed on a surface of a first side of the interlayer insulating layer 104. It is assumed here that the second electrode 105 is a drain electrode (hereinafter denoted by D) of a thin film transistor.
Referring to fig. 6, a trench 106 penetrating the second electrode 105, the interlayer insulating layer 104, and the first hydrogen diffusion channel 103 and extending into the first electrode 102 is formed.
In an exemplary embodiment, the thickness of the first hydrogen diffusion channel on the surface of the first side of the first electrode may be 10 to 30nm.
In embodiments of the present disclosure, the thickness is relative to a surface perpendicular to the first side of the substrate. For example, as shown in fig. 6, the thickness of the first hydrogen diffusion channel 103 on the surface of the first side of the first electrode 102 is denoted as h2, and the thickness of the first hydrogen diffusion channel 103 on the surface of the first side of the substrate 101 is denoted as h1. Where h1 is greater than h2, and h1 is the sum of the thickness of the first electrode 102 and h 2.
In the embodiment of the disclosure, the H2 thickness of 10-30 nm is selected, which is beneficial to realizing effective doping of H in the first region of the oxide semiconductor layer, so that the contact area between the first electrode 102 and the H-doped oxide semiconductor layer (for example, IGZO, where the H-doped IGZO is expressed as IGZO: H) is as large as possible, thereby being beneficial to reducing the contact resistance between the source electrode of the thin film transistor and the oxide semiconductor layer; on the other hand, the channel length of the thin film transistor can be ensured to meet the requirement. When H2 is less than 10nm, efficient doping of H in the first region cannot be achieved; when h2 is greater than 30nm, the channel length of the thin film transistor becomes small.
Referring to fig. 7, an oxide semiconductor layer 107 is formed on the inner wall of the trench 106 and the surface of the first side of the second electrode 105. Wherein the first side of the second electrode 105 is a side of the second electrode 105 away from the substrate 101.
The oxide semiconductor (oxide semiconductor) layer In the embodiments of the present disclosure may employ IGZO, and the ratio of different elements In IGZO is not limited, for example, in2o3:ga2o3:zno=1:1:1, but the present disclosure is not limited thereto.
In the embodiment of the disclosure, IGZO is adopted as the oxide semiconductor layer, and compared with other materials such as LTPS (Low Temperature Poly-Silicon, low-temperature polysilicon) and a-Si: H (hydrogenated amorphous Silicon), the oxide semiconductor layer has smaller leakage current and larger mobility.
Referring to fig. 8, a gate dielectric layer 108 is formed on an outer surface of the oxide semiconductor layer 107 on an inner wall of the trench 106.
In the embodiments of the present disclosure, as the gate dielectric layer of the thin film transistor, an insulating layer including one or more of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, a hafnium oxide layer, a yttrium oxide layer, a zirconium oxide layer, a gallium oxide layer, a tantalum oxide layer, a magnesium oxide layer, a lanthanum oxide layer, a cerium oxide layer, a neodymium oxide layer, and the like, which are formed by a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) method, a sputtering method, or the like, may be used. A single insulating layer or a plurality of insulating layers (two or more layers) selected from the above materials may be used.
Referring to fig. 9, a gate electrode 109 is filled in a trench including an oxide semiconductor layer 107 and a gate dielectric layer 108.
Referring to fig. 10, an annealing treatment is performed to diffuse hydrogen through the first hydrogen diffusion channel 103 into a first region on the oxide semiconductor layer 107 in contact with the first electrode 102, so that the first region includes hydrogen element (H) in addition to the oxide semiconductor.
In the embodiment of the disclosure, the hydrogen annealing treatment may be performed by using a mixed gas containing H2 (hydrogen) and Ar (argon)/N2 (nitrogen), wherein the ratio of H2 in the mixed gas may be 4-20%, 2-10 atm pressure (atmospheric pressure), and the treatment temperature is 20-90 min at 200-300 ℃. By performing the hydrogen annealing treatment under such conditions, efficient hydrogen doping into the oxide semiconductor layer can be achieved.
In an exemplary embodiment, the hydrogen diffusion channel may include a second hydrogen diffusion channel. Wherein the second hydrogen diffusion channel at least partially covers an outer surface of the second region, the outer surface of the second region being remote from the outer surface of the substrate.
In the embodiment of the present disclosure, the second hydrogen diffusion channel refers to a hydrogen diffusion channel for diffusing hydrogen to a second region where the oxide semiconductor layer is in contact with the second electrode. In some embodiments, the second hydrogen diffusion channel may be an air channel, for example as shown in fig. 10.
After the annealing treatment, a thin film transistor shown in fig. 11 is formed, and the oxide semiconductor layer of the thin film transistor includes a first region 111a in contact with the first electrode 102 and a second region 111b in contact with the second electrode 105. The first region 111a and the second region 111b include a hydrogen element therein, and when the oxide semiconductor layer is IGZO, the first region 111a and the second region 111b may be denoted as IGZO: H.
In an exemplary embodiment, a lateral diffusion distance between the first hydrogen diffusion channel and the oxide semiconductor layer is less than 2 μm.
As shown in fig. 11, the lateral direction refers to the extending direction of the substrate 101, which is perpendicular to the above-described thickness direction. The lateral diffusion distance refers to a distance W between the left boundary of the first hydrogen diffusion channel 103 and the oxide semiconductor layer, or a distance between the right boundary of the first hydrogen diffusion channel 103 and the oxide semiconductor layer.
In the disclosed embodiment, the lateral diffusion distance between the first hydrogen diffusion channel and the oxide semiconductor layer is less than 1/2 of the CD (critical dimension, critical dimension/feature size) of the Active Area (AA) of the thin film transistor. Because H molecules are small and are easy to diffuse in SiO2, the selection range of the transverse diffusion distance is also large. In addition, in order to achieve effective doping of the oxide semiconductor layer and to improve doping efficiency, the doping time is shortened, and the lateral diffusion distance needs to be less than 2 μ.
In other embodiments, the second hydrogen diffusion channel may include a physical substance therein, for example, as shown in fig. 12, and the second hydrogen diffusion channel 112 may include silicon dioxide.
In an exemplary embodiment, the second hydrogen diffusion channel has a thickness of 10 to 50nm.
In the embodiment of the disclosure, the second hydrogen diffusion channel with the thickness of 10-50 nm is selected, so that on one hand, effective doping of H in the second region of the oxide semiconductor layer is facilitated, contact resistance between the drain electrode of the thin film transistor and the oxide semiconductor layer is reduced, and meanwhile, consistency of doping concentrations of the first region and the second region is ensured; on the other hand, the channel length of the thin film transistor can be ensured to meet the requirement.
Referring to fig. 13, an annealing treatment is performed to diffuse hydrogen through the first hydrogen diffusion channel 103 into a first region on the oxide semiconductor layer 107 in contact with the first electrode 102, so that the first region includes hydrogen element (H) in addition to the oxide semiconductor. Meanwhile, hydrogen is also diffused through the second hydrogen diffusion channel 112 into the second region on the oxide semiconductor layer 107 in contact with the second electrode 105, so that the second region includes hydrogen element (H) in addition to the oxide semiconductor.
After the annealing treatment, a thin film transistor as shown in fig. 14 is formed, and the oxide semiconductor layer of the thin film transistor includes a first region 141a in contact with the first electrode 102 and a second region 141b in contact with the second electrode 105. The first and second regions 141a and 141b include a hydrogen element therein, and when the oxide semiconductor layer is IGZO, the first and second regions 141a and 141b may be denoted as IGZO: H.
In an exemplary embodiment, the hydrogen diffusion channel may include silicon dioxide.
In the embodiment of the disclosure, the first hydrogen diffusion channel and the second hydrogen diffusion channel are both made of silicon dioxide, so that the uniformity of hydrogen doping in the first area contacted with the first electrode and the second area contacted with the second electrode can be ensured.
In the embodiment of the present disclosure, the gate electrode, the source electrode, the drain electrode may be formed using a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt (Co), or the like, an alloy containing the above metal element as a component, an alloy combining the above metal elements, or the like.
The first electrode, the second electrode, the oxide semiconductor layer, the hydrogen diffusion channel, the interlayer insulating layer, the gate dielectric layer, the gate electrode, and the like in the embodiments of the present disclosure may be formed using a sputtering method or a PECVD method, or may be formed using other methods, for example, using a thermal metalorganic chemical vapor deposition (Chemical Vapor Deposition, CVD) method, such as a metalorganic chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD) method, an atomic layer deposition (Atomic Layer Deposition, ALD) method, or the like. Since the thermal CVD method is a film formation method that does not use plasma, defects caused by plasma damage do not occur.
The Channel surrounding gate electrode in the thin film transistor formed using the manufacturing method shown in fig. 1 to 14 may be referred to as a CAA (Channel-All-Around) TFT. When IGZO is used for the oxide semiconductor layer, it may be referred to as CAA IGZO TFT.
It will be appreciated that the solution provided by the embodiments of the present disclosure is applicable not only to CAATFT, but also to other TFT structures, such as planar TFT structures, and that the method provided by the embodiments of the present disclosure may be employed to reduce the resistance of the source and/or drain electrodes.
In the thin film transistor provided in the embodiments of the present disclosure, oxygen defects (Vo) are included in an oxide semiconductor layer, and hydrogen is added to the oxygen defects in a first region and/or a second region in the oxide semiconductor layer by using a hydrogen annealing process, so that n-type doping (n-type doping) is caused in the oxide semiconductor layer, for example, IGZO, and a donor level is formed near a conduction band, thereby increasing conductivity of the first region and/or the second region of the oxide semiconductor layer, reducing contact resistance of a first electrode electrically connected to the first region, and/or reducing contact resistance of a second electrode electrically connected to the second region. The thin film transistor can reduce off-state current, thereby being capable of suppressing power consumption. In addition, the thin film transistor can promote electric field (E) F ) And reduces the electron transfer barrier (Electron migration barrier) to achieve higher field effect mobility.
Further, the embodiments of the present disclosure also provide a semiconductor device, which may include the thin film transistor in any of the embodiments of the present disclosure.
The semiconductor device in the embodiments of the present disclosure may be any device including the above-described thin film transistor, and the type of the semiconductor device is not limited in the present disclosure. The semiconductor device may be any of a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device (for example, dynamic random access memory (Dynamic Random Access Memory, DRAM)), an imaging device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like), and the like, for example.
For example, the CAA TFT provided in the above embodiment may be used to fabricate a DRAM, which may be referred to as a CAA DRAM.
As shown in fig. 15, the method for manufacturing a thin film transistor according to the embodiment of the present disclosure may include steps S1510 to S1550.
In S1510, a first electrode is formed, the first electrode being a source electrode or a drain electrode of the thin film transistor.
In S1520, a second electrode is formed, which is a drain electrode or a source electrode of the thin film transistor.
In S1530, an oxide semiconductor layer including a first region and a second region electrically connected to the first electrode and the second electrode, respectively, is formed.
In S1540, a hydrogen diffusion channel is formed in contact with a portion of the first region and/or a portion of the second region.
In S1550, an annealing process is performed to diffuse hydrogen to the first region and/or the second region through the hydrogen diffusion channel so that hydrogen element is included in the first region and/or the second region.
In an exemplary embodiment, the hydrogen diffusion channel may include a first hydrogen diffusion channel.
Wherein forming the first electrode may include: providing a substrate; the first electrode is formed on a portion of a surface of the first side of the substrate.
Wherein, forming the hydrogen diffusion channel may include: the first hydrogen diffusion channel is formed on a surface of a first side of the first electrode, which is a side of the first electrode remote from the substrate, and on another part of the surface of the first side of the substrate.
Wherein the method may further comprise: an interlayer insulating layer is formed on a surface of a first side of the first hydrogen diffusion channel, the first side of the first hydrogen diffusion channel being a side of the first hydrogen diffusion channel remote from the substrate.
Wherein forming the second electrode may include: the second electrode is formed on a surface of a first side of the interlayer insulating layer, which is a side of the interlayer insulating layer away from the substrate.
In an exemplary embodiment, the hydrogen diffusion channel may include a second hydrogen diffusion channel. Wherein the method may further comprise: forming the second hydrogen diffusion channel at least partially covering an outer surface of the second region, the outer surface of the second region being remote from the outer surface of the substrate.
In an exemplary embodiment, performing the annealing process may include: and (3) annealing treatment is carried out by adopting mixed gas containing hydrogen at preset atmospheric pressure and preset temperature, wherein the hydrogen content in the mixed gas is 4-20%, the preset atmospheric pressure is 2-10 atm, the preset temperature is 200-300 ℃, and the treatment temperature is 20-90 min.
In an exemplary embodiment, the method may further include: a trench is formed through the second electrode, the interlayer insulating layer, and the first hydrogen diffusion channel and extends into the first electrode.
Wherein forming the oxide semiconductor layer may include: the oxide semiconductor layer is formed on the inner wall of the trench and the surface of the first side of the second electrode, which is the side of the second electrode away from the substrate.
Wherein the method may further comprise: forming a gate dielectric layer, wherein the gate dielectric layer is positioned on the outer surface of the oxide semiconductor layer on the inner wall of the groove; and forming a gate electrode, wherein the gate electrode is filled in the groove containing the oxide semiconductor layer and the gate dielectric layer.
In the description of the present specification, a description of the terms "some embodiments," "exemplary," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present disclosure have been shown and described above, it should be understood that the above embodiments are illustrative and not to be construed as limiting the present disclosure, and that variations, modifications, alternatives, and variations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present disclosure, which is therefore intended to be within the scope of the present disclosure as defined by the claims and specification.

Claims (10)

1. A thin film transistor, comprising:
a first electrode which is a source electrode or a drain electrode of the thin film transistor;
a second electrode which is a drain electrode or a source electrode of the thin film transistor;
an oxide semiconductor layer including a first region and a second region electrically connected to the first electrode and the second electrode, respectively, the first region and/or the second region including a hydrogen element therein;
and a hydrogen diffusion channel in contact with a portion of the first region and/or a portion of the second region for diffusing hydrogen to the first region and/or the second region.
2. The thin film transistor according to claim 1, wherein the hydrogen diffusion channel comprises a first hydrogen diffusion channel; wherein, the thin film transistor further includes:
a substrate, the first electrode being located on a portion of a surface of the first side of the substrate;
wherein the first hydrogen diffusion channel is located on a surface of a first side of the first electrode and another portion of a surface of the first side of the substrate, the first side of the first electrode being a side of the first electrode remote from the substrate.
3. The thin film transistor according to claim 2, wherein a thickness of the first hydrogen diffusion channel on a surface of the first side of the first electrode is 10 to 30nm.
4. The thin film transistor according to claim 2, wherein a lateral diffusion distance between the first hydrogen diffusion channel and the oxide semiconductor layer is less than 2 μ conductive.
5. The thin film transistor according to any one of claims 2 to 4, wherein the hydrogen diffusion channel includes a second hydrogen diffusion channel; wherein the second hydrogen diffusion channel at least partially covers an outer surface of the second region, the outer surface of the second region being remote from the outer surface of the substrate.
6. The thin film transistor according to claim 5, wherein the thickness of the second hydrogen diffusion channel is 10 to 50nm.
7. The thin film transistor of claim 1, wherein the hydrogen diffusion channel comprises silicon dioxide.
8. A method of manufacturing a thin film transistor, comprising:
forming a first electrode which is a source electrode or a drain electrode of the thin film transistor;
forming a second electrode which is a drain electrode or a source electrode of the thin film transistor;
forming an oxide semiconductor layer including a first region and a second region electrically connected to the first electrode and the second electrode, respectively;
forming a hydrogen diffusion channel in contact with a portion of the first region and/or a portion of the second region;
and performing annealing treatment to diffuse hydrogen to the first region and/or the second region through the hydrogen diffusion channel so that the first region and/or the second region comprises hydrogen.
9. The method of claim 8, wherein the hydrogen diffusion channel comprises a first hydrogen diffusion channel;
wherein forming the first electrode comprises:
providing a substrate;
forming the first electrode on a portion of a surface of the first side of the substrate;
wherein, form the hydrogen diffusion channel, include:
forming the first hydrogen diffusion channel on a surface of a first side of the first electrode, which is a side of the first electrode remote from the substrate, and on another part of the surface of the first side of the substrate;
wherein the method further comprises:
forming an interlayer insulating layer on a surface of a first side of the first hydrogen diffusion channel, the first side of the first hydrogen diffusion channel being a side of the first hydrogen diffusion channel remote from the substrate;
wherein forming the second electrode comprises:
the second electrode is formed on a surface of a first side of the interlayer insulating layer, which is a side of the interlayer insulating layer away from the substrate.
10. The method according to claim 8 or 9, wherein the annealing treatment is performed comprising:
and (3) annealing treatment is carried out by adopting mixed gas containing hydrogen at preset atmospheric pressure and preset temperature, wherein the hydrogen content in the mixed gas is 4-20%, the preset atmospheric pressure is 2-10 atm, the preset temperature is 200-300 ℃, and the treatment time is 20-90 min.
CN202310528523.2A 2023-05-10 2023-05-10 Thin film transistor and preparation method thereof Pending CN116565026A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116190443A (en) * 2022-09-23 2023-05-30 北京超弦存储器研究院 Method for manufacturing semiconductor device and semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116190443A (en) * 2022-09-23 2023-05-30 北京超弦存储器研究院 Method for manufacturing semiconductor device and semiconductor device
CN116190443B (en) * 2022-09-23 2024-03-15 北京超弦存储器研究院 Method for manufacturing semiconductor device and semiconductor device

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