JP2013214537A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology of enabling inhibition of characteristic deterioration of a thin film transistor in a semiconductor device including the thin film transistor which uses a metal oxide semiconductor film for a channel layer, particularly in a semiconductor device having a heat history after formation of the above-described thin film transistor.SOLUTION: A semiconductor device comprises a source electrode SE and a drain electrode DE which include a first electrode layer FE composed of a metal film such as aluminum (Al), silver (Ag), gold (Au) and copper (Cu), and a diffusion prevention layer DC which is formed between a channel layer CH and the first electrode layer FE so as to contact the channel layer CH in order to prevent the metal composing the first electrode layer FE from diffusing to the channel layer CH, and which is composed of a cobalt film.

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device including a field effect transistor using a metal oxide semiconductor film as a channel layer.

  Japanese Patent Laying-Open No. 2009-170905 (Patent Document 1) describes a technique for forming a thin film transistor on a display substrate. Specifically, in this thin film transistor, a gate electrode is formed on an insulating substrate, and a gate insulating film is formed on the insulating substrate covering the gate electrode. A first semiconductor pattern is formed on the gate insulating film, and a second semiconductor pattern is formed on the first semiconductor pattern. The first semiconductor pattern and the second semiconductor pattern serve as a channel layer. On this channel layer, data lines are formed so as to be in direct contact with each other, and ohmic contact is realized by the data lines and the second semiconductor pattern.

  In order to make an ohmic contact between the data line and the second semiconductor pattern, the data line is made of, for example, Ni, Co, Ti, Ag, Cu, Mo, Al, Be, Nb, Au, Fe, Se, or Ta. It is desirable to adopt a single film or multilayer film structure. Specifically, as an example of a multilayer film structure, a double film such as Ti / Al, Ta / Al, Ni / Al, Co / Al, Mo (Mo alloy) / Cu, or Ti / Al / Ti, Ta / Examples include triple films such as Al / Ta, Ti / Al / TiN, Ta / Al / TaN, Ni / AL / Ni, and Co / Al / Co.

JP 2009-170905 A

  Currently, thin film transistors (TFTs) used as drive elements for liquid crystal displays use amorphous silicon (a-Si) as a channel material because of low production costs and high uniformity of TFT characteristics. Yes. However, a thin film transistor using amorphous silicon as a channel material has a large threshold voltage shift caused by driving. Therefore, it is necessary to incorporate a correction circuit, which will become a major issue in the further advancement of liquid crystal display in the future. Yes.

  On the other hand, in a thin film transistor using a metal oxide semiconductor film typified by IGZO (indium gallium zinc oxide) as a channel layer, it is not necessary to incorporate a correction circuit because of the stability of the threshold voltage during driving. It is attracting attention as a driving element for future high-definition displays. In addition, in the current manufacturing process of a semiconductor device including a thin film transistor, heat treatment is necessary in the process of forming a passivation film, but the metal oxide semiconductor film itself can be formed at room temperature, and non-uniformity between elements It has a feature that it can be applied to a large area substrate. Therefore, a thin film transistor in which a metal oxide semiconductor film is used for a channel layer is a semiconductor element that can reduce manufacturing costs and is expected to be applied to a flexible element, an RFID tag, a thin film memory, and the like.

  On the other hand, with the increase in definition of liquid crystal displays, it will be necessary to make wiring finer in the future. For this reason, the current wiring materials such as molybdenum and molybdenum-tungsten alloy have insufficient conductivity, which causes problems such as signal delay in the wiring. In order to solve such a problem, for example, it is desirable to use a metal material having a low resistance of 3 μΩ · cm or less as a source electrode, a drain electrode, and a wiring material. Examples of such a metal material include aluminum (Al), silver (Ag), gold (Au), and copper (Cu).

  However, with regard to Al, Ag, Au, and Cu having low resistance values described above, Al, Ag, Au, and Cu are converted to source electrodes or the like by heat treatment applied in the semiconductor device manufacturing process such as a process of forming a passivation film. Diffusion from the drain electrode to the channel layer that is in direct contact with the source electrode or the drain electrode, and the diffused Al, Ag, Au, Cu is combined with oxygen contained in the metal oxide semiconductor film constituting the channel layer, thereby oxidizing the metal. Form things. As a result, there is a problem that the contact resistance between the source electrode (drain electrode) and the channel layer increases and the TFT characteristics deteriorate. There has been no solution to the problem that the metal element constituting the source electrode or the drain electrode diffuses into the channel layer formed of the metal oxide semiconductor film due to such heat treatment.

  An object of the present invention is to provide a technology capable of suppressing deterioration of characteristics of a thin film transistor in a semiconductor device including a thin film transistor using a metal oxide semiconductor film for a channel layer, particularly a semiconductor device having a thermal history after the formation of the thin film transistor described above. Is to provide.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor device in the present invention is a semiconductor device including a field effect transistor formed on an insulating substrate. In this case, the field effect transistor includes: (a) a source electrode and a drain electrode formed apart from each other; (b) formed between the source electrode and the drain electrode; and the source electrode and the drain electrode. A channel layer made of a metal oxide semiconductor film formed in contact with each of the electrodes; (c) a gate insulating film formed in contact with the channel layer; and (d) in contact with the gate insulating film. And a gate electrode formed in such a manner. Here, the source electrode and the drain electrode are configured to prevent (a1) a first electrode layer made of a metal film and (a2) a metal constituting the first electrode layer from diffusing into the channel layer. And a diffusion preventing layer formed to be in direct contact with the channel layer between the channel layer and the first electrode layer.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In a semiconductor device including a thin film transistor in which a metal oxide semiconductor film is used for a channel layer, in particular, a semiconductor device having a thermal history after formation of the above-described thin film transistor, deterioration of characteristics of the thin film transistor can be suppressed.

It is sectional drawing which shows the structure of the thin-film transistor in Embodiment 1 of this invention. 4 is a graph showing initial electrical characteristics and electrical characteristics after heating at 250 ° C. in the thin film transistor of Embodiment 1. It is a figure which shows the result of having analyzed the element distribution (In, Ga, Zn, Al, Co) of each layer of the thin-film transistor after a 250 degreeC heating by the secondary ion mass spectrometry. It is sectional drawing which shows the structure of the thin-film transistor in a comparative example. 4 is a graph showing initial electrical characteristics and electrical characteristics after heating at 250 ° C. in a thin film transistor of a comparative example. It is a figure which shows the result of having analyzed the elemental distribution (In, Ga, Zn, Al) of each layer of the thin-film transistor in the comparative example after a 250 degreeC heating by the secondary ion mass spectrometry. It is a figure which shows on-current in the case of using a tin oxide and zinc oxide for the channel layer of both the thin-film transistor in Embodiment 1, and the thin-film transistor in a comparative example. It is sectional drawing which shows the thin-film transistor of a bottom gate / bottom contact type structure. It is sectional drawing which shows the thin-film transistor of a top gate / top contact type structure. It is sectional drawing which shows the thin-film transistor of a top gate / bottom contact type structure. It is a figure which shows the result of having analyzed the element distribution (In, Zn, Ga, Cu, Co) in each layer of the thin-film transistor in Embodiment 2 after 250 degreeC heat processing by the secondary ion mass spectrometry. FIG. 10 is a plan view showing a TFT array constituting an active matrix liquid crystal display device in a fourth embodiment. 7 is a cross-sectional view illustrating a cross-sectional structure of a thin film transistor used in Embodiment 4. FIG. FIG. 16 is a plan view showing a memory cell array in which the thin film memories in the fifth embodiment are arranged in an array. FIG. 10 is a cross-sectional view showing a cross-sectional structure of a thin film memory in a fifth embodiment. FIG. 10 is a block diagram illustrating a configuration of an RFID tag according to Embodiment 6.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., unless otherwise specified, and in principle, it is not considered that it is clearly apparent in principle. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
The configuration of the thin film transistor TFT1 in the first embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing the configuration of the thin film transistor TFT1 in the first embodiment. In FIG. 1, first, a gate electrode GE is formed on an insulating substrate 1S, and a gate insulating film GOX is formed on the insulating substrate 1S so as to cover the gate electrode GE. A channel layer CH is formed on the gate insulating film GOX. Then, the source electrode SE and the drain electrode DE are formed so as to be separated from each other on the channel layer CH in a plan view and to extend on the gate insulating film GOX. The source electrode SE and the drain electrode DE include the first electrode layer FE made of a metal film, and the channel layer CH and the first electrode so as to prevent the metal constituting the first electrode layer FE from diffusing into the channel layer CH. The diffusion prevention layer DC is formed between the layers FE so as to be in direct contact with the channel layer CH.

  For example, quartz, glass, sapphire, a plastic film, or the like can be used as a material constituting the insulating substrate 1S, and the surface on the side where the gate electrode GE is formed may be coated as necessary. Here, a quartz substrate is used as the insulating substrate 1S.

  The gate electrode GE is made of a conductive material such as molybdenum (Mo), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), silver (Ag). ), Gold (Au), platinum (Pt), tantalum (Ta) or other metal materials, or transparent conductive materials such as indium tin oxide (ITO) or aluminum zinc oxide (AZO). Can do. Further, an evaporation method or a sputtering method can be used for forming the gate electrode GE, and an etching process or a lift-off process can be applied to the patterning. For example, a molybdenum film (Mo) having a thickness of 100 nm is formed by electron beam (EB) vapor deposition, and patterned by reactive ion etching (RIE (Reactive Ion Etching)) to form a gate electrode on the insulating substrate 1S. GE can be formed.

As the gate insulating film GOX, for example, a silicon oxide film (SiO _x ), a silicon nitride film, an aluminum oxide film, an aluminum nitride film, or the like formed by a CVD (Chemical Vapor Deposition) method or a sputtering method can be used. Here, for example, a silicon oxide film having a thickness of 100 nm formed by a CVD method is used.

The channel layer CH is formed from a metal oxide semiconductor film. For example, as the metal oxide semiconductor film, indium gallium zinc oxide (IGZO), tin zinc oxide (ZTO), zinc oxide (ZnO), or the like can be used. For forming the channel layer CH, for example, an evaporation method or a sputtering method using an indium gallium zinc oxide (IGZO) target, a tin zinc oxide (ZTO) target, or a zinc oxide (ZnO) target can be applied. For the patterning, an etching process or a lift-off process can be used. Here, for example, indium gallium zinc oxide (IGZO) with a thickness of 25 nm is formed by RF sputtering at room temperature, and then patterned using a wet etching process. As for the sputtering conditions, the pressure during film formation is, for example, 0.5 Pa (oxygen-argon mixed gas: O ₂ / Ar = 1/12), and the RF power is, for example, 50 W.

  The source electrode SE and the drain electrode DE are formed of the diffusion prevention layer DC and the first electrode layer FE. Specifically, for example, the diffusion prevention layer DC is formed of a cobalt (Co) film, and the first electrode layer FE includes an aluminum film (Al), a copper film (Cu), and a silver film (Ag) having a small specific resistance. A single layer film such as a gold film (Au), a multilayer film of these metals, or a multilayer film with a metal other than these metals can be used. The source electrode SE and the drain electrode DE configured as described above can be formed using, for example, a sputtering method or a vapor deposition method, and then patterned using an etching process or a lift-off process.

  The thin film transistor TFT1 in the first embodiment is configured as described above, and the characteristic points thereof will be described below. The feature of the first embodiment is that, as shown in FIG. 1, the source electrode SE and the drain electrode DE of the thin film transistor TFT1 are formed of the diffusion prevention layer DC and the first electrode layer FE. That is, in the first embodiment, the diffusion prevention layer DC is formed between the first electrode layer FE constituting the part of the source electrode SE and the channel layer CH so as to be in direct contact with the channel layer CH. There is a feature in the point. Similarly, in the first embodiment, the diffusion prevention layer DC is formed between the first electrode layer FE constituting the part of the drain electrode DE and the channel layer CH so as to be in direct contact with the channel layer CH. There is a feature in that. In other words, the present first embodiment is characterized in that the first electrode layer FE constituting part of each of the source electrode SE and the drain electrode DE is configured not to directly contact the channel layer CH. It can be said that there is.

  In this way, the diffusion prevention layer DC is formed between the first electrode layer FE and the channel layer CH constituting part of the source electrode SE and part of the drain electrode DE so as to be in direct contact with the channel layer CH. Explain why.

  For example, a thin film transistor is used as a switching device that controls application and non-application of a drive voltage to a pixel in order to change the alignment direction of liquid crystal present in each pixel constituting the liquid crystal display. In recent years, high definition of liquid crystal displays has been promoted, and along with the high definition of liquid crystal displays, it will be necessary to miniaturize wiring connected to thin film transistors in the future. For this reason, the current wiring materials such as molybdenum and molybdenum-tungsten alloy have insufficient conductivity, which causes problems such as signal delay in the wiring. In order to solve such a problem, it is desirable to use a metal material having a low resistance of, for example, 3 μΩ · cm or less as the source electrode SE, the drain electrode DE, and the wiring material. Examples of the low-resistance metal material include aluminum (Al), silver (Ag), gold (Au), and copper (Cu). Therefore, in the first embodiment, in order to reduce the resistance of the source electrode SE and the drain electrode DE, the source electrode SE and the drain electrode DE are made of aluminum (Al), silver (Ag), gold (Au), copper ( The first electrode layer is made of Cu) or the like.

  However, with regard to Al, Ag, Au, and Cu having low resistance values, the Al, Ag, Au, and Cu are formed by heat treatment applied after the thin film transistor is formed, such as a passivation film forming process in which a heat treatment at approximately 250 ° C. is performed. Au and Cu diffuse from the source electrode SE and the drain electrode DE to the channel layer CH in direct contact with the source electrode SE and the drain electrode DE. Then, the diffused Al, Ag, Au, and Cu are combined with oxygen contained in the metal oxide semiconductor film constituting the channel layer CH to form a metal oxide. As a result, there is a problem that the contact resistance between the source electrode SE (drain electrode DE) and the channel layer CH increases, and the TFT characteristics of the thin film transistor are deteriorated. That is, when the source electrode SE and the drain electrode DE made of aluminum (Al), silver (Ag), gold (Au), copper (Cu), etc. are brought into direct contact with the channel layer CH, they are added particularly after the thin film transistor is formed. According to the present inventors, the characteristics of the thin film transistor deteriorate due to diffusion of aluminum (Al), silver (Ag), gold (Au), copper (Cu), etc. into the channel layer CH made of a metal oxide semiconductor film due to the thermal history. Was newly found.

  Therefore, the present inventor has devised the configuration of the thin film transistor in order to solve the above-described problem. Specifically, a diffusion prevention layer DC is provided between the first electrode layer FE constituting the part of the source electrode SE and the channel layer CH so as to be in direct contact with the channel layer CH, and a part of the drain electrode DE is provided. A diffusion prevention layer DC is provided between the first electrode layer FE and the channel layer CH constituting the channel layer CH so as to be in direct contact with the channel layer CH.

  Thereby, for example, even when a thermal history of about 250 ° C. exists after the formation of the thin film transistor, aluminum (Al), silver (Ag), gold (Au), and copper (Cu) constituting the first electrode layer FE are formed. ) Or the like is suppressed by the diffusion prevention layer DC. As a result, it is possible to suppress an increase in contact resistance between the source electrode SE (drain electrode DE) and the channel layer CH, thereby obtaining a remarkable effect of suppressing deterioration of TFT characteristics of the thin film transistor. it can.

  In particular, the present inventor can use a cobalt film as a substance that effectively suppresses diffusion of aluminum (Al), silver (Ag), gold (Au), copper (Cu), etc. into the channel layer CH. I found. That is, specifically, the present inventor configures the diffusion prevention layer DC from a cobalt film, so that the aluminum (Al), silver (Ag), gold (Au), and copper (Cu) constituting the first electrode layer FE are formed. It has been found that diffusion into the channel layer CH can be effectively suppressed.

  Here, as shown in FIG. 1, the diffusion prevention layer DC is not formed over the entire source electrode SE and drain electrode DE, but is formed only in a region in direct contact with the channel layer CH. The diffusion prevention layer DC only needs to suppress diffusion of aluminum (Al), silver (Ag), gold (Au), copper (Cu), and the like constituting the first electrode layer FE into the channel layer CH. This is because the diffusion prevention layer DC may be formed so that the first electrode layer FE is not in direct contact with the channel layer CH. That is, the configuration in which the diffusion prevention layer DC is provided only in the region that is in direct contact with the channel layer CH is made of aluminum (Al), silver (Ag), gold (Au), copper (Cu), or the like constituting the first electrode layer FE. The configuration is necessary and sufficient to realize a function of suppressing diffusion to the channel layer CH.

  The reason why the diffusion prevention layer DC is formed only in the region in direct contact with the channel layer CH will be described below. That is, in the first embodiment, a cobalt film is employed as a material that performs a sufficient function as the diffusion preventing layer DC. This cobalt film is desirable from the viewpoint of suppressing diffusion of aluminum (Al), silver (Ag), gold (Au), copper (Cu), and the like constituting the first electrode layer FE into the channel layer CH. Therefore, the resistance value is higher than aluminum (Al), silver (Ag), gold (Au), copper (Cu), and the like. Therefore, when the cobalt film (diffusion prevention layer DC) is formed not only in the region directly in contact with the channel layer CH but also over the entire source electrode SE and drain electrode DE extending on the gate insulating film GOX, the source electrode SE and drain are formed. The resistance value of the electrode DE increases. That is, in the first embodiment, in order to lower the resistance value of the source electrode SE and the drain electrode DE, aluminum (Al), silver (Ag), gold (Au), and copper (Cu) whose resistance value is 3 μΩ · cm or less. From the viewpoint of reducing the resistance value of the source electrode SE and the drain electrode DE, it is preferable not to use a cobalt film. Therefore, in the first embodiment, in order to suppress diffusion of aluminum (Al), silver (Ag), gold (Au), copper (Cu), etc. constituting the first electrode layer FE into the channel layer CH. The cobalt film (diffusion prevention layer DC) is provided only in a necessary and sufficient region. That is, in the first embodiment, the source electrode SE and the drain electrode DE have a stacked structure of the cobalt film (diffusion prevention layer DC) and the first electrode layer FE in a region in direct contact with the channel layer CH. However, in the other regions, the first electrode layer FE is made of only a low resistance material such as aluminum (Al), silver (Ag), gold (Au), or copper (Cu). With this configuration, according to the first embodiment, aluminum (Al), silver (Ag), gold (Au), copper (Cu), etc. constituting the first electrode layer FE are supplied to the channel layer CH. It is possible to sufficiently suppress the diffusion and to obtain a remarkable effect that the resistance values of the source electrode SE and the drain electrode DE can be sufficiently reduced.

  As described above, in the first embodiment, a cobalt film is used as the diffusion prevention layer DC. However, according to this cobalt film, the metal constituting the first electrode layer FE is diffused into the channel layer CH. Can be suppressed. In the first embodiment, the case where the first electrode layer FE is formed from an aluminum film (Al) and the diffusion prevention layer DC is formed from a cobalt film is taken as an example, and the cobalt film sufficiently prevents the diffusion of aluminum. The result of verifying that the function is fulfilled will be described.

  Here, the thin film transistor TFT1 in which the thickness of the cobalt film is 5 nm and the aluminum film (single layer film) is 40 nm thick as the first electrode layer FE is taken as the thin film transistor TFT1 in the first embodiment. An EB vapor deposition method is used for forming the cobalt film and the aluminum film, and a lift-off method is used for patterning. The channel length (L) and the channel width (W) of the thin film transistor TFT1 are L = 100 μm and W = 2000 μm, respectively.

FIG. 2 is a graph showing initial electrical characteristics and electrical characteristics after heating at 250 ° C. in the thin film transistor TFT1 of the first embodiment. In FIG. 2, the vertical axis represents the on-current (I _on ), and the horizontal axis represents the gate voltage (Vg). Note that the voltage (V _d ) between the source electrode SE and the drain electrode DE at the time of measurement is 1.0V.

As shown in FIG. 2, the on-state current (I _on ) in the initial electrical characteristics before heating is 7.9 × 10 ⁻⁴ A, and the mobility (μ _fe ) (not shown) is 16 cm ² V ⁻¹ s. ^-1 . On the other hand, the on-state current (I _on ) in the electrical characteristics after heating at 250 ° C. is 1.1 × 10 ⁻³ A, and the mobility (μ _fe ) is 18 cm ² V ⁻¹ s ⁻¹ . The on-current (I _on ) here is a current when the gate voltage (Vg) is the threshold voltage (V _th ) + 20V. Comparing the on-current (I _on ) and mobility (μ _fe ) before and after heating at 250 ° C., the values are almost the same, and the on-current (I _on ) and movement by the heating step (thermal history) at 250 ° C. A decrease in degree (μ _fe ) was not confirmed. That is, according to the thin film transistor TFT1 in the first embodiment, it was confirmed that deterioration of the electrical characteristics of the thin film transistor TFT1 can be sufficiently suppressed even when a thermal history of, for example, about 250 ° C. is applied after the thin film transistor TFT1 is formed. .

  Next, in FIG. 3, the element distribution (In, Ga, Zn, Al, Co) of each layer of the thin film transistor TFT1 after heating at 250 ° C. was analyzed by secondary ion mass spectrometry (SIMS). It is a figure which shows a result. The horizontal axis of FIG. 3 represents the depth (nm) calculated using the sputtering rate of aluminum (Al), and the vertical axis represents the detection intensity of secondary ions in arbitrary units. In the SIMS analysis result of FIG. 3, when attention is paid to the position of the depth corresponding to the channel layer CH made of indium gallium zinc oxide (IGZO), indium (In) and zinc (which are constituent components of indium gallium zinc oxide (IGZO)) The peak of aluminum (Al) was not confirmed at a position where Zn) and gallium (Ga) had peaks. This shows that aluminum (Al) is not diffused in the channel layer CH made of indium gallium zinc oxide (IGZO). That is, the first electrode layer FE is configured by the diffusion prevention layer DC made of a cobalt film provided between the first electrode layer FE made of an aluminum film and the channel layer CH made of indium gallium zinc oxide (IGZO). It can be seen that aluminum can be prevented from diffusing into the channel layer CH. As described above, from the electrical characteristics shown in FIG. 2 and the SIMS result shown in FIG. 3, the cobalt film is present between the channel layer CH made of an aluminum film (Al) and indium gallium zinc oxide (IGZO). In the thin film transistor TFT1 in Mode 1, diffusion of aluminum (Al) into the channel layer CH made of indium gallium zinc oxide (IGZO) by heat treatment at 250 ° C. is suppressed. As a result, it was confirmed that reaction of aluminum with oxygen contained in indium gallium zinc oxide (IGZO) was suppressed, and deterioration of electrical characteristics of the thin film transistor TFT1 could be suppressed.

  Next, a comparative example for comparison with the thin film transistor TFT1 in the first embodiment described above will be described. FIG. 4 is a cross-sectional view showing the structure of the thin film transistor TFT2 in the comparative example. The structure of the thin film transistor TFT2 in the comparative example shown in FIG. 4 is substantially the same as the structure of the thin film transistor TFT1 in the first embodiment shown in FIG. 1, but the thin film transistor TFT2 in the comparative example is different from the thin film transistor TFT1 in the first embodiment. The difference is that there is no diffusion prevention layer DC.

  In FIG. 4, in the thin film transistor TFT2 in the comparative example, the gate electrode GE is formed on the insulating substrate 1S, and the gate insulating film GOX is formed on the insulating substrate 1S so as to cover the gate electrode GE. A channel layer CH is formed on the gate insulating film GOX. Then, the source electrode SE and the drain electrode DE are formed so as to be separated from each other on the channel layer CH in a plan view and to extend on the gate insulating film GOX. The source electrode SE and the drain electrode DE are composed of the first electrode layer FE made of a metal film, and the diffusion prevention layer DC is not formed.

  Here, as the thin film transistor TFT2 in the comparative example, a thin film transistor TFT2 in which an aluminum film (single layer film) having a thickness of 100 nm is used as the first electrode layer FE is taken up. An EB vapor deposition method is used for forming the aluminum film, and a lift-off method is used for patterning. The channel length (L) and the channel width (W) of the thin film transistor TFT2 are L = 300 μm and W = 2000 μm, respectively.

FIG. 5 is a graph showing initial electrical characteristics and electrical characteristics after heating at 250 ° C. in the thin film transistor TFT2 of the comparative example. In FIG. 5, the vertical axis represents the on-current (I _on ), and the horizontal axis represents the gate voltage (Vg). Note that the voltage (V _d ) between the source electrode SE and the drain electrode DE at the time of measurement is 1.0V.

As shown in FIG. 5, the on-current (I _on ) in the initial electrical characteristics before heating is 8.7 × 10 ⁻⁵ A, and the mobility (μ _fe ) (not shown) is 14 cm ² V ⁻¹ s. ^-1 . On the other hand, the on-state current (I _on ) in electrical characteristics after heating at 250 ° C. is 1.3 × 10 ⁻⁶ A, and the mobility (μ _fe ) is 1 cm ² V ⁻¹ s ⁻¹ . The on-current (I _on ) here is a current when the gate voltage (Vg) is the threshold voltage (V _th ) + 20V. Comparing the on-current (I _on ) and mobility (μ _fe ) before and after heating at 250 ° C., the on-current (I _on ) is about 1/70 and the mobility (μ _fe ) is 1/14 after heating. It turns out that it has fallen to the extent. That is, in the thin film transistor TFT2 in the comparative example, it was confirmed that the electrical characteristics of the thin film transistor TFT2 are remarkably deteriorated when a thermal history of about 250 ° C. exists after the thin film transistor TFT2 is formed.

  Next, FIG. 6 shows the result of analyzing the element distribution (In, Ga, Zn, Al) of each layer of the thin film transistor TFT2 after heating at 250 ° C. by secondary ion mass spectrometry (SIMS). FIG. The horizontal axis in FIG. 6 represents the depth (nm) calculated using the sputtering rate of aluminum (Al), and the vertical axis represents the secondary ion detection intensity in arbitrary units.

In the SIMS analysis result of FIG. 6, when attention is paid to the position of the depth corresponding to the channel layer CH made of indium gallium zinc oxide (IGZO), indium (In) or zinc (IG) that is a constituent component of indium gallium zinc oxide (IGZO). A peak of aluminum (Al) was confirmed at a position at the same depth as the position where Zn and gallium (Ga) had peaks. This shows that aluminum (Al) has diffused into the channel layer CH made of indium gallium zinc oxide (IGZO). That is, when the aluminum film (Al) is in direct contact with the channel layer CH made of indium gallium zinc oxide (IGZO) from the result of the electrical characteristics shown in FIG. 5 and the result of the SIMS analysis shown in FIG. It can be seen that aluminum (Al) diffuses into the channel layer CH made of indium gallium zinc oxide (IGZO) by the treatment. As a result, aluminum reacts with oxygen contained in indium gallium zinc oxide (IGZO), and electrical characteristics of the thin film transistor TFT2 deteriorate (decrease in on-current (I _on ) and decrease in mobility (μ _fe )). It was confirmed.

When the thin film transistor TFT1 in the first embodiment described above and the thin film transistor TFT2 in the comparative example are compared, in the thin film transistor TFT1 in the first embodiment, indium oxide in the heat treatment at about 250 ° C. confirmed in the thin film transistor TFT2 in the comparative example. Diffusion of aluminum (Al) into the channel layer CH made of gallium zinc (IGZO) has not been confirmed. In addition, in the electrical characteristics, a decrease in on-current (I _on ) and mobility (μ _fe ) was confirmed in the thin film transistor TFT2 in the comparative example, but not in the thin film transistor TFT1 in the first embodiment. From the above, like the thin film transistor TFT1 in the first embodiment, a cobalt film (diffusion prevention) is formed at the interface between the channel layer CH made of indium gallium zinc oxide (IGZO) and the first electrode layer FE made of an aluminum film (Al). By sandwiching the layer DC), diffusion of aluminum (Al) into the channel layer CH made of indium gallium zinc oxide (IGZO) can be prevented, thereby deteriorating the electrical characteristics of the thin film transistor TFT1 in the first embodiment. It confirmed that the effect which prevents was acquired.

  Note that the same results as those shown in FIGS. 2 and 3 were obtained in the thin film transistor TFT1 in which the cobalt film as the diffusion preventing layer DC was gradually increased to 100 nm. From this, if the thickness of the cobalt film existing at the interface between the indium gallium zinc oxide (IGZO) and the aluminum film (Al) is 5 nm or more and 100 nm or less, it is made of indium gallium zinc oxide (IGZO) of aluminum (Al). It was confirmed that the effect of preventing diffusion to the channel layer CH was obtained.

  In the case where a laminated film of aluminum (Al) and metal M (Al, Ag, Cu, Au, Mo, W, Mo-W, Ni, Cr, Ti, Fe, Ta) is used as the first electrode layer FE. The results similar to those shown in FIGS. 2 and 3 were obtained, and it was confirmed that the effect of preventing diffusion of metal elements into indium gallium zinc oxide (IGZO) was obtained.

  Further, in the verification described above, an example in which the channel layer CH is formed from indium gallium zinc oxide (IGZO) has been described. However, the present invention is not limited thereto, and the channel layer CH is formed from tin zinc oxide (ZTO) or zinc oxide (ZnO). In this case, the diffusion of aluminum (Al) into the channel layer CH is prevented by sandwiching the cobalt film (diffusion prevention layer DC) at the interface between the channel layer CH and the first electrode layer FE made of the aluminum film (Al). It was confirmed that the effect of preventing the deterioration of the electrical characteristics of the thin film transistor TFT1 can be obtained.

Specifically, FIG. 7 shows the on-state when tin oxide (ZTO) or zinc oxide (ZnO) is used for both channel layers CH of the thin film transistor TFT1 in the first embodiment and the thin film transistor TFT2 in the comparative example. It is a figure which shows electric current ( _Ion ). As shown in FIG. 7, in any case where zinc oxide (ZTO) or zinc oxide (ZnO) is used for the channel layer CH, the thin film transistor TFT1 in the first embodiment is more on than the thin film transistor TFT2 in the comparative example. It was confirmed that the current (I _on ) increased. Therefore, even when the channel layer CH is formed of tin zinc oxide (ZTO) or zinc oxide (ZnO), a cobalt film (diffusion prevention layer DC) is formed at the interface between the channel layer CH and the first electrode layer FE made of an aluminum film (Al). ) Can be prevented from diffusing into the channel layer CH of aluminum (Al), thereby preventing the deterioration of the electrical characteristics (on-current (I _on )) of the thin film transistor TFT1 in the first embodiment. It can be seen that

  The structure of the thin film transistor TFT1 shown in FIG. 1 is that the gate electrode GE is formed in the lower layer of the channel layer CH, and the source electrode SE and the drain electrode DE to be contacted are formed in the upper layer of the channel layer CH. This is called a gate / top contact type structure.

In the first embodiment, the thin film transistor TFT1 having the bottom gate / top contact type structure has been described. However, the bottom gate / bottom contact type structure, the top gate / top contact type structure, and the top gate / bottom contact type structure are also used for the channel. By interposing the cobalt film (diffusion prevention layer DC) at the interface between the layer CH and the first electrode layer FE made of the aluminum film (Al), diffusion of aluminum (Al) into the channel layer CH can be prevented, thereby The effect of preventing the deterioration of the electrical characteristics (on-current (I _on )) of the thin film transistor TFT1 can be obtained.

  Specifically, FIG. 8 is a cross-sectional view showing a thin film transistor TFT1 having a bottom gate / bottom contact type structure. As shown in FIG. 8, the bottom gate / bottom contact type thin film transistor TFT1 has a gate electrode GE on an insulating substrate 1S, and a gate insulating film GOX on the insulating film 1S covering the gate electrode GE. The bottom gate / bottom contact type thin film transistor TFT1 is arranged on the gate insulating film GOX so as to be spaced apart in a plane, and the source electrode SE and the source electrode SE arranged so as to extend on the gate insulating film GOX, respectively. It has a drain electrode DE, and has a channel layer CH formed so as to run over the end portion of the source electrode SE and the end portion of the drain electrode DE from the gate insulating film GOX between the source electrode SE and the drain electrode DE. According to the thin film transistor TFT1 shown in FIG. 8 configured as described above, since the gate electrode GE, the source electrode SE, and the drain electrode DE are formed below the channel layer CH, the thin film transistor having the bottom gate / bottom contact type structure. It is called TFT1.

The bottom gate / bottom contact type thin film transistor TFT1 is also configured to sandwich a cobalt film (diffusion prevention layer DC) at the interface between the channel layer CH and the first electrode layer FE made of an aluminum film (Al). For this reason, diffusion of aluminum (Al) into the channel layer CH can be prevented, thereby obtaining an effect of preventing deterioration of the electrical characteristics (on current (I _on )) of the thin film transistor TFT1.

  Next, FIG. 9 is a cross-sectional view showing a thin film transistor TFT1 having a top gate / top contact type structure. As shown in FIG. 9, a thin film transistor TFT1 having a top gate / top contact type structure has a channel layer CH on an insulating substrate 1S, and is disposed on the channel layer CH so as to be spaced apart in a plane, and is insulated from each other. A source electrode SE and a drain electrode DE extending on the substrate 1S are provided. The thin film transistor TFT1 having a top gate / top contact structure has a gate formed so as to run from the channel layer CH between the source electrode SE and the drain electrode DE to the end of the source electrode SE and the end of the drain electrode DE. It has an insulating film GOX, and further has a gate electrode GE formed on the gate insulating film GOX. According to the thin film transistor TFT1 shown in FIG. 9 configured as described above, the gate electrode GE, the source electrode SE, and the drain electrode DE are formed on the channel layer CH, so that the thin film transistor having a top gate / top contact type structure is formed. It is called TFT1.

The thin film transistor TFT1 having the top gate / top contact structure is also configured such that a cobalt film (diffusion prevention layer DC) is sandwiched between the interface of the channel layer CH and the first electrode layer FE made of an aluminum film (Al). For this reason, diffusion of aluminum (Al) into the channel layer CH can be prevented, thereby obtaining an effect of preventing deterioration of the electrical characteristics (on current (I _on )) of the thin film transistor TFT1.

  Next, FIG. 10 is a cross-sectional view showing a thin film transistor TFT1 having a top gate / bottom contact type structure. As shown in FIG. 10, the thin film transistor TFT1 having a top gate / bottom contact type structure is disposed on the insulating substrate 1S so as to be spaced apart in a plane, and the source electrode SE and the drain electrode respectively extending on the insulating substrate 1S. Has DE. The thin film transistor TFT1 having a top gate / bottom contact type structure is a channel formed so as to run from the insulating substrate 1S between the source electrode SE and the drain electrode DE to the end of the source electrode SE and the end of the drain electrode DE. It has a layer CH and a gate insulating film GOX formed on the channel layer CH. Further, the thin film transistor TFT1 having a top gate / bottom contact type structure includes a gate electrode GE on the gate insulating film GOX. According to the thin film transistor TFT1 shown in FIG. 10 configured as described above, the gate electrode GE is formed in the upper layer of the channel layer CH, and the source electrode SE and the drain electrode DE are formed in the lower layer of the channel layer CH. It is called a thin film transistor TFT1 having a top gate / bottom contact type structure.

The thin film transistor TFT1 having the top gate / bottom contact type structure is also configured such that a cobalt film (diffusion prevention layer DC) is sandwiched between the interface of the channel layer CH and the first electrode layer FE made of an aluminum film (Al). For this reason, diffusion of aluminum (Al) into the channel layer CH can be prevented, thereby obtaining an effect of preventing deterioration of the electrical characteristics (on current (I _on )) of the thin film transistor TFT1.

(Embodiment 2)
The structure of the thin film transistor TFT1 in the second embodiment will be described with reference to FIG. The thin film transistor TFT1 in the second embodiment has the same structure as the thin film transistor TFT1 in the first embodiment except that the material constituting the first electrode layer FE is changed from aluminum (Al) to copper (Cu). .

  As in the first embodiment, the thin film transistor TFT1 in the second embodiment in which the cobalt film (diffusion prevention layer DC) has a thickness of 5 nm and the first electrode layer FE has a copper film (Cu) of 40 nm, and The copper film (Cu) having a thickness of 100 nm is used as the first electrode layer FE without using the cobalt film (diffusion prevention layer DC), and the first electrode layer FE made of the copper film (Cu) is in direct contact with the channel layer CH. A thin film transistor TFT2 in a comparative example was produced as a structure to be used.

In the thin film transistor TFT1 in Embodiment 2, the initial electrical characteristics and the electrical characteristics after the heat treatment at 250 ° C. show the same results as in FIG. 2, and the on-current (I _on ) before and after the heat treatment at 250 ° C. and No decrease in mobility (μ _fe ) was observed.

  Next, FIG. 11 is a diagram showing a result of SIMS analysis of element distribution (In, Zn, Ga, Cu, Co) in each layer of the thin film transistor TFT1 in the second embodiment after the heat treatment at 250 ° C. In FIG. 11, the horizontal axis indicates the depth (nm) converted using the copper (Cu) sputtering rate, and the vertical axis indicates the detection intensity (arbitrary unit) of the secondary ions. Focusing on the position of the depth corresponding to the channel layer CH made of indium gallium zinc oxide (IGZO), indium (In), zinc (Zn), and gallium (Ga), which are constituent components of indium gallium zinc oxide (IGZO), are used. Since the peak of copper (Cu) cannot be confirmed at the depth position where the peak exists, it was confirmed that copper (Cu) was not diffused in the channel layer CH made of indium gallium zinc oxide (IGZO).

Then, electrical characteristics after heat treatment of the initial electric characteristics of the thin film transistor TFT2 and 250 ° C. in Comparative Example, similarly to the case of FIG. 5, the on-current by a heat treatment at about 250 ℃ _{(I on)} of about 1/70, mobility (Μ _fe ) was reduced to about 1/14. Furthermore, as a result of analyzing the element distribution (In, Zn, Ga, Cu) in each layer of the thin film transistor TFT2 in the comparative example by SIMS, indium (In) which is a constituent component of indium gallium zinc oxide (IGZO) as in FIG. The peak of the spectrum of copper (Cu) was detected at the same depth as the spectrum of gallium (Ga), zinc (Zn) and the like. From such electrical characteristics and SIMS analysis results, when the copper (Cu) is in direct contact with the channel layer CH made of indium gallium zinc oxide (IGZO) as in the thin film transistor TFT2 in the comparative example, the heat treatment is performed at 250 ° C. Copper (Cu) diffused into the channel layer CH made of indium gallium zinc oxide (IGZO), and the on-current (I _on ) and mobility (μ _fe ) of the thin film transistor TFT2 in the comparative example were reduced.

When the thin film transistor TFT1 in the second embodiment described above and the thin film transistor TFT2 in the comparative example are compared, in the thin film transistor TFT1 in the second embodiment, indium oxide in the heat treatment at about 250 ° C. confirmed in the thin film transistor TFT2 in the comparative example. Diffusion of copper (Cu) into the channel layer CH made of gallium zinc (IGZO) has not been confirmed. In addition, in the electrical characteristics, a decrease in on-current (I _on ) and mobility (μ _fe ) was confirmed in the thin film transistor TFT2 in the comparative example, but not in the thin film transistor TFT1 in the second embodiment. From the above, like the thin film transistor TFT1 in the second embodiment, a cobalt film (diffusion prevention) is formed at the interface between the channel layer CH made of indium gallium zinc oxide (IGZO) and the first electrode layer FE made of copper film (Cu). By sandwiching the layer DC), diffusion of copper (Cu) into the channel layer CH made of indium gallium zinc oxide (IGZO) can be prevented, thereby deteriorating the electrical characteristics of the thin film transistor TFT1 in the second embodiment. It confirmed that the effect which prevents was acquired.

  Note that the same results as those shown in FIGS. 2 and 3 were obtained in the thin film transistor TFT1 in which the cobalt film as the diffusion preventing layer DC was gradually increased to 100 nm. From this, if the thickness of the cobalt film present at the interface between indium gallium zinc oxide (IGZO) and the copper film (Cu) is 5 nm or more and 100 nm or less, it is made of indium gallium zinc oxide (IGZO) of copper (Cu). It was confirmed that the effect of preventing diffusion to the channel layer CH was obtained.

  Further, even when a laminated film of copper (Cu) and metal M is used as the first electrode layer FE, the same results as those shown in FIGS. 2 and 3 are obtained, and indium gallium zinc oxide (IGZO) is obtained. It was confirmed that the effect of preventing the diffusion of metal elements into the metal was obtained.

  Further, in the verification described above, an example in which the channel layer CH is formed from indium gallium zinc oxide (IGZO) has been described. However, the present invention is not limited thereto, and the channel layer CH is formed from tin zinc oxide (ZTO) or zinc oxide (ZnO). In this case, the diffusion of copper (Cu) into the channel layer CH is prevented by sandwiching the cobalt film (diffusion prevention layer DC) at the interface between the channel layer CH and the first electrode layer FE made of the copper film (Cu). It was confirmed that the effect of preventing the deterioration of the electrical characteristics of the thin film transistor TFT1 can be obtained.

In the second embodiment, the thin film transistor TFT1 having the bottom gate / top contact type structure has been described. However, the bottom gate / bottom contact type structure, the top gate / top contact type structure, and the top gate / bottom contact type structure are also used for the channel. By interposing the cobalt film (diffusion prevention layer DC) at the interface between the layer CH and the first electrode layer FE made of the copper film (Cu), diffusion of copper (Cu) into the channel layer CH can be prevented, thereby The effect of preventing the deterioration of the electrical characteristics (on-current (I _on )) of the thin film transistor TFT1 can be obtained.

(Embodiment 3)
A structure of the thin film transistor TFT1 in the third embodiment will be described with reference to FIG. The thin film transistor TFT1 in the third embodiment is the same as the thin film transistor TFT1 in the first embodiment except that the material constituting the first electrode layer FE is changed from aluminum (Al) to silver (Ag) or gold (Au). Has a structure.

  As in the first embodiment, the cobalt film (diffusion prevention layer DC) is 5 nm thick, and the first electrode layer FE is a 40 nm thick silver film (Ag) or gold film (Au). The thin film transistor TFT1 in FIG. 3 and the cobalt film (diffusion prevention layer DC) are not used, but a silver film (Ag) or a gold film (Au) with a thickness of 100 nm is used as the first electrode layer FE, The thin film transistor TFT2 in the comparative example was fabricated as a structure in which the first electrode layer FE made of a film (Au) was in direct contact with the channel layer CH.

In the thin film transistor TFT1 in Embodiment 3, the initial electrical characteristics and the electrical characteristics after the heat treatment at 250 ° C. show the same results as in FIG. 2, and the on-current (I _on ) before and after the heat treatment at 250 ° C. and No decrease in mobility (μ _fe ) was observed.

  Further, the SIMS analysis results of the element distribution (In, Zn, Ga, Ag (Au), Co) in each layer after the heat treatment at 250 ° C. show the same results as in FIG. 3, and indium gallium zinc oxide (IGZO) Diffusion of silver (Ag) or gold (Au) into the channel layer CH made of was not confirmed.

Then, electrical characteristics after heat treatment of the initial electric characteristics of the thin film transistor TFT2 and 250 ° C. in Comparative Example, similarly to the case of FIG. 5, the on-current by a heat treatment at about 250 ℃ _{(I on)} of about 1/70, mobility (Μ _fe ) was reduced to about 1/14. Furthermore, as a result of analyzing the element distribution (In, Zn, Ga, Ag (Au)) in each layer of the thin film transistor TFT2 in the comparative example by SIMS, indium which is a constituent component of indium gallium zinc oxide (IGZO) as in FIG. The peak of the spectrum of silver (Ag) or gold (Au) was detected at the same depth as the spectrum of (In), gallium (Ga), zinc (Zn), or the like. From the results of such electrical characteristics and SIMS analysis, when the silver (Ag) or gold (Au) is in direct contact with the channel layer CH made of indium gallium zinc oxide (IGZO) as in the thin film transistor TFT2 in the comparative example, 250 Silver (Ag) or gold (Au) is diffused into the channel layer CH made of indium gallium zinc oxide (IGZO) by heat treatment at 0 ° C., and the on-current (I _on ) and mobility (μ _fe ) of the thin film transistor TFT2 in the comparative example ) Was reduced.

When the thin film transistor TFT1 in the third embodiment described above and the thin film transistor TFT2 in the comparative example are compared, in the thin film transistor TFT1 in the third embodiment, indium oxide in the heat treatment at about 250 ° C. confirmed in the thin film transistor TFT2 in the comparative example. Diffusion of silver (Ag) or gold (Au) into the channel layer CH made of gallium zinc (IGZO) has not been confirmed. In addition, in the electrical characteristics, a decrease in on-current (I _on ) and mobility (μ _fe ) was confirmed in the thin film transistor TFT2 in the comparative example, but not in the thin film transistor TFT1 in the third embodiment. From the above, like the thin film transistor TFT1 in the third embodiment, the channel layer CH made of indium gallium zinc oxide (IGZO) and the first electrode layer FE made of a silver film (Ag) or a gold film (Au). By sandwiching the cobalt film (diffusion prevention layer DC) at the interface, diffusion of silver (Ag) or gold (Au) into the channel layer CH made of indium gallium zinc oxide (IGZO) can be prevented. It was confirmed that the effect of preventing the deterioration of the electrical characteristics of the thin film transistor TFT1 in Embodiment 3 was obtained.

  Note that the same results as those shown in FIGS. 2 and 3 were obtained in the thin film transistor TFT1 in which the cobalt film as the diffusion preventing layer DC was gradually increased to 100 nm. From this, if the thickness of the cobalt film present at the interface between indium gallium zinc oxide (IGZO) and the silver film (Ag) or gold film (Au) is 5 nm or more and 100 nm or less, silver (Ag) or gold ( It was confirmed that an effect of preventing diffusion of Au) into the channel layer CH made of indium gallium zinc oxide (IGZO) was obtained.

  In addition, when a laminated film of silver (Ag) and metal M or gold (Au) and metal M is used as the first electrode layer FE, the same results as those shown in FIGS. 2 and 3 are obtained. It was confirmed that the effect of preventing diffusion of metal elements into indium gallium zinc oxide (IGZO) was obtained.

  Further, in the verification described above, an example in which the channel layer CH is formed from indium gallium zinc oxide (IGZO) has been described. However, the present invention is not limited thereto, and the channel layer CH is formed from tin zinc oxide (ZTO) or zinc oxide (ZnO). In this case, the cobalt film (diffusion prevention layer DC) is sandwiched between the channel layer CH and the first electrode layer FE made of a silver film (Ag) or a gold film (Au), so that silver (Ag) or gold ( It was confirmed that the diffusion of Au) into the channel layer CH can be prevented, thereby obtaining the effect of preventing the deterioration of the electrical characteristics of the thin film transistor TFT1.

In the third embodiment, the bottom gate / top contact type thin film transistor TFT1 has been described. However, the bottom gate / bottom contact type structure, the top gate / top contact type structure, and the top gate / bottom contact type structure also apply to the channel. A channel layer of silver (Ag) or gold (Au) is formed by sandwiching a cobalt film (diffusion prevention layer DC) between the interface of the layer CH and the first electrode layer FE made of a silver film (Ag) or a gold film (Au). Diffusion to CH can be prevented, thereby obtaining an effect of preventing deterioration of the electrical characteristics (on-current (I _on )) of the thin film transistor TFT1.

(Embodiment 4)
In the fourth embodiment, an example in which the thin film transistor TFT1 described in the first to third embodiments is applied to an active matrix liquid crystal display device will be described.

  FIG. 12 is a plan view showing a TFT array constituting the active matrix liquid crystal display device in the fourth embodiment. In FIG. 12, in the TFT array, the data line DL and the gate line GL are arranged so as to be orthogonal to each other, and an insulating film IF for preventing a short circuit between the data line DL and the gate line GL is formed at the intersection. Is formed. A pixel electrode PE is formed in each array-like region partitioned by a plurality of data lines DL and gate lines GL. A thin film transistor TFT1 is provided corresponding to the plurality of pixel electrodes PE, and a gate electrode of the thin film transistor TFT1 is electrically connected to the gate wiring GL. Further, the source electrode of the thin film transistor TFT1 is electrically connected to the data line DL, and the drain electrode of the thin film transistor TFT1 is electrically connected to the pixel electrode PE.

  When an on voltage is applied to the gate wiring GL described above, the thin film transistor TFT1 is turned on, and a driving voltage is supplied to the pixel electrode PE through the thin film transistor TFT1 that is turned on.

  Next, a cross-sectional structure of the thin film transistor TFT1 used in the active matrix liquid crystal display device according to the fourth embodiment will be described. FIG. 13 is a cross-sectional view showing a cross-sectional structure of the thin film transistor TFT1 used in the fourth embodiment. As shown in FIG. 13, first, the gate electrode GE is formed on the insulating substrate 1S, and the gate insulating film GOX is formed on the insulating substrate 1S so as to cover the gate electrode GE. A channel layer CH is formed on the gate insulating film GOX. Then, the source electrode SE and the drain electrode DE are formed so as to be separated from each other on the channel layer CH in a plan view and to extend on the gate insulating film GOX. The source electrode SE and the drain electrode DE include the first electrode layer FE made of a metal film, and the channel layer CH and the first electrode so as to prevent the metal constituting the first electrode layer FE from diffusing into the channel layer CH. The diffusion prevention layer DC is formed between the layers FE so as to be in direct contact with the channel layer CH. At this time, the first electrode layer FE is, for example, a single layer film such as an aluminum film (Al), a copper film (Cu), a silver film (Ag), or a gold film (Au) having a small specific resistance, or a multilayer of these metals. The film is formed from a film or a multilayer film with a metal other than these metals, and the diffusion prevention layer DC is formed from, for example, a cobalt film (Co).

  As described above, the passivation film PAS is formed so as to cover the thin film transistor TFT1 formed on the insulating substrate 1S. A contact hole CNT is formed through the passivation film PAS so as to reach the source electrode SE and the drain electrode DE of the thin film transistor TFT1. In this contact hole CNT, a plug PLG is formed by embedding a wiring material made of an aluminum film (Al), a copper film (Cu), a silver film (Ag), a gold film (Au) or the like having a small specific resistance. . Further, a wiring L1 is formed on the passivation film PAS on which the plug PLG is formed, and a diffusion prevention layer DC2 is formed in a region sandwiched between the wiring L1 and the plug PLG.

  The passivation film PAS is formed of, for example, a silicon nitride film (SiNx), and can be formed by, for example, a plasma CVD method at about 250 ° C. Therefore, after the thin film transistor TFT1 is formed on the insulating substrate 1S, a thermal history of about 250 ° C. exists. However, in the thin film transistor TFT1 according to the fourth embodiment, for example, since the diffusion prevention layer DC made of a cobalt film is provided, even if a thermal history of about 250 ° C. exists after the formation of the thin film transistor TFT1, the first Diffusion prevention layer DC suppresses the diffusion of aluminum (Al), silver (Ag), gold (Au), copper (Cu), and the like constituting electrode layer FE into channel layer CH. As a result, an increase in contact resistance between the source electrode SE (drain electrode DE) and the channel layer CH can be suppressed, and thereby deterioration of the electrical characteristics of the thin film transistor TFT1 can be suppressed. Therefore, when the above-described thin film transistor TFT1 is used in an active matrix type liquid crystal display device, good switching characteristics can be obtained.

  In the fourth embodiment, as shown in FIG. 13, the diffusion prevention layer DC2 is provided at the connection portion between the plug PLG and the wiring L1. The reason for this will be described. For example, the wiring L1 is a pixel electrode PE, and an ITO electrode that is a metal oxide transparent conductor film is used for the pixel electrode PE (wiring L1). When this ITO electrode is brought into direct contact with aluminum (Al), silver (Ag), gold (Au), copper (Cu), or the like constituting the plug PLG, the aluminum (Al ), Silver (Ag), gold (Au), copper (Cu), and the like diffuse into the ITO electrode and combine with oxygen contained in the ITO electrode to form a metal oxide. As a result, the resistance of the connecting portion between the plug PLG and the ITO electrode (wiring L1) is increased. In other words, also in the connection portion between the ITO electrode and the plug PLG, diffusion to the channel layer CH such as aluminum (Al), silver (Ag), gold (Au), and copper (Cu) constituting the first electrode layer FE Similar problems arise. Therefore, in the fourth embodiment, a diffusion prevention layer DC2 made of, for example, a cobalt film is provided at a connection portion between the plug PLG and the wiring L1 (ITO electrode). Thereby, even when a thermal history of about 250 ° C. exists after the formation of the wiring L1 (ITO electrode), aluminum (Al), silver (Ag), gold (Au), and copper (Cu) constituting the plug PLG. ) And the like to the wiring L1 (ITO electrode) is suppressed by the diffusion preventing layer DC2. As a result, it is possible to suppress an increase in resistance of the connection portion between the plug PLG and the wiring L1 (ITO electrode).

(Embodiment 5)
In the fifth embodiment, an example in which the technical idea of the present invention is applied to a thin film memory will be described. FIG. 14 is a plan view showing a memory cell array in which the thin film memories according to the fifth embodiment are arranged in an array. As shown in FIG. 14, the source line SL and the bit line BL are arranged in parallel with each other, and the gate line GL is arranged so as to be orthogonal to the source line SL and the bit line BL extending in parallel. Yes. An insulating film IF for preventing a short circuit between the source line SL and the gate line GL and a short circuit between the bit line BL and the gate line GL is formed. A thin film memory TFM1 is formed in each cell region between the source line SL and the bit line BL. The source electrode of the thin film memory TFM1 is electrically connected to the source line SL, and the gate electrode of the thin film memory TFM1. Are electrically connected to the gate wiring GL.

  Next, a cross-sectional structure of the thin film memory TFM1 in the fifth embodiment will be described. FIG. 15 is a cross-sectional view showing a cross-sectional structure of thin film memory TFM1 in the fifth embodiment. As shown in FIG. 15, first, the gate electrode GE is formed on the insulating substrate 1S, and the gate insulating film GOX is formed on the insulating substrate 1S so as to cover the gate electrode GE. A channel layer CH is formed on the gate insulating film GOX. Then, the source electrode SE and the drain electrode DE are formed so as to be separated from each other on the channel layer CH in a plan view and to extend on the gate insulating film GOX. The source electrode SE and the drain electrode DE include the first electrode layer FE made of a metal film, and the channel layer CH and the first electrode so as to prevent the metal constituting the first electrode layer FE from diffusing into the channel layer CH. The diffusion prevention layer DC is formed between the layers FE so as to be in direct contact with the channel layer CH. At this time, the first electrode layer FE is, for example, a single layer film such as an aluminum film (Al), a copper film (Cu), a silver film (Ag), or a gold film (Au) having a small specific resistance, or a multilayer of these metals. The film is formed from a film or a multilayer film with a metal other than these metals, and the diffusion prevention layer DC is formed from, for example, a cobalt film (Co). A breakdown insulating layer IL is formed from the channel layer CH between the source electrode SE and the drain electrode DE to the source electrode SE and the drain electrode DE. An opening is formed in the destructive insulating layer IL, and the source electrode SE and the source wiring SL are electrically connected by filling the opening with a conductive material. On the other hand, the bit line BL is disposed on the drain electrode DE via the destructive insulating film IL.

  In the thin film memory TFM1 configured as described above, information is stored depending on whether or not the breakdown insulation layer IL formed between the bit line BL and the drain electrode DE is broken down. That is, for example, when information “1” is stored in the thin film memory TFM1, a high voltage is applied between the bit line BL and the drain electrode DE, and the destructive insulation formed between the bit line BL and the drain electrode DE. Break down the layer IL. Thus, once the breakdown insulating layer IL is broken down, a conductive path is formed between the bit line BL and the drain electrode DE. As a result, when a potential difference is applied between the source line SL and the bit line BL, a current flows through the thin film memory TFM1.

  On the other hand, when information “0” is stored in the thin film memory TFM1, the state in which the breakdown insulating layer IL formed between the bit line BL and the drain electrode DE is not broken down is maintained. In this case, since no conductive path is formed between the bit line BL and the drain electrode DE, no current flows through the thin film memory TFM1 even if a potential difference is applied between the source line SL and the bit line BL. As described above, the information “1” and the information “0” can be stored in the thin film memory TFM1 depending on the presence or absence of the current flowing through the thin film memory TFM1.

Next, a method for manufacturing the above-described thin film memory TFM1 will be briefly described. A quartz substrate is used as the insulating substrate 1S, and a molybdenum film (Mo) is formed with a thickness of 100 nm on the insulating substrate 1S by using, for example, EB vapor deposition. Then, the gate electrode GE is formed by patterning by RIE etching. Next, a gate insulating film GOX is formed on the insulating substrate 1S covering the gate electrode GE by forming a silicon oxide film (SiO ₂ ) using, for example, a CVD method. Subsequently, the channel layer CH (25 nm) made of indium gallium zinc oxide (IGZO) is subjected to a pressure of 0.5 Pa (oxygen-argon mixed gas: O ₂ / Ar = 1/12) at the time of film formation and an RF power of 50 W. Form with. Then, the diffusion prevention layer DC and the first electrode layer FE are sequentially formed over the channel layer CH and the gate insulating film GOX, and the formed diffusion prevention layer DC and the first electrode layer FE are sequentially formed using a mask. Patterning is performed by etching, and the source electrode SE and the drain electrode DE are formed. At this time, a cobalt film (Co) is used for the diffusion prevention layer DC, and an aluminum film (Al) is used for the first electrode layer FE. Thereafter, a destructive insulating layer IL made of a silicon oxide film is formed from the channel layer CH exposed between the source electrode SE and the drain electrode DE to the source electrode SE and the drain electrode DE. The destructive insulating layer IL can be formed with a thickness of 10 nm by, for example, a CVD method at about 250 ° C. Thereafter, an opening serving as an electrode extraction hole is formed in the destructive insulating layer IL on the source electrode SE, and then the source line SL and the bit line BL are formed. As described above, the thin film memory TFM1 in the fifth embodiment can be formed.

  As described above, in the manufacturing process of the thin film memory, after forming the channel layer CH, the source electrode SE, and the drain electrode, there is a heating process of about 250 ° C. as in the process of forming the destructive insulating layer IL, for example. become. However, in the thin film memory TFM1 according to the fifth embodiment, for example, the diffusion prevention layer DC made of a cobalt film is provided. Even if it exists, the diffusion to the channel layer CH of aluminum (Al) or the like constituting the first electrode layer FE is suppressed by the diffusion prevention layer DC made of a cobalt film. As a result, it is possible to suppress an increase in contact resistance between the source electrode SE (drain electrode DE) and the channel layer CH, thereby suppressing deterioration in electrical characteristics of the thin film memory TFM1.

(Embodiment 6)
In the sixth embodiment, an RFID tag using the thin film transistor TFT1 described in the first to third embodiments and the thin film memory TFM1 described in the fifth embodiment will be described. FIG. 16 is a block diagram showing a configuration of the RFID tag according to the sixth embodiment. As shown in FIG. 16, the RFID tag in the sixth embodiment includes an antenna unit ANT, a rectifier circuit RC, a digital circuit DGC, and a memory circuit MC. The RFID tag configured as described above exchanges transmission / reception signals having a frequency of 13.56 MHz with the reader / writer R / W, for example. For example, a transmission signal transmitted from the reader / writer R / W is received by the antenna unit ANT of the RFID tag and then converted into a DC signal by the rectifier circuit RC. Thereafter, the DC signal converted by the rectifier circuit RC is processed by the digital circuit DGC, and the result processed by the digital circuit DGC is stored in the memory circuit MC. In this way, information can be written to the RFID tag by the reader / writer R / W. On the other hand, in order to read the information stored in the RFID tag, the digital circuit DGC accesses the memory circuit MC to extract the information stored in the memory circuit MC, and then superimposes a signal for this information on the carrier wave. Transmit from the antenna unit ANT. The transmitted signal is received by the reader / writer R / W and information stored in the RFID tag is read out.

  In the sixth embodiment, the above-described RFID tag antenna portion ANT is formed of a transparent conductive film made of ITO. Further, the thin film transistor TFT1 described in the first to third embodiments is used for the rectifier circuit RC, and the thin film memory TFM1 described in the fourth embodiment is applied to the memory circuit MC. As a result, in the RFID tag in the sixth embodiment, deterioration of the electrical characteristics of the thin film transistor TFT1 used in the rectifier circuit RC and the electrical characteristics of the thin film memory MC used in the memory circuit MC is suppressed. Therefore, the characteristics of the RFID tag can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

1S Insulating substrate ANT Antenna part BL Bit wiring CH Channel layer CNT Contact hole DC Diffusion prevention layer DC2 Diffusion prevention layer DE Drain electrode DGC Digital circuit DL Data wiring FE First electrode layer GE Gate electrode GL Gate wiring GOX Gate insulating film IF Insulating film IL breakdown insulating layer L1 wiring MC memory circuit PAS passivation film PE pixel electrode PLG plug RC rectifier circuit R / W reader / writer SE source electrode SL source wiring TFM1 thin film memory TFT1 thin film transistor TFT2 thin film transistor

Claims (10)

A semiconductor device including a field effect transistor formed on an insulating substrate,
The field effect transistor is
(A) a source electrode and a drain electrode formed apart from each other;
(B) a channel layer made of a metal oxide semiconductor film formed between the source electrode and the drain electrode and formed in contact with each of the source electrode and the drain electrode;
(C) a gate insulating film formed in contact with the channel layer;
(D) a gate electrode formed so as to be in contact with the gate insulating film;
The source electrode and the drain electrode are
(A1) a first electrode layer made of a metal film;
(A2) It is formed between the channel layer and the first electrode layer so as to be in direct contact with the channel layer so as to prevent the metal constituting the first electrode layer from diffusing into the channel layer. A semiconductor device comprising a diffusion prevention layer. The semiconductor device according to claim 1,
The field effect transistor is
The gate electrode formed on the insulating substrate;
The gate insulating film formed on the insulating substrate so as to cover the gate electrode;
The channel layer made of the metal oxide semiconductor film formed on the gate insulating film;
A semiconductor device comprising: the source electrode and the drain electrode formed on the channel layer so as to be spaced apart from each other and extending on the gate insulating film. The semiconductor device according to claim 1,
The field effect transistor is
The gate electrode formed on the insulating substrate;
The gate insulating film formed on the insulating substrate so as to cover the gate electrode;
The source electrode and the drain electrode formed on the gate insulating film so as to be spaced apart from each other and extending on the gate insulating film,
The channel layer made of the metal oxide semiconductor film formed on the gate insulating film between the source electrode and the drain electrode so as to run over an end portion of the source electrode and an end portion of the drain electrode. A semiconductor device comprising: The semiconductor device according to claim 1,
The field effect transistor is
The channel layer made of the metal oxide semiconductor film formed on the insulating substrate;
The source electrode and the drain electrode formed on the channel layer so as to be spaced apart from each other and extending on the insulating film,
The gate insulating film formed so as to run from the channel layer between the source electrode and the drain electrode to an end portion of the source electrode and an end portion of the drain electrode;
A semiconductor device comprising: the gate electrode formed on the gate insulating film. The semiconductor device according to claim 1,
The field effect transistor is
The source electrode and the drain electrode formed on the insulating substrate so as to be spaced apart in a plane;
The channel layer made of the metal oxide semiconductor film formed so as to run over the end portion of the source electrode and the end portion of the drain electrode from the insulating substrate between the source electrode and the drain electrode;
The gate insulating film formed on the channel layer;
A semiconductor device comprising: the gate electrode formed on the gate insulating film. The semiconductor device according to claim 1,
The diffusion preventing layer is formed of a cobalt film. The semiconductor device according to claim 6,
The semiconductor device, wherein the first electrode layer is formed of a film containing any of aluminum (Al), copper (Cu), silver (Ag), or gold (Au). The semiconductor device according to claim 7,
The diffusion prevention layer has a thickness of 5 nm to 100 nm. 9. The semiconductor device according to claim 8, wherein
The channel layer is formed of a film containing at least one element selected from indium (In), gallium (Ga), zinc (Zn), and tin (Sn). The semiconductor device according to claim 9,
The semiconductor device is used for an active matrix liquid crystal display, a thin film memory, or an RFID tag.

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