CN106098559A - A kind of preparation method of bottom gate coplanar type metal oxide thin-film transistor - Google Patents
A kind of preparation method of bottom gate coplanar type metal oxide thin-film transistor Download PDFInfo
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 48
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 45
- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 239000010409 thin film Substances 0.000 title claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 41
- 238000001259 photo etching Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 32
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 31
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 25
- 238000000137 annealing Methods 0.000 claims abstract description 25
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 25
- 239000010936 titanium Substances 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 156
- 238000002161 passivation Methods 0.000 claims description 37
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 239000003989 dielectric material Substances 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 239000004411 aluminium Substances 0.000 claims description 8
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 239000002356 single layer Substances 0.000 claims description 5
- 229910000838 Al alloy Inorganic materials 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 32
- 230000007704 transition Effects 0.000 abstract description 15
- 230000008569 process Effects 0.000 abstract description 10
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 27
- 238000010586 diagram Methods 0.000 description 22
- 238000004528 spin coating Methods 0.000 description 13
- 238000004140 cleaning Methods 0.000 description 10
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 9
- 238000001755 magnetron sputter deposition Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 5
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 5
- 229910052738 indium Inorganic materials 0.000 description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 5
- 229910052725 zinc Inorganic materials 0.000 description 5
- 239000011701 zinc Substances 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 238000005546 reactive sputtering Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052593 corundum Inorganic materials 0.000 description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- -1 polyethylene terephthalate Polymers 0.000 description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- GZCWPZJOEIAXRU-UHFFFAOYSA-N tin zinc Chemical compound [Zn].[Sn] GZCWPZJOEIAXRU-UHFFFAOYSA-N 0.000 description 2
- QHGNHLZPVBIIPX-UHFFFAOYSA-N tin(II) oxide Inorganic materials [Sn]=O QHGNHLZPVBIIPX-UHFFFAOYSA-N 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- YSRUGFMGLKANGO-UHFFFAOYSA-N zinc hafnium(4+) indium(3+) oxygen(2-) Chemical compound [O-2].[Zn+2].[In+3].[Hf+4] YSRUGFMGLKANGO-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Abstract
The invention discloses the preparation method of a kind of bottom gate coplanar type metal oxide thin-film transistor, comprise the following steps: sequentially forming gate electrode and gate medium on substrate, wherein gate electrode part is covered on substrate, and gate medium is covered on substrate and gate electrode；Gate medium uses material deposit source region, drain region conductive layer formation source region and drain region after photoetching and etching that at least one of which contains aluminum and/or titanium；Gate medium, source region and drain region are formed with source region；Gate medium, source region, drain region and active area are formed source contact electrode and drain contact electrode；Device is made annealing treatment.The beneficial effects of the present invention is, in annealing process, aluminum and/or titanium in source region and drain region will diffuse in the active area contacted near place, form the contact transition region of low-resistance, can effectively reduce the contact resistance of source/drain regions and active layer, thus reduce the impact on device property of the source/drain dead resistance.
Description
Technical field
The present invention relates to the preparation method of thin film transistor (TFT), particularly relate to a kind of bottom gate coplanar type metal-oxide film
The preparation method of transistor.
Background technology
Flat pannel display industry is one of the most potential electronics and information industry, and the TFT-LCD of its main flow has evolved into
For one of pillar industry in electronics and information industry.Thin film transistor (TFT) (TFT) is as the core devices of flat pannel display, any active
The flat pannel display of matrix addressing mode such as LCD, OLED are required for control and the driving of TFT.In recent years, by all kinds of high-performance portables
Formula product and the driving of large scale high definition display product demand, flat pannel display is more and more higher to the requirement of TFT.It is limited to relatively
Low carrier mobility, non-crystalline silicon (a-Si) TFT technology of current main-stream can not meet wanting of flat pannel display of future generation
Ask.In this context, the TFT technology development of a new generation is needed badly.It is presently considered to meet flat board of future generation show
The TFT technology shown be mainly based upon low temperature polycrystalline silicon (Low temperature poly-Si, LTPS) TFT Display Technique and
With the metal-oxide semiconductor (MOS) TFT Display Technique that indium gallium zinc oxygen (InGaZnO, IGZO) TFT is representative, wherein IGZO TFT makees
Paid close attention to widely for current TFT field academic research focus.
Metal oxide thin-film transistor has not only had the preferable uniformity of non-crystalline silicon tft and the higher current-carrying of multi-crystal TFT concurrently
The advantage of transport factor, also has the advantage of low technological temperature, and relatively low technological temperature is possible not only to reduce its process costs, also with
The plastic flexible substrate of low cost is mutually compatible.Meanwhile, the long-time stability under metal-oxide TFT electric stress are preferable, bigger taboo
The feature of bandwidth makes metal-oxide have high visible light transmissivity so that it is be applicable to the all-transparent Display Technique in future.All
Many advantages make metal-oxide TFT be hopeful very much to be applied to large scale, high-resolution, high frame frequency Transparence Display of future generation
In.At present, the active layer material that metal-oxide TFT uses is mainly Zinc oxide-base and Indium sesquioxide. base oxide material, including
Zinc oxide, Indium sesquioxide., indium gallium zinc, zinc-tin oxide, indium zinc oxide, Indium sesquioxide. zinc-tin, stannum oxide, Tin monoxide, oxidation Asia
Copper etc..
Metal-oxide TFT generally uses bottom grating structure, can be divided into the end according to source/drain regions with the relative position of active layer
Grid are staggered and bottom gate coplanar type, and wherein in the staggered structure of bottom gate, source region and drain region are positioned at active layer and have been placed in
Active layer both sides, and bottom gate coplanar type structure is in contrast, i.e. source region and drain region is positioned under active layer.Bottom gate cross structure is
The current most popular device architecture of oxide TFT, in order to eliminate or reduce etching liquid in source region and drain region patterning process
Or the impact that plasma is on active layer, etch stopper layer process (etch-stop layer, ESL) or back of the body raceway groove can be used
Etching technics (back channel etch, BCE).ESL technique by introduce etching barrier layer protect active layer not by source/
The impact of leakage graphic metallization processes, can prepare the device of better performances, but the deposit of etching barrier layer, photoetching and etching increase
Having added process costs and difficulty, a step overlay alignment of increase makes device channel length be difficult to do short.Although BCE technique does not exists
The drawback that ESL technique is brought, it is shorter that device channel length can be done, but to the active layer back side during source/drain etched features
Impact is difficult to be completely eliminated, and is found to have the state at the active layer back side in follow-up research under the fundamental characteristics of device and electric stress
Long-time stability all can produce very important impact.In order to farthest take into account device performance, stability and be prepared as
This, the preparation technology of bottom gate cross structure still needs to study further and optimize.For bottom gate coplanar structure, although apply at present
Seldom, but in source/drain patterning step after the deposit of its active layer, therefore active area is not affected by source/drain is patterned, and having can
Can preparation and the device that ESL operational characteristic is comparable and channel length is identical with BCE technique.But it is limited to its construction features, source/drain
Effective contact area of district and active layer is less, can introduce bigger source/drain contact resistance thus affect device property, to different ditches
The impact of the uniformity of road length devices is the most prominent, and the consequence of this deficiency will have a strong impact on shorter channel device property, and
Not yet there are the effective ways that can eliminate this deficiency at present.In order to play the advantage of bottom gate coplanar structure, needing one badly can
The method effectively reducing its source/drain contact resistance.
Summary of the invention
The present invention provides the preparation method of a kind of bottom gate coplanar type metal oxide thin-film transistor, this preparation method energy
Enough its source/drain contact resistances of effectively reduction, improve product quality further.
Comprise the following steps:
1) sequentially forming gate electrode and gate medium on substrate, wherein gate electrode part is covered on substrate, and gate medium covers
It is placed on substrate and gate electrode；
2) material using at least one of which to contain aluminum and/or titanium on gate medium deposits source region, drain region conductive layer and passes through
Source region and drain region is formed after photoetching and etching；
3) on gate medium, source region and drain region, it is formed with source region；
4) on gate medium, source region, drain region and active area, source contact electrode and drain contact electrode are formed；
5) to by step 1)～step 4) device prepared makes annealing treatment, the metallic aluminium in source region, drain region simultaneously
Diffuse in active area with/titanium.
Further, source region, drain region conductive layer are by the metallic aluminium of monolayer, aluminium alloy, Titanium, titanium alloy, leading containing aluminum
The conducting metal oxide of metal oxide or titaniferous is made；Or source region, drain region conductive layer are containing aluminum or titanium coating
Lamination layer structure, every a layer thickness is 5nm～400nm.
Further, in step 5) in, the temperature of annealing is between 150 degrees Celsius～500 degrees Celsius.
Further, the substrate that substrate is made up of glass, silicon chip or flexible material.
Further, substrate is the substrate being fabricated from a flexible material, and is carrying out step 1) front, first deposit cushion.
Further, during the material of grid conducting layer is metal, conducting metal oxide or other conductive materials at least
A kind of；Gate medium is at least one in silicon oxide, silicon nitride, high dielectric constant material and organic dielectric material, its
Thickness is 5nm～400nm；The active area that active area is made up of N-shaped metal oxide materials, its thickness is 5nm～200nm；
The material of passivation layer uses at least one in silicon oxide, silicon nitride, high dielectric constant material and organic dielectric material,
Its thickness is 5nm～400nm.
Further, following steps are specifically included:
1) on substrate, grid conducting layer is deposited；
2) photoetching and etching grid conductive layer, graphically forms gate electrode by grid conducting layer；
3) on substrate and gate electrode, gate medium is deposited；
4) on gate medium, use material deposit source region, drain region conductive layer that at least one of which contains aluminum and/or titanium；
5) photoetching and etching source region, drain region conductive layer, form source region and leakage respectively by source region, drain region conducting layer figureization
District；
6) on gate medium, source region and drain region, it is deposited with source region layer；
7) photoetching and be etched with source region layer, is graphically formed with source region by active region layer；
8) on gate medium, source region, drain region and active area, a passivation layer is deposited；
9) photoetching and Etch Passivation form source contact hole and drain contact hole；
10) on passivation layer, source contact hole and drain contact hole, conductive layer is deposited；
11) photoetching and etching conductive layer, forms source contact electrode and drain contact electrode by conducting layer figureization
12) to by step 1)～step 11) device prepared makes annealing treatment, the metal in source region, drain region simultaneously
Aluminum and/titanium diffuse in active area.
Further, in step 6) after, step 7) before consecutive deposition one dielectric layer, dielectric layer use silicon oxide, nitrogen
At least one in SiClx, high dielectric constant material and organic dielectric material, its thickness is 10nm～400nm；In step
Rapid 7) carry out in dielectric layer is patterned, use same mask plate with active area.
Further, in step 7) after, carry out step 8) front, once make annealing treatment, annealing temperature is at 150 degrees Celsius
～between 500 degrees Celsius.
Further, in step 12) in, the temperature of annealing is between 150 degrees Celsius～500 degrees Celsius.
Contrast prior art, due to the fact that and take above technical scheme, have the advantage that
One, source region of the present invention and drain region material use the metallic aluminium of monolayer, aluminium alloy, Titanium, titanium alloy, leading containing aluminum
Metal oxide or the conducting metal oxide of titaniferous, or containing aluminum or the one of which of the multiple structure of titanium coating, rear
In continuous annealing process, aluminum and/or titanium in source region and drain region will diffuse into the metal-oxide half contacted near place
In conductor active area, form the contact transition region of low-resistance, can effectively reduce the contact resistance of source/drain regions and active layer, thus
Reduce the impact on device property of the source/drain dead resistance；
Two, due to the fact that active layer be deposited on source region and drain region graphically after carry out, the active layer back side is not by source
The patterned impact in district and drain region；Therefore, for relatively back of the body channel etching technique, the present invention can effectively eliminate active area back side matter
The impact that long-time stability under device property and electric stress are brought by amount；
Three, for relatively etch stopper layer process, the present invention need not increase by a step photoetching and graphically changes etching barrier layer, from
And technique is relatively easy.
The present invention can be widely applied in the preparation process of metal oxide thin-film transistor and panel display board.
Accompanying drawing explanation
Fig. 1 to Figure 11 shows the main of the bottom gate coplanar type metal oxide thin-film transistor of the embodiment of the present invention one
Manufacturing process steps, wherein:
Fig. 1 is the schematic diagram of deposit grid conducting layer；
Fig. 2 is photoetching, etch, remove photoresist after form the schematic diagram of gate electrode；
Fig. 3 is the schematic diagram of deposit gate medium；
Fig. 4 is deposit source region, the schematic diagram of drain region conductive layer；
Fig. 5 is photoetching, etch, remove photoresist after form source region, the schematic diagram in drain region；
Fig. 6 is the schematic diagram being deposited with source region layer；
Fig. 7 is photoetching, etch, remove photoresist after be formed with the schematic diagram of source region；
Fig. 8 is the schematic diagram of deposit passivation layer；
Fig. 9 is photoetching, etch, remove photoresist after form the schematic diagram of contact hole；
Figure 10 is to form source contact electrode, the schematic diagram of drain contact electrode；
Figure 11 is that the aluminum in source region, drain region diffuses into active area and forms the schematic diagram of low-resistance transition region after annealing；
In above-mentioned figure: 101 substrates；102 gate electrodes；103 gate mediums；104 source regions；105 drain regions；106—
Active area；107 passivation layers；108 source region extraction electrodes；109 drain region extraction electrodes；110 source region low-resistance transition regions；
111 drain region low-resistance transition regions；
Figure 12 to Figure 22 shows a kind of bottom gate coplanar type metal-oxide film crystal in the embodiment of the present invention two
The main technological steps of the preparation method of pipe, wherein:
Figure 12 is the schematic diagram of deposit grid conducting layer；
Figure 13 is photoetching, etch, remove photoresist after form the schematic diagram of gate electrode；
Figure 14 is the schematic diagram of deposit gate medium；
Figure 15 is deposit source region, the schematic diagram of drain region conductive layer；
Figure 16 is photoetching, etch, remove photoresist after form source region, the schematic diagram in drain region；
Figure 17 is to be deposited with source region layer and the schematic diagram of the first passivation layer；
Figure 18 is photoetching, etch, remove photoresist after be formed with source region and the schematic diagram of the first passivation layer；
Figure 19 is the schematic diagram of deposit the second passivation layer；
Figure 20 is photoetching, etch, remove photoresist after form the schematic diagram of contact hole；
Figure 21 is to form source contact electrode, the schematic diagram of drain contact electrode；
Figure 22 is that the aluminum in source region, drain region diffuses into active area and forms the schematic diagram of low-resistance transition region after annealing；
In above-mentioned figure: 201 substrates；202 gate electrodes；203 gate mediums；204 source regions；205 drain regions；206—
Active area；207 second passivation layers；208 source contact electrode；209 drain contact electrode；210 source region low-resistance transition
District；211 drain region low-resistance transition regions；212 first passivation layers.
Detailed description of the invention
The present invention provides the preparation method of a kind of bottom gate coplanar type metal oxide thin-film transistor, including following step
Rapid:
Substrate deposits grid conducting layer.Wherein, the substrate that substrate is made up of glass, silicon chip or flexible material.Soft
Property material be typically PEN (PEN), polyethylene terephthalate (PET), polyimides (PI) or
Flexible glass etc..When substrate uses flexible material to make, before being deposited grid conducting layer, first deposit cushion.Buffering
The material of layer can be at least one in silicon oxide, silicon nitride, high dielectric constant material and organic dielectric material, its
Middle high dielectric constant material includes aluminium oxide, hafnium oxide, zirconium oxide etc..This buffer layer deposition method using plasma increases
Extensive chemical vapor deposition, magnetron sputtering or reactive sputtering, atomic layer deposition or spin coating technique etc., this buffer layer thickness be 5nm～
400nm.The material of grid conducting layer is at least one in metal, conducting metal oxide or other conductive materials.
Photoetching and etching grid conductive layer, graphically form gate electrode by grid conducting layer.
Substrate and gate electrode deposit gate medium.Wherein, gate medium is silicon oxide, silicon nitride, high dielectric constant
At least one in material and organic dielectric material, its thickness is 5nm～400nm.Deposition process using plasma strengthens
Chemical vapor deposition, magnetron sputtering or reactive sputtering, atomic layer deposition or spin coating technique.
Gate medium deposits source region, drain region conductive layer.Wherein, source region, drain region conductive layer are by the metallic aluminium of monolayer, aluminum
The conducting metal oxide of alloy, Titanium, titanium alloy, conducting metal oxide containing aluminum or titaniferous is made；Source region, drain region
Conductive layer can also be the lamination layer structure containing aluminum or titanium coating, and its every a layer thickness is 5nm～400nm.When source region, drain region
When conductive layer uses multi-layer metal structure, the metal layer material in addition to aluminum or titanium can use copper, molybdenum or tantalum etc..Deposition process is adopted
With magnetron sputtering, reactive sputtering, heat evaporation, electronics art evaporation etc..
Photoetching and etching source region, drain region conductive layer, form source region and drain region respectively by source region, drain region conducting layer figureization.
Gate medium, source region and drain region are deposited with source region layer.Before carrying out next step, can be with consecutive deposition one medium
Layer, dielectric layer uses at least one in silicon oxide, silicon nitride, high dielectric constant material and organic dielectric material, its
Thickness is 10nm～400nm.
Photoetching and be etched with source region layer, is graphically formed with source region by active region layer.Active area is by N-shaped metal-oxide
The active area that material is made, active area is N-shaped metal oxide materials, can use zinc oxide (ZnO), Indium sesquioxide. (In2O3) or base
In the multi-component metal oxide semiconductor of above two material, such as indium gallium zinc (IGZO), indium zinc oxide (IZO), oxidation
Zinc-tin (ZTO), hafnium oxide indium zinc (HIZO), tin indium oxide (ITO) etc..Deposition technology uses magnetron sputtering, reactive sputtering, atom
The methods such as layer deposit or spin coating, or use anodic oxidation to obtaining after processing, its thickness is 5nm～200nm.Now, may be used
To use same mask plate with active area, dielectric layer is patterned.This step can add and once makes annealing treatment, the temperature of annealing
Degree is between 150 degrees Celsius～500 degrees Celsius.
Gate medium, source region, drain region and active area deposit passivation layer.The material of passivation layer use silicon oxide, silicon nitride,
At least one in high dielectric constant material and organic dielectric material, its thickness is 5nm～400nm.
Photoetching and Etch Passivation form source contact hole and drain contact hole.
Passivation layer, source contact hole and drain contact hole deposit conductive layer.
Photoetching and etching conductive layer, form source contact electrode and drain contact electrode by conducting layer figureization.
The device prepared by above-mentioned steps is made annealing treatment.The temperature of annealing is at 150 degrees Celsius～500 degrees Celsius
Between.After annealing, source region can diffuse into the active area near contacting with the metallic aluminium in drain region and/or titanium, forms aluminum respectively
And/or titanium doped source region low-resistance transition region and drain region low-resistance transition region.
Source region of the present invention and drain region material use the metallic aluminium of monolayer, aluminium alloy, Titanium, titanium alloy, conduction containing aluminum
Metal-oxide or the conducting metal oxide of titaniferous, or containing aluminum or the one of which of the multiple structure of titanium coating, it is possible to
In annealing process, the metal-oxide making the aluminum in source region and drain region and/or titanium will diffuse near the place of contacting partly is led
In body active area, form the contact transition region of low-resistance, can effectively reduce the contact resistance of source/drain regions and active layer, thus subtract
The impact on device property of the little source/drain dead resistance, and reach this effect and be not required to increase by a step photoetching and graphically change quarter
Erosion barrier layer, therefore Simplified flowsheet, improve production efficiency and product quality.
Combine accompanying drawing below by detailed description of the invention the present invention is described in further detail.
Embodiment one:
Refer to Fig. 1 to Figure 11, Fig. 1 to Figure 11 and show a kind of bottom gate coplanar type metal oxide thin-film transistor
Preparation method, comprises the following steps:
As it is shown in figure 1, on the substrate 101 by metal molybdenum (Mo) conductive thin of magnetically controlled DC sputtering one layer of 150nm of deposit
Film.
As in figure 2 it is shown, on metal Mo spin coating photoresist；The gate electrode figure of Mo is formed after carrying out photoetching, etching；Carry out
Remove photoresist, cleaning treatment, obtain gate electrode 102.
As it is shown on figure 3, using plasma chemical vapor deposition (PECVD) method is formed sediment on substrate 101 and gate electrode 102
A long-pending thickness is the gate medium 103 of 200nm, and the material of gate medium 103 is SiO2。
As shown in Figure 4, using DC magnetron sputtering method to deposit a layer thickness on gate medium 103 is the aluminium gold of 100nm
Belong to conductive layer.
As it is shown in figure 5, on metal Al spin coating photoresist；Source region and the drain region figure of Al is formed after carrying out photoetching, etching；
Carry out removing photoresist, cleaning treatment, obtain source region 104 and drain region 105.
As shown in Figure 6, DC magnetron sputtering method is used to deposit one layer on source region 104, drain region 105 and gate medium 103
Thickness is indium gallium zinc (IGZO) active layer of 50nm.
As it is shown in fig. 7, on IGZO spin coating photoresist；IGZO active area figure is formed after carrying out photoetching, etching；Go
Glue, cleaning treatment, obtain active area 106.
As shown in Figure 8, PECVD method is used to deposit one on gate medium 103, source region 104, drain region 105 and active area 106
Layer thickness is the passivation layer 107 of 200nm, and passivation layer 107 is SiO2Passivation layer.
As it is shown in figure 9, on passivation layer 107 spin coating photoresist, form source contact hole and drain region after carrying out photoetching, etching
Contact hole.Carry out again removing photoresist, cleaning treatment, obtain source contact hole and drain contact hole.
Using magnetically controlled DC sputtering, depositing a layer thickness on passivation layer 107, source contact hole and drain contact hole is
Tin indium oxide (ITO) conductive layer of 150nm.
As shown in Figure 10, spin coating photoresist on ITO conductive layer；Carry out photoetching, etching after formed source contact electrode and
Drain contact electrode；Carry out again removing photoresist, cleaning treatment, obtain source contact electrode 108 and drain contact electrode 109.
As shown in figure 11, carry out making annealing treatment under 350 degrees Celsius 2 hours, obtain source region low-resistance transition region 110 and drain region
Low-resistance transition region 111.
Embodiment two:
Refer to Figure 12 to Figure 22, Figure 12 to Figure 22 and show a kind of bottom gate coplanar type metal oxide thin-film transistor
Preparation method, comprise the following steps:
As shown in figure 12, on the substrate 201 by the metal molybdenum conductive film of magnetically controlled DC sputtering one layer of 150nm of deposit.
As shown in figure 13, spin coating photoresist on metal Mo；The gate electrode figure of Mo is formed after carrying out photoetching, etching；Enter
Row removes photoresist, cleaning treatment, obtains gate electrode 202.
As shown in figure 14, using plasma chemical gas-phase deposition method deposits a thickness on substrate 201 and gate electrode 202
Degree is the gate medium 203 of 200nm, and the material of gate medium 203 is SiO2。
As shown in figure 15, using DC magnetron sputtering method to deposit a layer thickness on gate medium 203 is the doping of 100nm aluminum
Zinc oxide metallic oxide conducting layer.
As shown in figure 16, spin coating photoresist on AZO conductive layer, then carry out photoetching, etching after formed AZO source region and
Drain region figure, then carry out removing photoresist, cleaning treatment, obtain source region 204 and drain region 205.
As shown in figure 17, DC magnetron sputtering method is used to deposit one layer on source region 204, drain region 205 and gate medium 203
Thickness is the indium gallium zinc active layer of 50nm.IGZO active layer uses atomic layer deposition method consecutive deposition a layer thickness
Al for 30nm2O3Passivation layer.
As shown in figure 18, at Al2O3Spin coating photoresist on passivation layer.After carrying out photoetching, initially with reactive ion etching
(RIE) method etching Al2O3Passivation layer, Al2O3After having etched, dilute hydrochloric acid (HCl) solution etches IGZO is used to be formed with source region
Figure；Carry out again removing photoresist, cleaning treatment, obtain active area 206 and the first passivation layer 212.
As shown in figure 19, use PECVD method on gate medium 203, source region 204, drain region 205 and the first passivation layer 212
Deposit a layer thickness is second passivation layer 207 of 200nm, and the second passivation layer 207 is SiO2Passivation layer.
As shown in figure 20, spin coating photoresist on the second passivation layer 207；Source contact is formed after carrying out photoetching, RIE etching
Hole and drain contact hole；Carry out again removing photoresist, cleaning treatment, obtain source contact hole and drain contact hole.
Use magnetically controlled DC sputtering, the second passivation layer 207, source contact hole and drain contact hole deposit a layer thickness
Tin indium oxide (ITO) conductive layer for 150nm.
As shown in figure 21, spin coating photoresist on ITO conductive layer；Then carry out again removing photoresist, cleaning after carrying out photoetching, etching
Process, obtain source contact electrode 208 and drain contact electrode 209.
As shown in figure 22, carry out making annealing treatment under 350 degrees Celsius 2 hours, obtain source region low-resistance transition region 210 and drain region
Low-resistance transition region 211.
In the present embodiment, for relatively embodiment one, many one layer of passivation layers, the first passivation layer 212 and the second passivation layer
207 pairs of active layers 206 play the effect of protection jointly, and protection degree relatively embodiment one is big, it is possible to reduce source region 204 and leakage further
The impact that active layer 206 is produced by district 205 graphical treatment.
Above content is to combine specific embodiment further description made for the present invention, it is impossible to assert this
Bright being embodied as is confined to these explanations.For general technical staff of the technical field of the invention, do not taking off
On the premise of present inventive concept, it is also possible to make some simple deduction or replace, all should be considered as belonging to the protection of the present invention
Scope.
Claims (10)
1. the preparation method of a bottom gate coplanar type metal oxide thin-film transistor, it is characterised in that comprise the following steps:
1) sequentially forming gate electrode and gate medium on substrate, wherein said gate electrode part is covered on described substrate, described
Gate medium is covered on described substrate and described gate electrode；
2) material using at least one of which to contain aluminum and/or titanium on described gate medium deposits source region, drain region conductive layer and passes through
Source region and drain region is formed after photoetching and etching；
3) on described gate medium, described source region and described drain region, it is formed with source region；
4) on described gate medium, described source region, described drain region and described active area, source contact electrode and drain contact are formed
Electrode；
5) device prepared by step 1)～step 4) is made annealing treatment, the metallic aluminium in the most described source region, drain region
And/or titanium diffuses in described active area.
The preparation method of a kind of bottom gate coplanar type metal oxide thin-film transistor the most as claimed in claim 1, its feature
Being, described source region, drain region conductive layer are by the metallic aluminium of monolayer, aluminium alloy, Titanium, titanium alloy, conducting metal oxygen containing aluminum
The conducting metal oxide of compound or titaniferous is made；Or described source region, drain region conductive layer are compound containing aluminum or titanium coating
Rotating fields, every a layer thickness is 5nm～400nm.
The preparation method of a kind of bottom gate coplanar type metal oxide thin-film transistor the most as claimed in claim 1, its feature
Being, in step 5), the temperature of annealing is between 150 degrees Celsius～500 degrees Celsius.
The preparation method of a kind of bottom gate coplanar type metal oxide thin-film transistor the most as claimed in claim 1 or 2, it is special
Levy and be, the substrate that described substrate is made up of glass, silicon chip or flexible material.
The preparation method of a kind of bottom gate coplanar type metal oxide thin-film transistor the most as claimed in claim 1 or 2, it is special
Levying and be, described substrate is the substrate being fabricated from a flexible material, and before carrying out step 1), first deposits cushion.
The preparation method of a kind of bottom gate coplanar type metal oxide thin-film transistor the most as claimed in claim 1, its feature
Being, the material of described grid conducting layer is at least one in metal, conducting metal oxide or other conductive materials；Described
Gate medium is at least one in silicon oxide, silicon nitride, high dielectric constant material and organic dielectric material, and its thickness is
5nm～400nm；The active area that described active area is made up of N-shaped metal oxide materials, its thickness is 5nm～200nm；Institute
The material stating passivation layer uses at least in silicon oxide, silicon nitride, high dielectric constant material and organic dielectric material
Kind, its thickness is 5nm～400nm.
The preparation method of a kind of bottom gate coplanar type metal oxide thin-film transistor the most as claimed in claim 1 or 2, it is special
Levy and be, comprise the following steps:
1) on substrate, grid conducting layer is deposited；
2) photoetching and the described grid conducting layer of etching, graphically form gate electrode by described grid conducting layer；
3) on described substrate and described gate electrode, gate medium is deposited；
4) on described gate medium, use material deposit source region, drain region conductive layer that at least one of which contains aluminum and/or titanium；
5) photoetching and etching described source region, drain region conductive layer, described source region, drain region conducting layer figureization are formed respectively source region and
Drain region；
6) on described gate medium, described source region and described drain region, it is deposited with source region layer；
7) photoetching and the described active region layer of etching, be graphically formed with source region by described active region layer；
8) on described gate medium, described source region, described drain region and active area, a passivation layer is deposited；
9) photoetching and the described passivation layer of etching form source contact hole and drain contact hole；
10) on described passivation layer, described source contact hole and described drain contact hole, conductive layer is deposited；
11) photoetching and the described conductive layer of etching, form source contact electrode and drain contact electrode by described conducting layer figureization；
12) device prepared by step 1)～step 11) is made annealing treatment, the metal in the most described source region, drain region
Aluminum and/titanium diffuse in described active area.
The preparation method of a kind of bottom gate coplanar type metal oxide thin-film transistor the most as claimed in claim 7, its feature
Being, after step 6), consecutive deposition one dielectric layer before step 7), described dielectric layer uses silicon oxide, silicon nitride, Gao Jie
At least one in constant dielectric material and organic dielectric material, its thickness is 10nm～400nm；Step 7) is carried out
Described dielectric layer is patterned, uses same mask plate with described active area.
The preparation method of a kind of bottom gate coplanar type metal oxide thin-film transistor the most as claimed in claim 7, its feature
Being, after step 7), before carrying out step 8), once make annealing treatment, annealing temperature is at 150 degrees Celsius～500 degrees Celsius
Between.
The preparation method of a kind of bottom gate coplanar type metal oxide thin-film transistor the most as claimed in claim 7, its feature
Being, in step 12), the temperature of annealing is between 150 degrees Celsius～500 degrees Celsius.
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| CN101728433A (en) * | 2008-10-10 | 2010-06-09 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
| WO2012002085A1 (en) * | 2010-06-29 | 2012-01-05 | 株式会社日立製作所 | Semiconductor device |
| CN102598284A (en) * | 2009-11-06 | 2012-07-18 | 株式会社半导体能源研究所 | Semiconductor device |
| CN104157699A (en) * | 2014-08-06 | 2014-11-19 | 北京大学深圳研究生院 | Back channel etching type thin film transistor and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101728433A (en) * | 2008-10-10 | 2010-06-09 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
| CN102598284A (en) * | 2009-11-06 | 2012-07-18 | 株式会社半导体能源研究所 | Semiconductor device |
| WO2012002085A1 (en) * | 2010-06-29 | 2012-01-05 | 株式会社日立製作所 | Semiconductor device |
| CN104157699A (en) * | 2014-08-06 | 2014-11-19 | 北京大学深圳研究生院 | Back channel etching type thin film transistor and preparation method thereof |
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Application publication date: 20161109 |