CN116646392A - Schottky barrier thin film transistor and preparation method thereof - Google Patents
Schottky barrier thin film transistor and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 11
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
The embodiment of the application provides a Schottky barrier metal oxide thin film transistor and a preparation method thereof, which relate to the technical field of semiconductors, and the preparation method comprises the following steps: the semiconductor device comprises a substrate, a gate electrode layer, a gate dielectric layer, a metal oxide semiconductor layer, a metal oxide insulating layer and an electrode layer, wherein the electrode layer comprises a source electrode and a drain electrode, and a non-noble metal material is adopted. The insulating layer is used as an etching barrier layer of the semiconductor layer and also used as a regulating and controlling functional layer of the Schottky contact barrier between the electrode layer and the semiconductor layer. And part of the electrode layer is in direct contact with the semiconductor layer to form an ohmic contact region or a low Schottky contact barrier region, and the other part of the electrode layer is in direct contact with the metal oxide insulating layer to form a high Schottky contact barrier region, so that the Schottky barrier metal oxide thin film transistor is ensured to have the characteristics of low saturation voltage and high saturation output current. The Schottky barrier metal oxide thin film transistor has the advantages of simple structure, low preparation cost, excellent electrical characteristics and the like.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a Schottky barrier thin film transistor and a preparation method thereof.
Background
The schottky barrier thin film transistor, also called a source gate thin film transistor or a tunneling contact thin film transistor, generally has a lower saturation voltage, and the output current after the device is saturated remains basically unchanged, and the characteristic can be applied to realize the line voltage drop compensation of a current-driven display device; in addition, the Schottky barrier thin film transistor can still maintain good field effect characteristics under the condition of ultra-narrow channels, which is helpful for improving the pixel density or the circuit integration level of the display device. Therefore, the schottky barrier thin film transistor has wide application prospects in the fields of novel display devices, such as active matrix organic light emitting diode displays (AMOLED), active matrix millimeter/micro-displays (AM-mini/micro-LEDs), integrated circuits and the like.
However, the inventor researches and discovers that the manufacturing cost of the existing schottky barrier thin film transistor is high due to the adoption of noble metals such as platinum, palladium and the like as metal source/drain electrodes; when non-noble metal electrodes are used, the problem of higher contact defect states or lower saturation current density exists.
Disclosure of Invention
The object of the present application includes, for example, providing a schottky barrier thin film transistor and a method of manufacturing the same, which can at least partially solve the above technical drawbacks, and realize a high performance schottky barrier metal oxide thin film transistor with low cost, low saturation voltage and high saturation output current density characteristics.
Embodiments of the application may be implemented as follows:
in a first aspect, an embodiment of the present application provides a schottky barrier thin film transistor, including: the semiconductor device comprises a substrate, a gate electrode layer, a gate dielectric layer, a semiconductor layer, an insulating layer and an electrode layer, wherein the electrode layer comprises a source electrode and a drain electrode;
the insulating layer is a metal oxide insulating layer, the semiconductor layer is a metal oxide semiconductor layer, and the gate layer, the insulating layer, the semiconductor layer and the electrode layer are patterned by photoetching;
the insulating layer is used as an etching barrier layer of the semiconductor layer and is also used as a regulating and controlling functional layer of the Schottky contact barrier between the electrode layer and the semiconductor layer;
the electrode layer is in partial direct contact with the semiconductor layer and in partial direct contact with the insulating layer.
Alternatively, the electrode layer is in direct contact with the semiconductor layer to form a schottky barrier smaller than a schottky barrier formed between the electrode layer, the insulating layer, and the semiconductor layer.
Optionally, a silicon nitride passivation layer is disposed over the insulating layer and the electrode layer to enhance conductivity of the semiconductor layer between the source electrode and the drain electrode.
Optionally, the source electrode and the drain electrode are stacked electrodes, and the source electrode and the drain electrode are both composed of a first work function metal and a second work function metal;
the first work function metal is deposited prior to the second work function metal;
a part of the first work function metal is in direct contact with the semiconductor layer, the other part of the first work function metal is in direct contact with the insulating layer, and the second work function metal is in direct contact with the insulating layer;
ohmic contact or quasi-ohmic contact is formed between the first work function metal and the semiconductor layer, ohmic contact or quasi-ohmic contact is formed among the first work function metal, the insulating layer and the semiconductor layer, and Schottky contact is formed among the second work function metal, the insulating layer and the semiconductor layer.
Optionally, the thickness of the semiconductor layer is 10-200 nm, and the thickness of the insulating layer is less than or equal to 10 nm.
Optionally, the semiconductor layer is made of InGaZnO, inZnO, inZnSnO, ln-IZO, inGaO,ZnO、Ga 2 O 3 Or SnO 2 Any one of them;
the insulating layer is made of Al 2 O 3 、SiO 2 、HfO 2 Or ZrO(s) 2 Any one of them;
the electrode layer is made of one or two of Cu, mo, al, ti, ni, W and Cr or one or two of Cu, mo, al, ti, ni, W and Cr alloy.
In a second aspect, an embodiment of the present application provides a method for preparing a schottky barrier thin film transistor, where the method includes:
providing a substrate, depositing a gate layer on the substrate by a sputtering mode, and carrying out photoetching patterning on the gate layer;
forming a gate dielectric layer on the gate electrode layer by means of plasma enhanced chemical vapor deposition;
preparing a semiconductor layer on the gate dielectric layer by means of magnetron sputtering or atomic layer deposition, and performing photoetching patterning on the semiconductor layer, wherein the semiconductor layer is a metal oxide semiconductor layer;
preparing an insulating layer on the semiconductor layer by means of magnetron sputtering or atomic layer deposition, and performing photoetching patterning on the insulating layer, wherein the insulating layer is a metal oxide insulating layer;
and depositing metal on the insulating layer and photoetching and patterning to form an electrode layer to obtain the Schottky barrier thin film transistor, wherein the electrode layer comprises a source electrode and a drain electrode.
Optionally, the method further comprises:
the semiconductor layer is treated with an argon plasma to convert the semiconductor layer not covered by the insulating layer into a conductor.
Optionally, the source electrode and the drain electrode are stacked electrodes, and the source electrode and the drain electrode are both composed of a first work function metal and a second work function metal; the method further comprises the steps of:
depositing a first work function metal layer on the semiconductor layer and the insulating layer, and carrying out photoetching patterning on the first work function metal layer;
and depositing a second work function metal layer on the insulating layer, and carrying out photoetching patterning on the second work function metal layer.
Optionally, the method further comprises:
forming a silicon nitride passivation layer on the insulating layer by means of plasma enhanced chemical vapor deposition, or sequentially depositing silicon dioxide and the silicon nitride passivation layer by means of plasma enhanced chemical vapor deposition;
and annealing is carried out in an inert gas atmosphere, so that hydrogen in the silicon nitride passivation layer is diffused into the semiconductor layer, and the conductivity of the semiconductor layer is improved.
The beneficial effects of the embodiment of the application include:
the present solution provides a schottky barrier thin film transistor, comprising: the semiconductor device comprises a substrate, a gate electrode layer, a gate dielectric layer, a semiconductor layer, an insulating layer and an electrode layer, wherein the electrode layer comprises a source electrode and a drain electrode. By adopting the non-noble metal source-drain electrode, the preparation cost of the device is greatly reduced; by arranging the metal oxide insulating layer, the direct contact between metal and the semiconductor layer is avoided, so that a Schottky barrier closer to a theoretical value is formed, and the defect state formed by contact is reduced; by forming an ohmic contact region and a Schottky barrier contact region at the source/drain electrode simultaneously, the Schottky barrier thin film transistor is ensured to have higher saturation output current density and lower saturation voltage.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a schottky barrier thin film transistor according to an embodiment of the present application;
fig. 2 is a schematic diagram of a schottky barrier thin film transistor including a passivation layer according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a Schottky barrier thin film transistor including metal electrodes with different work functions according to an embodiment of the present application;
fig. 4 is a flowchart illustrating steps of a method for manufacturing a schottky barrier thin film transistor according to an embodiment of the present application;
fig. 5 is a schematic diagram of a resistor-capacitor network in a saturation critical state of a schottky barrier thin film transistor according to an embodiment of the present application;
fig. 6 is a schematic diagram of a resistor-capacitor network in which a semiconductor layer not covered by an insulating layer is processed and then converted into a conductor schottky barrier thin film transistor in a saturated critical state according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a resistance-capacitance network of a Schottky barrier thin film transistor in a saturation threshold state comprising metal electrodes with different work functions according to an embodiment of the present application;
fig. 8 is a schematic diagram of a schottky barrier indium gallium zinc oxide thin film transistor based on a copper source/drain electrode according to an embodiment of the present application;
fig. 9 is a line graph of schottky barrier height as a function of alumina insulation layer thickness provided by an embodiment of the present application;
fig. 10 is an output characteristic diagram of a schottky barrier indium gallium zinc oxide thin film transistor based on a copper source/drain electrode according to an embodiment of the present application.
Icon: a 10-schottky barrier thin film transistor; 11-a substrate; 12-gate layer; 13-a gate dielectric layer; 14-a semiconductor layer; 15-an insulating layer; 16-electrode layer; 161-source electrode; 162-drain electrode; 17-depletion region; 18-a passivation layer; 21-a first work function metal; 22-second work function metal.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
Since 2004 Hosono et al successfully developed an ohmic contact metal oxide thin film transistor using amorphous indium gallium zinc oxide (a-IGZO) as a channel layer material, the a-IGZO thin film transistor has higher carrier mobility>10cm 2 And (2) the Active Matrix Liquid Crystal Display (AMLCD) and AMOLED fields can be rapidly applied in commercialization due to the advantages of small off-state current, large-area uniform preparation, good stability, compatibility with low-temperature processes and the like. Accordingly, schottky barrier metal oxide thin film transistors have also received much research and attention.
In the prior art, a schottky barrier thin film transistor [ Proceedings of the National Academy of Sciences,2019,116 (11): 4843-4848] is proposed, and the formation of the schottky contact depends on the introduction of oxygen when sputtering a metal source/drain electrode on a metal oxide layer, so as to facilitate the formation of good schottky contact between the metal and a metal oxide semiconductor layer. The mode adopts noble metal source/drain electrodes such as Pd, pt and the like, and can realize the Schottky barrier metal oxide thin film transistor with good electrical characteristics. However, noble metals are expensive and are not viable for large area applications in flat panel display devices. In another mode [ IEEE transactions on electron devices,2013,60 (3) [ 1128-1135], when metals such as Ni and Cu are used as source/drain electrodes, the nickel oxide and copper oxide formed at the interface are acceptor state defects, so that the schottky barrier thin film transistor prepared correspondingly has serious stability problem and cannot meet the application requirements of display and electronic circuits.
In addition, a schottky barrier metal oxide thin film transistor based on Mo source/drain electrode is also proposed in the prior art [ Science,2016,354 (6310):302-304 ], which can change the contact between Mo electrode and IGZO layer from ohmic contact to schottky contact by adjusting the amount of oxygen introduced during the sputter deposition of IGZO layer. However, the contact greatly increases the contact resistance of the device, resulting in a significant drop in the on-current of the corresponding schottky barrier device, which obviously limits the increase in pixel density in display device applications requiring an increase in the width of the device channel.
In summary, the existing schottky barrier metal oxide thin film transistor uses noble metals such as platinum, palladium, gold and the like as source/drain electrodes, so that the manufacturing cost is high; the non-noble metal electrodes such as copper, nickel and molybdenum have the problems of higher contact defect state and lower saturation output current density, and cannot meet the application requirements of the fields of novel display, integrated circuits and the like.
Based on the above circumstances, the embodiments of the present disclosure provide a schottky barrier thin film transistor and a method for manufacturing the same, which can effectively alleviate the above technical problems.
Referring to fig. 1, a schottky barrier thin film transistor 10 according to an embodiment of the present application includes: the substrate 11, the gate layer 12, the gate dielectric layer 13, the semiconductor layer 14, the insulating layer 15, and the electrode layer 16, the electrode layer 16 including a source electrode 161 and a drain electrode 162.
The insulating layer 15 is a metal oxide insulating layer, the semiconductor layer 14 is a metal oxide semiconductor layer, and the gate layer 12, the insulating layer 15, the semiconductor layer 14, and the electrode layer 16 are all lithographically patterned.
The insulating layer 15 serves as an etch stop layer for the semiconductor layer 14, protecting the semiconductor layer 14 from etching liquid during the photolithographic patterning of the electrode layer 16. Meanwhile, as a functional layer that promotes the schottky contact barrier between the electrode layer 16 and the semiconductor layer 14.
The electrode layer 16 and the semiconductor layer 14 form schottky contact, the electrode layer 16, the insulating layer 15 and the semiconductor layer 14 form schottky contact, and a depletion region 17 with a certain width is formed in the semiconductor layer 14 at a corresponding contact position.
As shown in fig. 1, the schottky barrier thin film transistor 10 sequentially includes a substrate 11, a gate electrode layer 12, a gate dielectric layer 13, a semiconductor layer 14, an insulating layer 15, and an electrode layer 16 in order of deposition. The electrode layer 16 includes a source electrode 161 and a drain electrode 162. The material of the base 11 may be a hard substrate such as glass or silicon, or a flexible substrate such as polyimide. The material of the gate layer 12 may be one of aluminum, copper, titanium, molybdenum, or indium tin oxide conductive oxide. The material of the gate dielectric layer 13 may be silicon dioxide or silicon nitride, or may be a stacked layer of silicon dioxide and silicon nitride. The material of semiconductor layer 14 may be InGaZnO, inZnO, inZnSnO, ln-IZO, inGaO, znO, ga 2 O 3 Or SnO 2 Any one of them. The insulating layer is metal oxide, and the specific material can be Al 2 O 3 、SiO 2 、HfO 2 、ZrO 2 Any one of them. The source electrode 161 and the drain electrode 162 may be made of any one of Cu, mo, ni, W materials, and the source electrode 161 and the drain electrode 162 may be made of the same material or different materials. The insulating layer 15 is not only an etching barrier layer of the semiconductor layer 14 when the electrode layer 16 is lithographically patterned, but also serves as a contact barrier between the modulating electrode layer 16 and the semiconductor layer 14.
Alternatively, the schottky contact barrier formed by the semiconductor layer 14 and the electrode layer 16 is smaller than the schottky contact barrier formed between the semiconductor layer 14, the insulating layer 15, and the electrode layer 16.
Optionally, as shown in fig. 2, a silicon nitride passivation layer 18 is disposed over the insulating layer 15 and the electrode layer 16, where the silicon nitride passivation layer 18 not only serves as a protection layer for the back channel of the schottky barrier thin film transistor 10, but also enables hydrogen doping of the semiconductor layer 14 to enhance the conductivity of the semiconductor layer 14.
Alternatively, as shown in fig. 3, the source electrode 161 and the drain electrode 162 are stacked electrodes, and the source electrode 161 and the drain electrode 162 are each composed of a first work function metal 21 and a second work function metal 22.
The first work function metal 21 is deposited prior to the second work function metal 22. A part of the first work function metal 21 is in direct contact with the semiconductor layer 14, another part is in direct contact with the insulating layer 15, and the second work function metal 22 is in direct contact with the insulating layer 15.
Ohmic or quasi-ohmic contact is formed between the first work function metal 21 and the semiconductor layer 14, ohmic or quasi-ohmic contact is formed between the first work function metal 21, the insulating layer 15 and the semiconductor layer 14, and schottky contact is formed between the second work function metal 22, the insulating layer 15 and the semiconductor layer 14.
The first work function metal 21 is a low work function metal such as Al, ti, cr, etc., and the second work function metal 22 is a high work function metal such as Cu, mo, ni, W, etc. In the preparation of the schottky barrier thin film transistor 10, the first work function metal 21 is deposited and lithographically patterned, and the second work function metal 22 is deposited and lithographically patterned. Wherein the first work function metal 21 is in direct contact with the semiconductor layer 14 and in part with the insulating layer 15; the second work function metal 22 is in direct contact with only the insulating layer 15. Ohmic contact or quasi-ohmic contact is formed between the first work function metal 21 and the semiconductor layer 14, ohmic contact or quasi-ohmic contact is formed between the first work function metal 21, the insulating layer 15 and the semiconductor layer 14, and schottky contact is formed between the second work function metal 22, the insulating layer 15 and the semiconductor layer 14, wherein the schottky contact potential barrier is greater than 0.4eV.
Alternatively, the thickness of the semiconductor layer 14 is 10-200 nm, and the thickness of the insulating layer 15 is less than or equal to 10 nm.
Optionally, the material of the semiconductor layer 14 is InGaZnO, inZnO, inZnSnO, ln-IZO, inGaO, znO, ga 2 O 3 Or SnO 2 Any one of them. The insulating layer 15 is made of Al 2 O 3 、SiO 2 、HfO 2 Or ZrO(s) 2 Any one of them. The material of the electrode layer 16 is either one or both of Cu, mo, al, ti, ni, W or Cr, or either one or both of Cu, mo, al, ti, ni, W or Cr alloy.
Based on the same inventive concept, as shown in fig. 4, an embodiment of the present application provides a schottky barrier thin film transistor manufacturing method, which includes the steps of:
step S110: providing a substrate, depositing a gate layer on the substrate by a sputtering mode, and carrying out photoetching patterning on the gate layer.
Step S120: and forming a gate dielectric layer on the gate layer by means of plasma enhanced chemical vapor deposition.
Step S130: preparing a semiconductor layer on the gate dielectric layer by means of magnetron sputtering or atomic layer deposition, and carrying out photoetching patterning on the semiconductor layer, wherein the semiconductor layer is a metal oxide semiconductor layer.
Step S140: and preparing an insulating layer on the semiconductor layer by means of magnetron sputtering or atomic layer deposition, and carrying out photoetching patterning on the insulating layer, wherein the insulating layer is a metal oxide insulating layer.
Step S150: and depositing metal on the insulating layer and photoetching and patterning to form an electrode layer to obtain the Schottky barrier thin film transistor, wherein the electrode layer comprises a source electrode and a drain electrode.
In the method for manufacturing a schottky barrier thin film transistor provided in the embodiments of the present specification, reference numerals in the embodiments of the schottky barrier thin film transistor described above will be continued.
Optionally, the method further comprises: after the insulating layer 15 is deposited and photolithography is completed, the semiconductor layer 14 is treated with argon ions so that the semiconductor layer 14 not covered with the insulating layer 15 is converted into a conductor.
Alternatively, the source electrode 161 and the drain electrode 162 are stacked electrodes, and the source electrode 161 and the drain electrode 162 are each composed of the first work function metal 21 and the second work function metal 22. The method further comprises the steps of:
a first work function metal layer is formed on the semiconductor layer 14 and the insulating layer 15 by sputter deposition, and the first work function metal layer is subjected to photolithographic patterning. A second work function metal layer is formed on the insulating layer 15 by sputter deposition, and the second work function metal layer is subjected to photolithographic patterning.
Optionally, the method further comprises: a passivation layer 18 is formed on the insulating layer 15 and the electrode layer 16 by means of plasma-enhanced chemical vapor deposition. By annealing in an inert gas atmosphere such as nitrogen, hydrogen in the passivation layer 18 diffuses into the semiconductor layer 14, and hydrogen doping of the semiconductor layer 14 between the source and drain is achieved to improve conductivity.
FIGS. 5, 6 and 7 show TFT saturation threshold networks of different configurations, with R on the source side cs1 ＞＞R cs2 +R cs3 On the drain side, there is R cs1 ＞＞R cd2 Therefore, the saturated output current of the device is I dsat ≈V dsat /(R cs2 +R cs3 +R cd2 ) The saturation voltage of the device is:
the thin film transistors of FIGS. 5-7 can adjust R by adjusting ΔL cs3 Or by hydrogen doping through the metal oxide channel layer, R is changed ch The saturated output current and the saturated output voltage of the device are regulated and controlled through the adjustment of the resistance values.
For a better explanation of the scheme of the present application, a schottky barrier InGaZnO thin film transistor based on copper source/drain electrodes as shown in fig. 8 will be exemplified.
Please refer to fig. 8, which shows a schottky barrier InGaZnO thin film transistor based on copper source/drain electrodes. The film layer structure of the thin film transistor sequentially comprises a patterned aluminum gate electrode, an aluminum oxide gate dielectric layer, a patterned InGaZnO semiconductor layer, a patterned aluminum oxide insulating layer and a patterned copper source/drain electrode according to the deposition sequence on a glass substrate, wherein the thickness of the InGaZnO semiconductor layer is 30nm, and the thickness of the aluminum oxide insulating layer is 3nm. The preparation process of the thin film transistor comprises the following steps:
first, an aluminum electrode was sputter deposited on a glass substrate and lithographically patterned as a gate electrode.
And then, growing an alumina gate dielectric layer with the thickness of 200nm on the surface of the aluminum gate by adopting an anodic oxidation method.
And preparing an InGaZnO film with the thickness of 30nm by adopting magnetron sputtering, performing photoetching patterning, and annealing the patterned InGaZnO film under the air condition of 450 ℃.
Further, an alumina layer with the thickness of 3nm is deposited by sputtering, the alumina layer is subjected to photoetching patterning, and the patterned alumina layer is annealed under the air condition of 350 ℃.
Then, a Cu electrode with the thickness of 200nm is deposited by sputtering, a Cu source/drain electrode is obtained by photoetching, and the whole device is annealed for 10min in a nitrogen atmosphere at 250 ℃, wherein the Schottky barrier in contact with Cu/InGaZnO is 0.45eV, and Cu/AlO x The schottky barrier of the InGaZnO contact was 0.78eV (as shown in fig. 9).
Finally, a 100nm thick passivation layer of silicon nitride was deposited by PECVD and annealed in a nitrogen atmosphere at 250℃for 10min. As shown in fig. 10, the output characteristics of the thin film transistor are shown in V gs Under the condition of=20v, the saturation voltage V of the thin film transistor dsat And < 3V, and the saturation of the thin film transistor has more stable output current.
The application at least comprises the following beneficial effects:
provided is a Schottky barrier thin film transistor including: the semiconductor device comprises a substrate, a gate electrode layer, a gate dielectric layer, a semiconductor layer, an insulating layer and an electrode layer, wherein the electrode layer comprises a source electrode and a drain electrode. By adopting the non-noble metal source-drain electrode, the preparation cost of the device is greatly reduced; by arranging the metal oxide insulating layer, the direct contact between metal and the semiconductor layer is avoided, so that a Schottky barrier closer to a theoretical value is formed, and the defect state formed by contact is reduced; by forming an ohmic contact region and a Schottky barrier contact region at the source/drain electrode simultaneously, the Schottky barrier thin film transistor is ensured to have higher saturation output current density and lower saturation voltage.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present application should be included in the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A schottky barrier thin film transistor, comprising: the semiconductor device comprises a substrate, a gate electrode layer, a gate dielectric layer, a semiconductor layer, an insulating layer and an electrode layer, wherein the electrode layer comprises a source electrode and a drain electrode;
the insulating layer is a metal oxide insulating layer, the semiconductor layer is a metal oxide semiconductor layer, and the gate layer, the insulating layer, the semiconductor layer and the electrode layer are patterned by photoetching;
the insulating layer is used as an etching barrier layer of the semiconductor layer and is also used as a regulating and controlling functional layer of the Schottky contact barrier between the electrode layer and the semiconductor layer;
the electrode layer is in partial direct contact with the semiconductor layer and in partial direct contact with the insulating layer.
2. The schottky barrier thin film transistor of claim 1 wherein the electrode layer is in direct contact with the semiconductor layer to form a schottky barrier that is smaller than the schottky barrier formed between the electrode layer, the insulating layer, and the semiconductor layer.
3. The schottky barrier thin film transistor of claim 2 wherein a silicon nitride passivation layer is disposed over the insulating layer and the electrode layer to enhance conductivity of the semiconductor layer between the source electrode and the drain electrode.
4. The schottky barrier thin film transistor of claim 1 wherein the source electrode and the drain electrode are stacked electrodes and the source electrode and the drain electrode are each comprised of a first work function metal and a second work function metal;
the first work function metal is deposited prior to the second work function metal;
a part of the first work function metal is in direct contact with the semiconductor layer, the other part of the first work function metal is in direct contact with the insulating layer, and the second work function metal is in direct contact with the insulating layer;
ohmic contact or quasi-ohmic contact is formed between the first work function metal and the semiconductor layer, ohmic contact or quasi-ohmic contact is formed among the first work function metal, the insulating layer and the semiconductor layer, and Schottky contact is formed among the second work function metal, the insulating layer and the semiconductor layer.
5. The schottky barrier thin film transistor according to any one of claims 1 to 4, wherein the thickness of the semiconductor layer is 10 to 200nm, and the thickness of the insulating layer is less than or equal to 10 nm.
6. The schottky barrier thin film transistor according to any one of claims 1 to 4, wherein the semiconductor layer is made of InGaZnO, inZnO, inZnSnO, ln to IZO, inGaO, znO, ga 2 O 3 Or SnO 2 Any one of them;
the insulating layer is made of Al 2 O 3 、SiO 2 、HfO 2 Or ZrO(s) 2 Any one of them;
the electrode layer is made of one or two of Cu, mo, al, ti, ni, W and Cr or one or two of Cu, mo, al, ti, ni, W and Cr alloy.
7. A method of fabricating a schottky barrier thin film transistor, the method comprising:
providing a substrate, depositing a gate layer on the substrate by a sputtering mode, and carrying out photoetching patterning on the gate layer;
forming a gate dielectric layer on the gate electrode layer by means of plasma enhanced chemical vapor deposition;
preparing a semiconductor layer on the gate dielectric layer by means of magnetron sputtering or atomic layer deposition, and performing photoetching patterning on the semiconductor layer, wherein the semiconductor layer is a metal oxide semiconductor layer;
preparing an insulating layer on the semiconductor layer by means of magnetron sputtering or atomic layer deposition, and performing photoetching patterning on the insulating layer, wherein the insulating layer is a metal oxide insulating layer;
and depositing metal on the insulating layer and photoetching and patterning to form an electrode layer to obtain the Schottky barrier thin film transistor, wherein the electrode layer comprises a source electrode and a drain electrode.
8. The schottky barrier thin film transistor fabrication method of claim 7, further comprising:
the semiconductor layer is treated with an argon plasma to convert the semiconductor layer not covered by the insulating layer into a conductor.
9. The method of manufacturing a schottky barrier thin film transistor according to claim 7, wherein the source electrode and the drain electrode are stacked electrodes, and the source electrode and the drain electrode are each composed of a first work function metal and a second work function metal; the method further comprises the steps of:
depositing a first work function metal layer on the semiconductor layer and the insulating layer, and carrying out photoetching patterning on the first work function metal layer;
and depositing a second work function metal layer on the insulating layer, and carrying out photoetching patterning on the second work function metal layer.
10. The schottky barrier thin film transistor fabrication method of claim 7, further comprising:
forming a silicon nitride passivation layer on the insulating layer by means of plasma enhanced chemical vapor deposition, or sequentially depositing silicon dioxide and the silicon nitride passivation layer by means of plasma enhanced chemical vapor deposition;
and annealing is carried out in an inert gas atmosphere, so that hydrogen in the silicon nitride passivation layer is diffused into the semiconductor layer, and the conductivity of the semiconductor layer is improved.
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