CN116564939A - Wafer structure - Google Patents
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- CN116564939A CN116564939A CN202310484939.9A CN202310484939A CN116564939A CN 116564939 A CN116564939 A CN 116564939A CN 202310484939 A CN202310484939 A CN 202310484939A CN 116564939 A CN116564939 A CN 116564939A
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- wafer structure
- conducting
- conductive line
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- 239000004065 semiconductor Substances 0.000 claims abstract description 85
- 238000012216 screening Methods 0.000 claims abstract description 18
- 238000005520 cutting process Methods 0.000 claims abstract description 4
- 238000012360 testing method Methods 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 238000011056 performance test Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The application discloses a wafer structure. The wafer structure comprises: a wafer body provided with dicing streets and comprising a plurality of semiconductor devices defined by the dicing streets, the semiconductor devices comprising three electrode portions of at least two different electrode types; the conducting layer is formed on the wafer main body and comprises a plurality of conducting discs corresponding to the semiconductor devices and conducting wires connected with the conducting discs, the conducting wires are arranged in the cutting channels, the conducting discs comprise three conducting parts, the conducting parts are corresponding to the electrode parts and are electrically connected, and the conducting parts corresponding to the electrode parts of the same electrode type are connected by the same conducting wires. Through the mode, the wafer structure provided by the application can remarkably reduce the cost of early failure screening of the semiconductor device and improve the screening efficiency.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a wafer structure.
Background
Burn-in testing plays a very important role in semiconductor development. The primary purpose of the burn-in test is to predict and evaluate the performance degradation of a semiconductor component during long term use. By performing burn-in testing, engineers can determine the reliability and long-term stability of the semiconductor assembly. Burn-in testing may also help improve the design of semiconductor components, thereby improving their reliability during use.
The ying fei ling designs a test machine which can test a large number of samples simultaneously, and the method of screening out early failures simultaneously in a low-pressure (36V) mode is named as Marathon stress test.
Many experiments prove that early electrical failures are caused by interface defects, and the early failures must be shaved before entering the burn-in test, otherwise whether the early electrical failures pass the burn-in test cannot be judged, and samples with early electrical failures can cause erroneous judgment during the burn-in test and need to be removed before entering the burn-in test.
This is because the number of early failures of the sample is very low, so a large number of burn-in samples must be tested simultaneously to detect one or two early failed samples. To achieve a yield on the ppm scale, at least 1000 samples should be tested before one will appear.
And the adoption of the Yingfei scheme has the advantage that the equipment cost is too high; or early failure detection is carried out on the aging test samples one by one, the consumed time and cost are extremely high, and the efficiency is extremely low.
Disclosure of Invention
The application mainly provides a wafer structure to solve the problem that the cost of semiconductor device early failure screening is high and inefficiency.
In order to solve the technical problems, one technical scheme adopted by the application is as follows: a wafer structure is provided. The wafer structure comprises: a wafer body provided with dicing streets and comprising a plurality of semiconductor devices defined by the dicing streets, the semiconductor devices comprising three electrode portions of at least two different electrode types; the conducting layer is formed on the wafer main body and comprises a plurality of conducting discs corresponding to the semiconductor devices and conducting wires connected with the conducting discs, the conducting wires are arranged in the cutting channels, the conducting discs comprise three conducting parts, the conducting parts are corresponding to the electrode parts and are electrically connected, and the conducting parts corresponding to the electrode parts of the same electrode type are connected by the same conducting wires.
In some embodiments, the conductive portion has an area greater than an area of the corresponding electrode portion, and the conductive portion entirely covers the corresponding electrode portion.
In some embodiments, a portion of the conductive portion is located in the scribe line and connected to the corresponding conductive line.
In some embodiments, different ones of the conductive lines within a same one of the dicing lanes are insulated by a gap therebetween; or (b)
Different ones of the conductive lines within the same scribe line are insulated from each other by a dielectric layer.
In some embodiments, the wafer structure further includes a dielectric layer disposed on the scribe line, the dielectric layer is flush with two electrode portions of the same layer of the three electrode portions, and the conductive line is disposed on the dielectric layer.
In some embodiments, the conductive layer is a metal layer.
In some embodiments, the semiconductor device is a planar semiconductor device, the three electrode portions include a gate electrode and two source electrodes, the conductive lines include a first conductive line and a second conductive line, the conductive portion corresponding to the gate electrode on the semiconductor device is connected to the first conductive line, and the two conductive portions corresponding to the two source electrodes on the semiconductor device are connected to the second conductive line.
In some embodiments, the first conductive line and the second conductive line connected to the same semiconductor device are located in different dicing lanes.
In some embodiments, the semiconductor device is a vertical semiconductor, the three electrode portions include a gate electrode, a source electrode, and a drain electrode, the conductive lines include a first conductive line, a second conductive line, and a third conductive line, the conductive portion corresponding to the gate electrode is connected to the first conductive line, the conductive portion corresponding to the source electrode is connected to the second conductive line, and the conductive portion corresponding to the drain electrode is connected to the third conductive line.
In some embodiments, the wafer structure is applied to an early failure screening test, the conductive lines on the wafer structure serving as inputs for an early failure screening voltage.
The beneficial effects of this application are: unlike the prior art, the present application discloses a wafer structure. The conductive layer is formed on the wafer main body and comprises a plurality of conductive plates corresponding to the semiconductor devices in the wafer main body and conductive wires connected with the conductive plates, the conductive wires are arranged on the cutting channels of the wafer main body, the conductive plates comprise conductive parts corresponding to the electrode parts of the semiconductor devices, the conductive parts corresponding to the electrode parts of the same electrode type are connected by the same conductive wires, the conductive wires can serve as voltage input ends, and under a specific environment, the voltage is input through the conductive wires, so that a large number of semiconductor devices contained in the wafer main body can be directly screened out from the devices with early failure defects, and compared with the method of adopting expensive equipment or processing test one by one, the scheme of the application can remarkably reduce screening cost and improve screening efficiency.
Drawings
For a clearer description of embodiments of the present application or of the solutions of the prior art, the drawings that are required to be used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are only some embodiments of the present application, and that other drawings may be obtained, without inventive effort, by a person skilled in the art from these drawings, in which:
FIG. 1 is a schematic diagram of an embodiment of a wafer structure provided herein;
FIG. 2 is a schematic view of a wafer body in the wafer structure of FIG. 1;
FIG. 3 is a schematic view of the structure of the semiconductor device in the wafer body shown in FIG. 2;
fig. 4 is a schematic top view of a partial area of the wafer structure of fig. 1.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms "first," "second," "third," and the like in the embodiments of the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1 to 4, fig. 1 is a schematic structural diagram of an embodiment of a wafer structure provided in the present application, fig. 2 is a schematic structural diagram of a wafer body in the wafer structure shown in fig. 1, fig. 3 is a schematic structural diagram of a semiconductor device in the wafer body shown in fig. 2, and fig. 4 is a schematic structural diagram of a top view of a partial region in the wafer structure shown in fig. 1. Fig. 1 is a schematic cross-sectional view of a wafer structure 100, and fig. 2 is a schematic top view of a wafer body 10.
Referring to fig. 1 to 4, the wafer structure 100 includes a wafer body 10 and a conductive layer 20, wherein the wafer body 10 is provided with scribe lines 12 and includes a plurality of semiconductor devices 14 defined by the scribe lines 12, the semiconductor devices 14 include three electrode portions 142, and the three electrode portions 142 are at least two different electrode types; the conductive layer 20 is formed on the wafer body 10, and includes a plurality of conductive pads 22 corresponding to the semiconductor devices 14 and conductive wires 24 connected to the plurality of conductive pads 22, the conductive wires 24 are disposed on the scribe line 12, the conductive pads 22 include three conductive portions 222, the conductive portions 222 are corresponding to the electrode portions 142 and electrically connected, and the conductive portions 222 corresponding to the electrode portions 142 of the same electrode type are connected by using the same conductive wires 24.
As shown in fig. 2 and 3, the wafer body 10 is formed on a wafer by vapor deposition, metallization, photolithography, etching, doping, planarization, and the like. The wafer body 10 includes a plurality of semiconductor devices 14 defined by streets 12. In this embodiment, the plurality of semiconductor devices 14 are arranged in an array, and the streets 12 include a plurality of streets 120 arranged in a vertically intersecting manner in a plurality of rows and a plurality of columns
In other embodiments, the distribution form of the scribe line 12 and the outline shape of the semiconductor device 14 may be other forms, which is not particularly limited in this application.
Three electrode portions 142 are located on top of the semiconductor device 14, the three electrode portions 142 being of at least two different electrode types, e.g. one electrode portion 142 being the gate electrode 124 and the other two electrode portions 142 being the source electrode 122, or the three electrode portions 142 being the gate electrode 124, the source electrode 122 and the drain electrode 126, respectively.
As shown in fig. 3, in the present embodiment, the semiconductor device 14 is a planar semiconductor device, in which two source electrodes 122 may be formed on a wafer substrate by diffusion or ion implantation, a gate insulating layer is formed on the two source electrodes 122 by chemical vapor deposition, a gate electrode 124 is formed on the gate insulating layer by physical vapor deposition, and a drain electrode 126 is formed on a side of the wafer substrate facing away from the gate electrode 124, wherein the gate electrode 124 and the two source electrodes 122 form three electrode portions 142.
Alternatively, the semiconductor device 14 may be a vertical semiconductor device, in which the active electrode 122 and the drain electrode 126 are formed on a wafer substrate by diffusion or ion implantation, and the gate insulating layer and the gate electrode 124 are formed on the active electrode 122 and the drain electrode 126, respectively, and the active electrode 122, the drain electrode 126, and the gate electrode 124 form three electrode portions 142.
As shown in fig. 1, the conductive layer 20 is formed on the wafer body 10, and the conductive layer 20 may be a metal layer, for example, copper, aluminum, or a metal alloy, or may be a transparent metal oxide, for example, ITO (indium tin oxide), which is not particularly limited in this application.
In this embodiment, the conductive layer 20 is a metal layer formed on the semiconductor device 14 by physical vapor deposition.
Referring to fig. 1 to 4 in combination, the conductive layer 20 includes a plurality of conductive pads 22 disposed corresponding to the semiconductor device 14 and conductive lines 24 connected to the plurality of conductive pads 22, the conductive pads 22 are disposed corresponding to the semiconductor device 14 one by one, the conductive lines 24 are disposed on the scribe line 12, wherein the conductive pads 22 include three conductive portions 222, the three conductive portions 222 are disposed corresponding to and electrically connected to the three electrode portions 142, and the conductive portions 222 corresponding to the electrode portions 142 of the same electrode type are connected by using the same conductive lines 24.
In this embodiment, the semiconductor device 14 is a planar semiconductor device, the three electrode portions 142 include the gate electrode 124 and the two source electrodes 122, the conductive line 24 is divided into a first conductive line 241 and a second conductive line 242, the conductive layer 20 includes a plurality of conductive pads 22, and the first conductive line 241 and the second conductive line 242, the conductive portion 222 of each conductive pad 22 corresponding to the gate electrode 124 on the semiconductor device 14 is connected to the first conductive line 241, and the two conductive portions 222 of each conductive pad 22 corresponding to the two source electrodes 122 on the semiconductor device 14 are connected to the second conductive line 242. Wherein the different conductive lines 24 on the same scribe line 12 are insulated from each other, i.e., the first conductive line 241 and the second conductive line 242 are insulated from each other.
Alternatively, the semiconductor device 14 is a vertical semiconductor, the three electrode portions 142 include the gate electrode 124, the source electrode 122 and the drain electrode 126, the conductive line 24 is divided into a first conductive line 241, a second conductive line 242 and a third conductive line (not shown), the conductive layer 20 includes a plurality of conductive pads 22 and the first conductive line 241, the second conductive line 241 and the third conductive line, each conductive portion 222 of the conductive pads 22 corresponding to the gate electrode 124, the source electrode 122 and the drain electrode 126 on the same semiconductor device 14 is connected to a different conductive line 24, that is, each conductive portion 222 of the conductive pads 22 corresponding to the gate electrode 124 on the semiconductor device 14 is connected to the first conductive line 241, each conductive portion 222 of the conductive pads 22 corresponding to the source electrode 122 on the semiconductor device 14 is connected to the second conductive line 242, and each conductive portion 222 of the conductive pads 22 corresponding to the drain electrode 126 on the semiconductor device 14 is connected to the third conductive line. Wherein the different conductive lines 24 on the same scribe line 12 are isolated from each other, i.e., the first conductive line 241, the second conductive line 242, and the third conductive line are isolated from each other.
In the present embodiment, the semiconductor devices 14 on the wafer body 10 are arranged in an array, and the conductive portions 222 corresponding to the electrode portions 142 of the same electrode type are respectively connected to a conductive wire 24 in the plurality of conductive pads 22 corresponding to the semiconductor devices 14 of the same row or column.
Specifically, the semiconductor device 14 is a planar semiconductor device, only two conductive lines 24 need to be disposed on the scribe line 12 distributed along the row or the column, the two conductive lines 24 are a first conductive line 241 and a second conductive line 242, respectively, and the plurality of first conductive lines 241 distributed along the row or the column are connected to each other at the tail end, and the plurality of second conductive lines 244 distributed along the row or the column are connected to each other at the tail end.
The first conductive wires 241 and the second conductive wires 242 connected to the semiconductor devices 14 in the same row or the same column are respectively located in different dicing channels 12, so that wiring is convenient, the first conductive wires 241 and the second conductive wires 242 are prevented from crossing, and wiring difficulty of the conductive wires 24 is reduced.
Further, different conductive lines 24 located within the same scribe line 12 are insulated from each other. Specifically, different conductive lines 24 located within the same scribe line 12 are insulated by gaps therebetween; or different conductive lines 24 within the same scribe line 12 are insulated from each other by dielectric layers, which may be made of silicon dioxide or silicon nitride.
As shown in fig. 4, in the present embodiment, the area of the conductive portion 222 is larger than the area of the corresponding electrode portion 142, and the conductive portion 222 fully covers the corresponding electrode portion 142, so as to improve the electrical connection stability of the conductive portion 222 and the corresponding electrode portion 142, thereby ensuring stable voltage charging of each semiconductor power device 14 during the burn-in test.
Further, the portion of the conductive portion 222 is located in the scribe line 12 and connected to the corresponding conductive line 24, that is, the portion of the conductive portion 222 located in the scribe line 12 is connected to the corresponding conductive line 24 after the conductive portion 222 covers the corresponding electrode portion 142, so that the position of the conductive line 24 is isolated from the position of the semiconductor device 14, and the situation that the same conductive line 24 applies voltages to the electrode portions 142 with different electrode types on the semiconductor device 14 is effectively avoided.
Further, referring to fig. 1, the wafer structure 100 further includes a dielectric layer 16 disposed on the scribe line 12, the dielectric layer 16 is flush with two electrode portions 142 located on the same layer of the three electrode portions 142, and the conductive line 24 is disposed on the dielectric layer 16.
It will be appreciated that the height of the scribe line 12 is smaller than the height of the two electrode portions 142 located on the same layer of the semiconductor device 14, so that a certain height difference is formed between the scribe line 12 and the semiconductor device 14, and when the conductive layer 20 is directly formed on the scribe line 12 itself, more material cost and manufacturing process time are consumed.
The dielectric layer 16 has insulating properties, and can be made of silicon dioxide or silicon nitride by vapor deposition, etc., and the conductive line 24 and a portion of the conductive portion 222 are located on the dielectric layer 16, and can be insulated from the rest of each semiconductor device 14, so that the interference can be effectively reduced.
The wafer structure 100 is used for early failure screening test, and the conductive wire 24 on the wafer structure 100 is used as an input terminal of early failure screening voltage. Referring to fig. 3 and 4, the conductive portion 222 corresponding to the gate electrode 124 is connected to the first conductive line 241, and the first conductive line 241 is connected to a low voltage, which may be twice the gate operating voltage; the corresponding conductive portions 222 of the two source electrodes 122 are connected to the second conductive line 242, and the second conductive line 242 is grounded; drain electrode 126 is a planar electrode common to each semiconductor device 14 that may be tied to a high voltage, for example, 650V to 1200V, which may be a voltage value that may be based on the particular situation.
Optionally, the semiconductor device 14 is a vertical semiconductor, and the first conductive line 241 on the wafer structure 100 is connected to a low voltage, the second conductive line 242 is grounded, and the third conductive line is connected to a high voltage, which will not be described again.
The semiconductor devices 14 in the wafer structure 100 are subjected to early failure rejection before burn-in testing, and the early failure rejection is performed by applying low voltage to the wafer structure 100 in a high-temperature environment and continuously operating for a preset period of time such as 100 hours, so that the pretreatment of early failure screening is completed, and the degradation of the semiconductor devices 14 with early failure defects in the semiconductor devices 14 is more serious, so that the semiconductor devices 14 with early failure can be conveniently and directly selected out through subsequent electrical detection, and rejection is completed.
The wafer structure 100 provided in the present application can be used for performing the pretreatment of early failure screening on the plurality of semiconductor devices 14 included in the wafer structure at the same time, and forming the conductive layer 20 on the wafer main body 10 by adding a layer of photomask in the process, and the photomask can be reused, so that the voltage can be applied to each semiconductor device 14 on the photomask at the same time, compared with the method of adopting expensive equipment or processing the test one by one, the scheme of the present application can significantly reduce the screening cost and improve the screening efficiency.
In the pre-processing of early failure screening, the wider conductive wires 24 are properly arranged, and the conductive wires 24 at a plurality of positions on the wafer structure 100 are electrified, so that the end voltages of the tested semiconductor devices 14 are basically the same, and the influence on the subsequent screening precision due to the difference of the testing voltages of the semiconductor devices 14 is avoided.
It should be noted that the individual semiconductor devices 14 are connected in parallel during the burn-in test, and each semiconductor device 14 must be isolated and tested independently when confirming the performance test of the semiconductor device 14, so that the manner in which the semiconductor device 14 is biased during the performance test is different from the burn-in test.
The foregoing description is only exemplary embodiments of the present application and is not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the present application.
Claims (10)
1. A wafer structure, comprising:
a wafer body provided with dicing streets and comprising a plurality of semiconductor devices defined by the dicing streets, the semiconductor devices comprising three electrode portions of at least two different electrode types;
the conducting layer is formed on the wafer main body and comprises a plurality of conducting discs corresponding to the semiconductor devices and conducting wires connected with the conducting discs, the conducting wires are arranged in the cutting channels, the conducting discs comprise three conducting parts, the conducting parts are corresponding to the electrode parts and are electrically connected, and the conducting parts corresponding to the electrode parts of the same electrode type are connected by the same conducting wires.
2. The wafer structure of claim 1, wherein the conductive portions have an area greater than an area of the corresponding electrode portions, and the conductive portions fully cover the corresponding electrode portions.
3. The wafer structure of claim 2, wherein a portion of the conductive portion is located in the scribe line and connected to the corresponding conductive line.
4. The wafer structure of claim 1, wherein different ones of the conductive lines within a same scribe line are insulated by a gap therebetween; or (b)
Different ones of the conductive lines within the same scribe line are insulated from each other by a dielectric layer.
5. The wafer structure of claim 1, further comprising a dielectric layer disposed on the scribe line, the dielectric layer being flush with two of the electrode portions of the same layer of the three electrode portions, the conductive line being disposed on the dielectric layer.
6. The wafer structure of claim 1, wherein the conductive layer is a metal layer.
7. The wafer structure according to claim 1, wherein the semiconductor device is a planar semiconductor device, the three electrode portions include a gate electrode and two source electrodes, the conductive lines include a first conductive line and a second conductive line, the conductive portion corresponding to the gate electrode on the semiconductor device is connected to the first conductive line, and the two conductive portions corresponding to the two source electrodes on the semiconductor device are connected to the second conductive line.
8. The wafer structure of claim 7, wherein the first conductive line and the second conductive line connected to the same semiconductor device are located in different scribe lanes.
9. The wafer structure according to claim 1, wherein the semiconductor device is a vertical semiconductor, the three electrode portions include a gate electrode, a source electrode, and a drain electrode, the conductive lines include a first conductive line, a second conductive line, and a third conductive line, the conductive portion corresponding to the gate electrode is connected to the first conductive line, the conductive portion corresponding to the source electrode is connected to the second conductive line, and the conductive portion corresponding to the drain electrode is connected to the third conductive line.
10. The wafer structure of claim 1, wherein the wafer structure is used for early failure screening testing, and the conductive lines on the wafer structure serve as inputs for early failure screening voltages.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310484939.9A CN116564939A (en) | 2023-04-28 | 2023-04-28 | Wafer structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310484939.9A CN116564939A (en) | 2023-04-28 | 2023-04-28 | Wafer structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116564939A true CN116564939A (en) | 2023-08-08 |
Family
ID=87492506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310484939.9A Pending CN116564939A (en) | 2023-04-28 | 2023-04-28 | Wafer structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116564939A (en) |
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2023
- 2023-04-28 CN CN202310484939.9A patent/CN116564939A/en active Pending
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