CN211206583U - Wafer test probe card - Google Patents
Wafer test probe card Download PDFInfo
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- CN211206583U CN211206583U CN201920908482.9U CN201920908482U CN211206583U CN 211206583 U CN211206583 U CN 211206583U CN 201920908482 U CN201920908482 U CN 201920908482U CN 211206583 U CN211206583 U CN 211206583U
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- probe card
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- electrical conductor
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- 238000012360 testing method Methods 0.000 title claims abstract description 124
- 239000000523 sample Substances 0.000 title claims abstract description 49
- 239000004020 conductor Substances 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 239000011889 copper foil Substances 0.000 claims description 11
- 238000013522 software testing Methods 0.000 abstract description 5
- 235000012431 wafers Nutrition 0.000 description 26
- 230000003071 parasitic effect Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 241001424392 Lucia limbaria Species 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Measuring Leads Or Probes (AREA)
Abstract
The utility model provides a wafer test probe card, which comprises a substrate, wherein the surface of the substrate is provided with an inner circle area and an outer ring area, and the radius of the inner circle area is smaller than the ring width of the outer ring area; the inner circle region is annularly provided with a first path of electric conductor consisting of more than two paths of test channels, and each test channel in the first path of electric conductor is annularly distributed in the inner circle region; and a second path of electric conductor consisting of more than two paths of test channels is arranged in the outer ring area in a ring mode, and each test channel in the second path of electric conductor is distributed in a columnar mode from the edge of the inner circular area to the edge of the substrate. Through the utility model discloses can increase with surveying quantity, improve efficiency of software testing, prolong the life of probe card, improve the test precision.
Description
Technical Field
The utility model relates to a semiconductor test technical field, more specifically relates to a wafer test probe card.
Background
The wafer refers to a silicon wafer used for manufacturing a silicon semiconductor integrated circuit, and is called a wafer because the shape is circular; various circuit element structures can be processed on a silicon wafer to form an IC product with specific electrical functions. The wafer is a core element in a semiconductor device and needs to be subjected to very strict technical test, which mainly verifies whether a product circuit is good or not and verifies whether the function of the driving wafer meets the requirements of terminal application or not.
Probe cards are often used in the industry to test wafers for the purpose of signal transmission between the test equipment and the wafer. Namely: through the probe contact arranged on the probe card, one end of the probe is contacted with the contact, the other end of the probe is contacted with the metal pad on the chip to be tested, and the automatic test is completed by matching with a test instrument and related software. Conventional wafer test probe cards currently provide 48 sets of electrical test channels, but use a wider layout. In the production process, a large-area plate is easily warped and uneven due to temperature change due to uneven stress, so that the test efficiency is reduced, the life cycle of the probe card is shortened, and leakage current and small parasitic capacitance are generated.
Therefore, in order to increase the number of simultaneous tests, improve the testing efficiency, prolong the service life of the probe card, and improve the testing accuracy, there is a need to improve the conventional wafer testing probe card.
SUMMERY OF THE UTILITY MODEL
In view of the above problems, an object of the present invention is to provide a wafer test probe card to solve the problems of low test efficiency and short life span of the conventional wafer test probe card.
The utility model provides a wafer test probe card, which comprises a substrate, wherein the surface of the substrate is provided with an inner circle area and an outer ring area, and the radius of the inner circle area is smaller than the ring width of the outer ring area; the inner circle region is internally and annularly provided with a first path of electric conductor consisting of more than two paths of test channels, and each test channel in the first path of electric conductor is annularly distributed in the inner circle region; and a second path of electric conductor consisting of more than two paths of test channels is annularly arranged in the outer ring area, and each test channel in the second path of electric conductor is distributed in a columnar manner from the edge of the inner circular area to the edge of the substrate.
Further, a preferable structure is: and a contact point contacted with the probe is arranged on each test channel of the first path of electric conductor and the second path of electric conductor, and a grounding contact point is arranged on each test channel of the second path of electric conductor.
Further, a preferable structure is: the ring shape is a perfect circle; the column is a rod-shaped column or a square column which is gradually enlarged from inside to outside.
Further, a preferable structure is: and each test channel of the first path of electric conductor and the second path of electric conductor is a copper foil.
Further, a preferable structure is: and a first anti-interference layer is arranged on each test channel of the second path of electric conductors, and the first anti-interference layers are longitudinally arranged on each test channel of each second path of electric conductors.
Further, a preferable structure is: and a second anti-interference layer is arranged on the substrate positioned in the outer ring area and is arranged among the test channels of the second path of electric conductors.
Further, a preferable structure is: the second anti-interference layer is annular or rectangular.
Further, a preferable structure is: the first anti-interference layer is an area milled on the copper foil.
Further, a preferable structure is: each test channel in the first path of electric conductor is distributed in the inner circle area in a first preset line width and a first preset interval; and the test channels in the second path of electric conductors are distributed in the outer ring area by a second preset line width and a second preset distance.
Further, a preferable structure is: the number of the test channels of the first path of electric conductors is equal to that of the test channels of the second path of electric conductors.
Utilize the aforesaid to according to the utility model discloses a wafer test probe card sets up two way electric conductors through the surface at the base plate, and each way electric conductor comprises multichannel test channel to increase with surveying quantity, improve efficiency of software testing, prolong the life of probe card, improve the test precision.
Drawings
Other objects and results of the present invention will become more apparent and more readily appreciated as the same becomes better understood by reference to the following description and appended claims, taken in conjunction with the accompanying drawings.
In the drawings:
fig. 1 is a schematic diagram illustrating an overall structure of a wafer test probe card according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a partially enlarged structure of a wafer test probe card according to an embodiment of the present invention.
The same reference numbers in all figures indicate similar or corresponding features or functions.
In the figure: the device comprises a substrate 1, an inner circle region 2, test channels 21 of a first path of electric conductors, an outer ring region 3, test channels 31 of a second path of electric conductors, a contact 4, a first anti-interference layer 5, a second anti-interference layer 6 and a grounding contact 7.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
The test channel that provides to aforementioned present wafer test probe card is few, and efficiency of software testing is low, probe card life cycle is short, and easily produces the problem of leaking current and small parasitic capacitance, the utility model discloses a set up two way electric conductors on the surface of base plate, each way electric conductor comprises multichannel test channel, and the test channel in each way electric conductor all distributes in order to predetermineeing the shape to increase with surveying quantity, improve efficiency of software testing, the life of extension probe card improves the test precision.
To illustrate the wafer test probe card provided by the present invention, fig. 1 shows an overall structure according to an embodiment of the present invention, and fig. 2 shows a local amplification structure according to an embodiment of the present invention.
As shown in fig. 1 and fig. 2, the wafer test probe card provided by the present invention includes a substrate 1, wherein an inner circle region 2 and an outer ring region 3 are disposed on the surface of the substrate 1, and the radius of the inner circle region 2 is smaller than the ring width of the outer ring region 3; wherein, a first path of electric conductor consisting of more than two paths of test channels is annularly arranged in the inner circle region 2, and each test channel 21 in the first path of electric conductor is annularly distributed in the inner circle region 2; the inner ring of the outer ring area 3 is provided with a second path of electric conductor consisting of more than two paths of test channels, and each test channel 31 in the second path of electric conductor is distributed in a columnar shape from the edge of the inner ring area 2 to the edge of the substrate.
That is, two annular regions (i.e., an inner circular region and an outer circular region) are divided on the surface of the substrate 1, and both of the two annular regions are concentric with the substrate, wherein the radius of the substrate minus the radius of the inner circular region is the ring width of the outer circular region. A first path of electric conductor consisting of a plurality of paths of test channels is annularly distributed in the inner circular area, and a second path of electric conductor consisting of a plurality of paths of test channels is annularly distributed in the outer circular area; each test channel in the first path of electric conductor is annular and is distributed in the inner circle area by a first preset line width and a first preset interval; each test channel in the second path of electric conductor is columnar, and each test channel in the second path of electric conductor is distributed from the edge of the inner circle area to the edge of the substrate by a second preset line width and a second preset interval. Therefore, in order to increase the number of simultaneous tests, the line width of each test channel can be made very small, and the space between the test channels is also made very small, so that the number of the test channels distributed in the inner circle area and the outer ring area is increased, however, the line width of each test channel cannot be reduced unlimitedly, because the too narrow line width is easily affected by external force to cause circuit breaking, and the service life of the probe card is affected, therefore, taking a substrate with the diameter of 245mm as an example, the line width of each test channel in the inner circle area is set to be 2.4mm, and the space between the test channels is set to be 0.49 mm; the line width of each test channel in the outer ring area is set to be 5.3mm, and the space between the test channels is set to be 5.38mm, so that the best effect can be achieved. It should be noted that the line width of each test channel and the distance between the test channels need to be determined according to the diameter of the substrate and the number of the test channels distributed in the inner circle region and the outer ring region.
Furthermore, each test channel 21 of the first path of electrical conductor and each test channel 31 of the second path of electrical conductor are provided with a contact 4 contacted with the probe, and the contact 4 is contacted with the probe, so that the chip to be tested and the wafer test probe card are electrically conducted, and the test with the chip to be tested is completed; and a ground contact 7 is arranged on each test channel of the second path of electrical conductors.
Each test channel 21 in the first path of electrical conductor is a perfect circle, each test channel 31 in the second path of electrical conductor is a column, and the column is a rod-shaped column or a square column which is gradually enlarged from inside to outside, and the meaning that the column is gradually enlarged from inside to outside means that the column is gradually enlarged from the edge of the inner circle area to the edge of the substrate; in this embodiment, each test channel in the first electrical conductor is circular, and the optimal length thereof is 2.4mm, and each test channel in the second electrical conductor is cylindrical, and the optimal length thereof is 85.79mm, so that the test effect and the service life of the wafer test probe card can be optimal.
Further, each test channel 21 in the first electrical conductor and the test channel 31 in the second electrical conductor are both copper foils for facilitating electrical conduction. The first anti-interference layer 5 is arranged on each test channel 31 of the second path of electric conductors, and the arrangement of the first anti-interference layer 5 can reduce electromagnetic interference generated when current conducted through the probe is concentrated on a copper foil with a small area, and reduce the occurrence probability of leakage current and small parasitic capacitance.
The first interference suppression layer 5 is arranged longitudinally on each test channel of the second path of electric conductors. Furthermore, a second interference rejection layer 6 is arranged on the substrate in the outer ring region, which second interference rejection layer 6 is arranged between the test channels of the second electrical conductor. Specifically, the second anti-interference layer is annular or rectangular. The first anti-interference layer 5 is a region milled on the copper foil, and may be a groove formed on the copper foil.
Further, the number of the test channels 21 in the first path of electric conductors is equal to the number of the test channels 31 in the second path of electric conductors; taking a substrate with a diameter of 245mm as an example, the number of the test channels in the first electric conductor and the second electric conductor is designed to be 64, so that the test effect can be optimal.
Therefore, the wafer test probe card provided by the utility model utilizes the thin copper foil line width as the electric conductor, and reduces the space between the copper foils, so that the current can be effectively concentrated on the area of the small copper foil through the probe, and the chances of leakage current and small parasitic capacitance are reduced; and can increase the number of testing simultaneously through two way electric conductors, improve efficiency of software testing, prolong the life of probe card, improve the test accuracy.
A wafer test probe card according to the present invention is described above by way of example with reference to the accompanying drawings. However, it should be understood by those skilled in the art that various modifications can be made to the wafer test probe card provided in the present invention without departing from the scope of the invention. Therefore, the scope of the present invention should be determined by the content of the appended claims.
Claims (10)
1. A wafer test probe card includes a substrate; the substrate is characterized in that an inner circle area and an outer ring area are arranged on the surface of the substrate, and the radius of the inner circle area is smaller than the ring width of the outer ring area; the inner circle region is internally and annularly provided with a first path of electric conductor consisting of more than two paths of test channels, and each test channel in the first path of electric conductor is annularly distributed in the inner circle region; and a second path of electric conductor consisting of more than two paths of test channels is annularly arranged in the outer ring area, and each test channel in the second path of electric conductor is distributed in a columnar manner from the edge of the inner circular area to the edge of the substrate.
2. The wafer test probe card of claim 1, wherein a contact point for contacting a probe is disposed on each test channel of the first electrical conductor and the second electrical conductor, and a ground contact point is disposed on each test channel of the second electrical conductor.
3. The wafer test probe card of claim 1, wherein the ring shape is a perfect circle; the column is a rod-shaped column or a square column which is gradually enlarged from inside to outside.
4. The wafer test probe card of claim 1, wherein each test channel of the first electrical conductor and the second electrical conductor is a copper foil.
5. The wafer test probe card of claim 4, wherein a first interference rejection layer is disposed on each test channel of the second electrical conductor, the first interference rejection layer being disposed longitudinally on each test channel of the second electrical conductor.
6. The wafer test probe card of claim 1, wherein a second anti-interference layer is disposed on the substrate in the outer ring area, the second anti-interference layer being disposed between the test channels of the second electrical conductor.
7. The wafer test probe card of claim 6, wherein the second anti-interference layer is annular or rectangular.
8. The wafer test probe card of claim 5, wherein the first tamper resistant layer is a milled area on the copper foil.
9. The wafer test probe card of claim 1, wherein the test channels in the first electrical conductors are distributed in the inner circular area with a first predetermined line width and a first predetermined pitch; and the test channels in the second path of electric conductors are distributed in the outer ring area by a second preset line width and a second preset distance.
10. The wafer test probe card of claim 8, wherein the number of test channels of the first electrical conductor is equal to the number of test channels of the second electrical conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920908482.9U CN211206583U (en) | 2019-06-17 | 2019-06-17 | Wafer test probe card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920908482.9U CN211206583U (en) | 2019-06-17 | 2019-06-17 | Wafer test probe card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211206583U true CN211206583U (en) | 2020-08-07 |
Family
ID=71856447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920908482.9U Active CN211206583U (en) | 2019-06-17 | 2019-06-17 | Wafer test probe card |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211206583U (en) |
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2019
- 2019-06-17 CN CN201920908482.9U patent/CN211206583U/en active Active
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200921 Address after: 230000 building a, Yunhai Road Industrial Park, 176 Yuner Road, Hefei Economic and Technological Development Zone, Anhui Province Patentee after: Hefei core semiconductor Co., Ltd Address before: Room 706, good news building, 1 Jubilee street, Hong Kong, China Patentee before: Yuandingfeng Investment Co.,Ltd. |
|
| TR01 | Transfer of patent right |