CN116482511B - Chip comprehensive testing device and chip comprehensive testing method - Google Patents
Chip comprehensive testing device and chip comprehensive testing method Download PDFInfo
- Publication number
- CN116482511B CN116482511B CN202310323266.9A CN202310323266A CN116482511B CN 116482511 B CN116482511 B CN 116482511B CN 202310323266 A CN202310323266 A CN 202310323266A CN 116482511 B CN116482511 B CN 116482511B
- Authority
- CN
- China
- Prior art keywords
- chip
- film body
- film
- wafer
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 94
- 239000002184 metal Substances 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000000523 sample Substances 0.000 claims description 37
- 239000000919 ceramic Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 238000010998 test method Methods 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 67
- 235000012431 wafers Nutrition 0.000 description 29
- 239000010409 thin film Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- KTXUOWUHFLBZPW-UHFFFAOYSA-N 1-chloro-3-(3-chlorophenyl)benzene Chemical compound ClC1=CC=CC(C=2C=C(Cl)C=CC=2)=C1 KTXUOWUHFLBZPW-UHFFFAOYSA-N 0.000 description 3
- 230000000670 limiting effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2868—Complete testing stations; systems; procedures; software aspects
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
- G01N29/04—Analysing solids
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N2291/00—Indexing codes associated with group G01N29/00
- G01N2291/02—Indexing codes associated with the analysed material
- G01N2291/023—Solids
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
The invention discloses a chip comprehensive testing device and a chip comprehensive testing method, wherein the device comprises a needle card and a film module; the needle clamp is provided with a through hole; the film module is arranged in the through hole in a penetrating way and is fixedly connected with the needle card; the film module comprises a metal body and a film body; the film body is of a structure with one end open and the other end closed, and the inside of the film body is hollow; the metal body is arranged in the film body, and a cavity is formed between the metal body and the bottom of the film body at intervals. The invention integrates the film module on the needle card, and simulates the application scene of the waveform by the film module, so that the conventional electrical test on the wafer and the ultrasonic test on the chip can be realized, the test time is greatly shortened, and the test efficiency is improved.
Description
Technical Field
The present invention relates to the field of semiconductor testing technologies, and in particular, to a chip integrated testing device and a chip integrated testing method.
Background
Probe stations (probers) are mainly used in the semiconductor industry, the optoelectronics industry, integrated circuits and testing of packages. When a Wafer (Wafer) with a plurality of ultrasonic fingerprint chips is tested by using a probe station, the Wafer is borne on a copper disc, probes on a probe card are contacted with a bonding Pad (Pad) of the Wafer, and then the probe card is communicated with a tester to form a closed loop, so that the Wafer is tested.
However, in the prior art, only conventional electrical tests, that is, tests such as voltage supply and current measurement and voltage supply, can be performed on the wafer, but no method for simulating the application scene of waveforms exists, so that ultrasonic tests cannot be performed, and whether the ultrasonic fingerprint chip meets the requirements cannot be judged.
Accordingly, improvements in the art are needed.
The above information is presented as background information only to aid in the understanding of the present disclosure and is not intended or admitted to be prior art relative to the present disclosure.
Disclosure of Invention
The invention provides a chip comprehensive testing device and a chip comprehensive testing method, which are used for solving the defects in the prior art.
In order to achieve the above object, the present invention provides the following technical solutions:
in a first aspect, the present invention provides a chip integrated test device, including a needle card and a film module;
the needle clamp is provided with a through hole;
the film module is arranged in the through hole in a penetrating way and is fixedly connected with the needle card;
the film module comprises a metal body and a film body;
the film body is of a structure with one end open and the other end closed, and the inside of the film body is hollow;
the metal body is arranged in the film body, and a cavity is formed between the metal body and the bottom of the film body at intervals.
Further, in the chip integrated test device, the pin card comprises a PCB, a ceramic substrate and a probe;
the ceramic substrate is arranged on the PCB;
the probes are arranged on the ceramic substrate;
the ceramic substrate and the probe are provided with the through holes.
Further, in the integrated chip testing device, the thin film module further comprises a fixed guide rail and a distance adjusting measuring tool;
the fixed guide rail penetrates through the through hole and is fixedly connected with the needle card;
the film body is arranged on the fixed guide rail in a sliding way;
the distance adjusting measuring tool is fixed on the fixed guide rail;
the measuring extension end of the distance adjusting measuring tool is propped against or fixedly connected with the metal body; or the measuring extension end of the distance adjusting measuring tool is propped against or fixedly connected with the film body.
Further, in the chip integrated test device, the distance adjusting measuring tool is a digital display differential rule.
Further, in the chip integrated test device, the interval between the metal body and the bottom of the film body is 3mm.
Further, in the chip integrated test device, rubber is arranged on the outer side of the bottom of the film body.
Further, in the integrated chip test device, the thicknesses of the side wall and the bottom of the film body are 400um-600um.
Further, in the integrated chip test device, the thickness of the bottom of the film body is 400um-600um.
In a second aspect, the present invention provides a chip integrated test method, based on the chip integrated test device according to the first aspect, the method includes:
controlling the wafer to rise so that the probes on the needle card are in contact with the Pad of the wafer, and the bottom of the film body is in contact with the sensor area of the chip;
and starting a test program, performing electrical test on the wafer through the probe, and powering on the chip to enable the sensor region of the chip to emit ultrasonic waves so as to cooperate with the film body to perform ultrasonic test.
Further, in the integrated chip test method, before the step of controlling the wafer to rise so that the probe on the probe card contacts the Pad of the wafer and the bottom of the film body contacts the sensor area of the chip, the method further includes:
and adjusting the height of the film body to a proper position through a distance adjusting measuring tool.
Compared with the prior art, the invention has the following beneficial effects:
according to the chip comprehensive testing device and the chip comprehensive testing method, the thin film module is integrated on the needle card, and the thin film module simulates the application scene of waveforms, so that the conventional electrical testing of the wafer and the ultrasonic testing of the chip can be realized, the testing time is greatly shortened, and the testing efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a chip integrated test device according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a chip integrated test device according to a first embodiment of the present invention;
fig. 3 is a flow chart of a method for testing chips comprehensively according to a second embodiment of the invention.
Reference numerals:
a needle card 1, a film module 2, a wafer 3, a pad 4 and a sensor area 5;
a PCB 11, a ceramic substrate 12 and a probe 13;
metal body 21, film body 22, cavity 23, fixed guide rail 24, distance adjusting gauge 25.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is apparent that the embodiments described below are only some embodiments of the present invention, not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it will be understood that when one component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present.
Furthermore, the terms "long," "short," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship based on that shown in the drawings, for convenience of description of the present invention, and are not intended to indicate or imply that the apparatus or elements referred to must have this particular orientation, operate in a particular orientation configuration, and thus should not be construed as limiting the invention.
The technical scheme of the invention is further described below by the specific embodiments with reference to the accompanying drawings.
Example 1
In view of the above-mentioned drawbacks of the conventional chip testing technology, the applicant is based on the fact that the design and manufacture of such products has been performed for many years, and actively research and innovation in combination with the application of the theory, so as to hope to create a technology capable of solving the drawbacks of the prior art, so that the chip testing technology has more practicability. After continuous research and design and repeated sample test and improvement, the invention with practical value is finally created.
Referring to fig. 1-2, an embodiment of the present invention provides a chip integrated test device, which includes a probe card 1 and a film module 2;
the needle card 1 is provided with a through hole;
the film module 2 is arranged through the through hole and fixedly connected with the needle card 1;
the film module 2 comprises a metal body 21 and a film body 22;
the film body 22 has a structure with one end open and the other end closed, and is hollow;
the metal body 21 is disposed in the film body 22, and a cavity 23 is formed between the metal body 21 and the bottom of the film body 22.
It should be noted that, in the prior art, the conventional electrical test is performed on the wafer 3 by using the probe card, the electrical test is OK, the ultrasonic test on the chip is performed in the next step, and before the ultrasonic test is performed, the film needs to be pasted on the sensor (sensing) area of the chip to simulate the application scenario of the waveform, because if the film is not pasted, the ultrasonic wave emitted by the sensor area 5 cannot rebound due to no medium touching after entering the air, that is, the ultrasonic test cannot be performed due to no medium feedback waveform, so the ultrasonic test can be performed only by performing the film pasting process to determine whether the ultrasonic fingerprint chip meets the requirement. The problem with this test procedure is that the non-simultaneous step-wise manner and the added film-attachment procedure result in a long test time, which affects the test efficiency. In view of this, the present embodiment proposes a scheme of integrating conventional electrical testing and ultrasonic testing, specifically, by integrating the film module 2 on the pin card 1, the film module 2 simulates the application scenario of waveforms, so that the conventional electrical testing on the wafer 3 can be implemented, and the ultrasonic testing on the chip can be implemented simultaneously, so that the chip with poor ultrasonic testing result can be found in advance, the cost and time of the subsequent film-pasting test are reduced, and the testing efficiency is improved.
Specifically, a metal body 21 is arranged in a film body 22, and a cavity 23 is formed at intervals between the metal body 21 and the bottom of the film body 22, after the film body 22 of the module is contacted with a sensor area 5, a layer of film is adhered to the sensor area 5, so that the film body 22 can be matched for ultrasonic testing to replace the existing film adhering process, and the cavity 23 can simulate the application environment that ultrasonic waves encounter different media to be reflected and grabbed to analyze and test when the test is performed, so that the good condition of a chip can be better judged according to the different waveforms, namely, the transmission and reflection sound wave speeds of the ultrasonic waves sent by the sensor area 5 when the ultrasonic waves enter rubber and air are different, the time of the sensor receiving signals is also different, the information fed back by the chip can be calculated according to the time difference, and then the information fed back by the chip can be directly judged on the wafer 4 by comparing with the expected information.
Referring again to fig. 1-2, in this embodiment, the pin card 1 includes a PCB 11, a ceramic substrate 12, and probes 13;
the ceramic substrate 12 is arranged on the PCB 11;
the probe 13 is provided on the ceramic substrate 12;
the through holes are formed in both the ceramic substrate 12 and the probes 13.
In addition, the probes 13 are in contact with the Pad 4 of the wafer when the wafer 3 is subjected to a conventional electrical test.
Referring again to fig. 1-2, in this embodiment, the film module 2 further includes a fixed rail 24 and a distance adjusting gauge 25;
the fixed guide rail 24 is arranged through the through hole and is fixedly connected with the needle card 1;
the film body 22 is slidably arranged on the fixed guide rail 24;
the distance adjusting measuring tool 25 is fixed on the fixed guide rail 24;
the measuring extension end of the distance adjusting gauge 25 is propped against or fixedly connected with the metal body 21; or, the measuring extension end of the distance adjusting gauge 25 is abutted against or fixedly connected with the film body 22.
It should be noted that, if the solution without the fixed guide rail 24 and the distance adjusting gauge 25 is adopted, the set height of the film module 2 is fixed, which is suitable for testing wafers in the same size batch. The height of the film module 2 is adjustable if the test of wafers of different size batches is to be adapted. The fixed guide rail 24 and the distance adjusting gauge 25 are designed to facilitate practical application of the module. After the fixed guide rail 24 is added, the fixed guide rail 24 is fixed on the needle card 1, so that the film module 2 is fixed, the distance adjusting measuring tool 25 is matched, the height position of the film module 2 is adjusted up and down by the distance adjusting measuring tool 25, the film module 2 is adjusted to a height value required to be contacted with the sensor area 5 through program control, the sensor area 5 is subjected to lamination test, and a chip is not damaged.
In this embodiment, the interval between the metal body 21 and the bottom of the film body 22 is 3mm.
It will be appreciated that 3mm is actually the height of the cavity 23, which can be arbitrarily set by the skilled person according to the empirical values and the actual application scenario, and this embodiment is specifically defined only by taking 3mm as an example.
In this embodiment, the distance adjusting gauge 25 is a digital differential ruler.
It should be noted that, the distance that the microscopic dividing ruler can be adjusted up and down is displayed, so that the position of the film module 2 can be accurately adjusted, and the film module 2 can be accurately adjusted to the height that needs to contact the sensor region 5.
In this embodiment, rubber is provided on the outer side of the bottom of the film body 22.
It should be noted that, the rubber disposed at the outer side of the bottom of the film body 22 may further protect the chip.
In this embodiment, the thickness of the side wall and the bottom of the film body 22 is 400um-600um, so that the film body can be better formed integrally.
It will be appreciated that only the bottom of the film body 22 need be actually thinner, since only the bottom of the film body 22 needs to be in contact with the sensor region 5 to function as a film, and therefore only the bottom of the film body 22 need be actually designed to have a thickness of 400um to 600um. In this embodiment, the metal body 21 is made of CR12 metal material, and the film body 22 is made of PVC material.
The metal body 21 and the film body 22 are bonded by resin.
In this embodiment, the rectangular metal body 21 is formed by CR12 metal for supporting and fixing, the film body 22 is directly formed by PVC in one step, and then the two are bonded and fixed by resin.
Although the terms of the pin card 1, the film module, the PCB board 11, the ceramic substrate 12, the probe, etc. are used more herein, the possibility of using other terms is not excluded. These terms are used merely for convenience in describing and explaining the nature of the invention; they are to be interpreted as any additional limitation that is not inconsistent with the spirit of the present invention.
According to the chip comprehensive testing device provided by the invention, the thin film module is integrated on the needle card, and the thin film module simulates the application scene of waveforms, so that the conventional electrical test on the wafer and the ultrasonic test on the chip can be realized, the testing time is greatly shortened, and the testing efficiency is improved.
Example two
Referring to fig. 3, a flow chart of a method for testing a wafer is provided in a second embodiment of the present invention, and the method is implemented based on a device for testing a wafer. The method specifically comprises the following steps:
s201, controlling the wafer to ascend so that the probes on the needle card are contacted with the Pad of the wafer, and the bottom of the film body is contacted with the sensor area of the chip;
after the probe station sends the start test signal, the copper plate carrying the wafer is lifted, the probe is contacted with the Pad at this time, the bottom of the film body is contacted with the sensor area, and the tester, the probe and the chip form a required circuit structure at this time.
In this embodiment, before the step S201, the method may further include the steps of:
and adjusting the height of the film body to a proper position through a distance adjusting measuring tool.
Before the chip is ready for testing, the height of the film body is adjusted to the highest, then the proper height value between the probe and the Pad is adjusted on the probe table, and then the film body is adjusted to the proper height value position by using a plurality of micro-dividing rules so as to be contacted with the Sensor area.
S202, starting a test program, performing electrical test on the wafer through the probe, and powering on the chip to enable the sensor area of the chip to emit ultrasonic waves so as to cooperate with the film body to perform ultrasonic test.
It should be noted that, after the testing machine receives the start test signal of the probe station, the testing program is started to power up the chip, so that the chip enters a required working state, at this time, the sensor area emits ultrasonic waves, the transmission and reflection sound wave speeds of the ultrasonic waves when the ultrasonic waves enter rubber and air are different, the time of the sensor receiving the signal is also different, the information fed back by the chip can be calculated according to the time difference, and then the comparison with the expected information is performed, so that whether the chip meets the requirement can be directly judged on the wafer.
According to the chip comprehensive test method provided by the invention, the thin film module is integrated on the needle card, and the thin film module simulates the application scene of waveforms, so that the conventional electrical test on the wafer and the ultrasonic test on the chip can be realized, the test time is greatly shortened, and the test efficiency is improved.
In view of the foregoing, it will be evident to a person skilled in the art that the foregoing detailed disclosure may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be proposed by this application, and are intended to be within the spirit and scope of the exemplary embodiments of this application.
Furthermore, certain terms in the present application have been used to describe embodiments of the present application. For example, "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. Thus, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various portions of this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined as suitable in one or more embodiments of the application.
It should be appreciated that in the foregoing description of embodiments of the present application, various features are grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the application. However, this is not to say that a combination of these features is necessary, and it is entirely possible for a person skilled in the art to extract some of them as separate embodiments to understand them at the time of reading this application. That is, embodiments in this application may also be understood as an integration of multiple secondary embodiments. While each secondary embodiment is satisfied by less than all of the features of a single foregoing disclosed embodiment.
Each patent, patent application, publication of patent application, and other materials, such as articles, books, specifications, publications, documents, articles, etc., cited herein are hereby incorporated by reference. All matters are to be interpreted in a generic and descriptive sense only and not for purposes of limitation, except for any prosecution file history associated therewith, any and all matters not inconsistent or conflicting with this document or any and all matters not complaint file histories which might have a limiting effect on the broadest scope of the claims. Now or later in association with this document. For example, if there is any inconsistency or conflict between the description, definition, and/or use of terms associated with any of the incorporated materials, the terms in the present document shall prevail.
Finally, it is to be understood that the embodiments of the application disclosed herein are illustrative of the principles of the embodiments of the present application. Other modified embodiments are also within the scope of the present application. Accordingly, the embodiments disclosed herein are by way of example only and not limitation. Those skilled in the art can adopt alternative configurations to implement the applications herein according to embodiments herein. Accordingly, embodiments of the present application are not limited to the embodiments precisely described in the application.
Claims (9)
1. The chip comprehensive testing device is used for testing an ultrasonic fingerprint chip and is characterized by comprising a needle card (1) and a film module (2);
the needle card (1) is provided with a through hole;
the film module (2) is penetrated through the through hole and fixedly connected with the needle card (1);
the film module (2) comprises a metal body (21) and a film body (22);
the film body (22) is of a structure with one end open and the other end closed, and the inside of the film body is hollow;
the metal body (21) is arranged in the film body (22), and a cavity (23) is formed between the metal body (21) and the bottom of the film body (22) at intervals;
the needle card (1) comprises a PCB (11), a ceramic substrate (12) and a probe (13);
the ceramic substrate (12) is arranged on the PCB (11);
the probe (13) is arranged on the ceramic substrate (12);
the ceramic substrate (12) and the probe (13) are both provided with the through hole;
the probe on the needle card is contacted with the Pad of the wafer, and the bottom of the film body is contacted with the sensor area of the chip;
and the sensor area of the chip emits ultrasonic waves by electrifying the chip so as to be matched with the film body for ultrasonic testing.
2. The chip integrated test device according to claim 1, wherein the film module (2) further comprises a fixed guide rail (24) and a distance adjusting gauge (25);
the fixed guide rail (24) penetrates through the through hole and is fixedly connected with the needle card (1);
the film body (22) is arranged on the fixed guide rail (24) in a sliding way;
the distance adjusting measuring tool (25) is fixed on the fixed guide rail (24);
the measuring extension end of the distance adjusting measuring tool (25) is propped against or fixedly connected with the metal body (21); or the measuring extension end of the distance adjusting measuring tool (25) is propped against or fixedly connected with the film body (22).
3. The chip integrated test device according to claim 2, wherein the distance adjusting gauge (25) is a digital differential gauge.
4. The integrated chip testing device according to claim 1, wherein the metal body (21) is spaced 3mm from the bottom of the film body (22).
5. The chip integrated test device according to claim 1, wherein rubber is provided on the bottom outside of the film body (22).
6. The integrated chip testing device according to claim 1, wherein the thickness of the side wall and the bottom of the film body (22) is 400um to 600um.
7. The integrated chip testing device according to claim 1, wherein the thickness of the bottom of the film body (22) is 400um-600um.
8. A chip integrated test method based on the chip integrated test device according to any one of claims 1-7, characterized in that the method comprises:
controlling the wafer to rise so that the probes on the needle card are in contact with the Pad of the wafer, and the bottom of the film body is in contact with the sensor area of the chip;
and starting a test program, performing electrical test on the wafer through the probe, and powering on the chip to enable the sensor region of the chip to emit ultrasonic waves so as to cooperate with the film body to perform ultrasonic test.
9. The integrated chip test method according to claim 8, wherein before the step of controlling the wafer to rise so that the probes on the probe card contact the Pad of the wafer, the bottom of the film body contacts the sensor region of the chip, the method further comprises:
and adjusting the height of the film body to a proper position through a distance adjusting measuring tool.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310323266.9A CN116482511B (en) | 2023-03-29 | 2023-03-29 | Chip comprehensive testing device and chip comprehensive testing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310323266.9A CN116482511B (en) | 2023-03-29 | 2023-03-29 | Chip comprehensive testing device and chip comprehensive testing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116482511A CN116482511A (en) | 2023-07-25 |
| CN116482511B true CN116482511B (en) | 2024-03-22 |
Family
ID=87224242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310323266.9A Active CN116482511B (en) | 2023-03-29 | 2023-03-29 | Chip comprehensive testing device and chip comprehensive testing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116482511B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170094059A (en) * | 2016-02-08 | 2017-08-17 | 박철 | Finger Print Sensor Module |
| CN109003950A (en) * | 2018-08-08 | 2018-12-14 | 苏州晶方半导体科技股份有限公司 | A kind of encapsulating structure and packaging method of ultrasonic fingerprint chip |
| CN109492472A (en) * | 2017-09-12 | 2019-03-19 | 南昌欧菲生物识别技术有限公司 | Ultrasonic fingerprint identifies mould group and electronic equipment |
| CN213122203U (en) * | 2020-10-25 | 2021-05-04 | 九天创新(南昌)设备制造有限公司 | Main control chip circuit testing arrangement |
| CN216996470U (en) * | 2022-03-07 | 2022-07-19 | 上海芯丑半导体设备有限公司 | Chip conveying device |
| CN114859463A (en) * | 2022-04-29 | 2022-08-05 | 中山大学 | On-chip micro-cavity ultrasonic sensitization hollowed chip and preparation method thereof |
| CN115641619A (en) * | 2022-09-13 | 2023-01-24 | 深圳市汇顶科技股份有限公司 | Ultrasonic fingerprint identification device and electronic equipment |
| CN218383172U (en) * | 2022-09-27 | 2023-01-24 | 深圳市汇顶科技股份有限公司 | Wafer and wafer testing device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7276744B2 (en) * | 2019-02-26 | 2023-05-18 | 国立大学法人豊橋技術科学大学 | Ultrasonic inspection device and ultrasonic inspection method |
-
2023
- 2023-03-29 CN CN202310323266.9A patent/CN116482511B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170094059A (en) * | 2016-02-08 | 2017-08-17 | 박철 | Finger Print Sensor Module |
| CN109492472A (en) * | 2017-09-12 | 2019-03-19 | 南昌欧菲生物识别技术有限公司 | Ultrasonic fingerprint identifies mould group and electronic equipment |
| CN109003950A (en) * | 2018-08-08 | 2018-12-14 | 苏州晶方半导体科技股份有限公司 | A kind of encapsulating structure and packaging method of ultrasonic fingerprint chip |
| CN213122203U (en) * | 2020-10-25 | 2021-05-04 | 九天创新(南昌)设备制造有限公司 | Main control chip circuit testing arrangement |
| CN216996470U (en) * | 2022-03-07 | 2022-07-19 | 上海芯丑半导体设备有限公司 | Chip conveying device |
| CN114859463A (en) * | 2022-04-29 | 2022-08-05 | 中山大学 | On-chip micro-cavity ultrasonic sensitization hollowed chip and preparation method thereof |
| CN115641619A (en) * | 2022-09-13 | 2023-01-24 | 深圳市汇顶科技股份有限公司 | Ultrasonic fingerprint identification device and electronic equipment |
| CN218383172U (en) * | 2022-09-27 | 2023-01-24 | 深圳市汇顶科技股份有限公司 | Wafer and wafer testing device |
Non-Patent Citations (1)
| Title |
|---|
| 一种全平面指纹传感器的研究与实现;徐步陆;功能材料与器件学报;20200515;第26卷(第02期);第127-130页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116482511A (en) | 2023-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI384227B (en) | Active non-contact probe card | |
| TWI447414B (en) | Test apparatus and test method | |
| JP5016892B2 (en) | Inspection apparatus and inspection method | |
| US9030216B2 (en) | Coaxial four-point probe for low resistance measurements | |
| KR101191594B1 (en) | Holding member for inspection and method for manufacturing holding member for inspection | |
| US11327050B2 (en) | Mechanical failure monitoring, detection, and classification in electronic assemblies | |
| KR101138297B1 (en) | Probe apparatus and test apparatus | |
| US20110084721A1 (en) | Manufacturing method and wafer unit for testing | |
| US20130015871A1 (en) | Systems, devices, and methods for two-sided testing of electronic devices | |
| CN116482511B (en) | Chip comprehensive testing device and chip comprehensive testing method | |
| US20140184261A1 (en) | Testing apparatus and testing method | |
| KR102521076B1 (en) | Method of inspecting insert assembly and test socket for inspecting semiconductor device | |
| CN107219167B (en) | Test equipment and test method | |
| US20130176045A1 (en) | Package test devices having a printed circuit board | |
| JP2008170194A (en) | Test method of electronic device, tester of electronic device, and test system of electronic device | |
| CN101587850B (en) | Bearing structure and testing device | |
| KR20090075515A (en) | Probe card and test apparatus comprising the same | |
| US20190204380A1 (en) | Lead guides having a recessed face | |
| CN215641649U (en) | Test circuit board structure | |
| US11761983B2 (en) | Probe card integrated with a hall sensor | |
| TWI580980B (en) | Method of measuring electrical length in semiconductor testing apparatus and method of conductive region of wafer alignment | |
| TWI735915B (en) | A wafer probe card integrated with a light source facing a device under test side and method of manufacturing | |
| CN219675488U (en) | Testing device of ultrasonic fingerprint identification chip | |
| JP2005308558A (en) | System-in-package test inspection device and test inspection method | |
| CN106338621A (en) | PCB thin board vertical flying probe test bracing frame |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |