CN116435352B - Power device primitive cell structure, power device and preparation method thereof - Google Patents

Power device primitive cell structure, power device and preparation method thereof Download PDF

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CN116435352B
CN116435352B CN202310576995.5A CN202310576995A CN116435352B CN 116435352 B CN116435352 B CN 116435352B CN 202310576995 A CN202310576995 A CN 202310576995A CN 116435352 B CN116435352 B CN 116435352B
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gate
grooves
power device
grid
groove
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CN116435352A (en
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吴振兴
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Beijing Beiyinkai Microelectronics Co ltd
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Beijing Beiyinkai Microelectronics Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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Abstract

The application discloses a power device primitive cell structure, a power device and a preparation method thereof, wherein the power device primitive cell structure comprises the following components: a plurality of grid grooves and grid electrodes corresponding to the grid grooves respectively; the gate trench includes: a plurality of first grooves and a plurality of second grooves which are arranged in parallel and are mutually independent; the first groove is connected with the grid bus bar, and two ends of the second groove are arranged in a floating mode; the grid electrode comprises: a first gate corresponding to the first trench, a second gate corresponding to the second trench. The dummy gate structures are adopted to separate the Trench of the cell region mutually, so that the floating effect of the gate oxide layer of the Trench is generated, the floating effect is not counted in Cge or Cies, the input capacitance is further greatly reduced, and in addition, the input capacitance and the feedback capacitance can be regulated by regulating the number of the dummy gates.

Description

Power device primitive cell structure, power device and preparation method thereof
Technical Field
The application relates to the technical field of power device manufacturing, in particular to a power device primitive cell structure, a power device and a preparation method thereof.
Background
As shown in fig. 1, the front-side cell structures of the mainstream IGBT and MOSFET and other power devices have mostly adopted a trench gate cell structure, and the power device with the trench gate cell structure has a longitudinal channel perpendicular to the surface of the chip compared with the earlier Planar (Planar) cell structure, so that the current density of the chip can be greatly improved.
Oxide layers and PN junctions are generated inside the chip in the preparation process of IGBT and MOSFET, and parasitic capacitance is generated inside the chip due to the existence of the oxide layers and PN junctions. As shown in FIG. 2, parasitic capacitances generated between three electrodes of the IGBT are respectively C gc 、C ge And C ce To represent. According to the electric characteristics of the IGBT in operation, the IGBT capacitance is defined as the input capacitance: cies=c gc +C ge The method comprises the steps of carrying out a first treatment on the surface of the Feedback capacitance (miller capacitance): cres=c gc The method comprises the steps of carrying out a first treatment on the surface of the Output capacitance: coes=C gc +C ce 。
As shown in fig. 3, the IGBT turn-on process is roughly divided into four phases: 1. after the grid Gate receives the voltage signal, the grid is charged through Cge, so that the grid voltage Vg is quickly increased to the threshold voltage Vth of the IGBT, namely the channel of the IGBT is opened; 2. the grid continues to be opposite to C gc And C ge Charging, the channel is continuously opened, the ce current of the IGBT is rapidly increased, the maximum load current IC is reached, the Vg is continuously increased, and the Vg reaches the Miller voltage at the moment; 3. after Vg reaches the Miller voltage, the grid continues to supply C gc Charging, the Vce voltage continues to rise, at which time the value of the Miller voltage remains unchanged for a period of time, known as the Miller plateau, at which time a large dV/dt tends to occur; 4. after Vce reaches the bus voltage VCC, the grid continues to conduct C ge And charging, wherein Vge gradually rises to the signal voltage.
The cell design mode of the IGBT has great influence on the value of the grid capacitance, and the area of the oxide layer, the concentration depth of the PN junction and the like can influence the parasitic capacitance. Under different design modes, the parasitic capacitance parameters of the IGBT are possibly greatly different, and factors such as the switching speed, the switching loss, the driving power of the driving circuit, the design mode of the driving circuit and the like of the IGBT are influenced.
Currently, the dominant technology is to regulate the gate capacitance through the cell structure of the dummy gate. As shown in fig. 4, multiple Trench are connected by polysilicon to form a practical primitive cell structure. The middle part of the cell has no active region implantation nor openings on the side of the Trench, and is practically non-conductive. The conductive channel is implanted and formed only in the two side active regions. The above structure has limited effect on the Cies regulation, but has more remarkable effect on the regulation of the feedback capacitance, cres=c gc， The semiconductor device is formed by serially connecting a grid electrode bottom oxide layer capacitor, a depletion layer capacitor formed by a P well region in a cell and an N-substrate. At high Vce values, the depletion layer capacitance is much smaller than the oxide layer capacitance, and the feedback capacitance is substantially determined by the depletion layer capacitance. Under the condition of high Vce, the active regions on the left and right sides of the cell structure only form depletion layers, so that the device voltage resistance is provided. The middle dummy gate region does not participate in depletion and thus Cres can be significantly improved from a chip global perspective.
Although the prior art can improve the feedback capacitance, there is little improvement in the input capacitance. Since the input capacitance is the sum of the gate to emitter capacitances in parallel, it is virtually essentially equal to the thin gate oxide capacitance. Since the dummy gates, although not capable of turning on the channel, are all connected to the gate potential, cge will be relatively large, in other words the input capacitance Cies will be relatively large. That is, if the IGBT is turned on with an increase in chip area or cell density, a strong driving current is often required to make the chip reach the threshold voltage and turn on later. The voltage change after the IGBT gate receives the turn-on signal can be expressed by the following formula:
as can be seen from the above equation, the larger Cge, the slower the Vge rise speed.
Disclosure of Invention
The application aims to provide a power device primitive cell structure, a power device and a preparation method thereof, wherein the false gate structure is adopted to separate the tresses of the primitive cell region mutually, so that a floating effect is generated on a gate oxide layer of the tresses, the floating effect is not counted in Cge or Cies, the input capacitance is further greatly reduced, and in addition, the input capacitance and the feedback capacitance can be regulated by regulating the number of the false gates.
To solve the above technical problem, a first aspect of an embodiment of the present application provides a cell structure of a power device, including: a plurality of gate trenches and gates corresponding to the gate trenches respectively;
the gate trench includes: a plurality of first grooves and a plurality of second grooves which are arranged in parallel and are mutually independent;
the first groove is connected with the grid bus bar, and two ends of the second groove are arranged in a floating mode;
the gate electrode includes: a first gate corresponding to the first trench, a second gate corresponding to the second trench.
Further, the first groove is a first preset length, and the second groove is a second preset length;
the length difference between the first preset length and the second preset length is a preset value.
Further, at least two second grooves are arranged between the two first grooves;
input capacitance value C of the power device i And feedback capacitance value C r Inversely related to the number of said second grooves between two of said first grooves;
the input capacitance value C i The calculation formula of (2) is as follows:
C i ＝A·C u ；
wherein A is the area factor of the chip, C u The total input capacitance value of each repeating unit connected in parallel for the cell region of the chip;
C u ＝C i1 +nC i2 ；
C i ＝(C i1 +nC i2 )·[A/(1+n)]；
wherein C is i1 C is the input capacitance value of the first groove i2 The input capacitance value of the second grooves is obtained, and n is the number of the second grooves;
the feedback capacitance value C r The calculation formula of (2) is as follows:
C r ＝(C r1 +nC r2 )·[A/(1+n)]；
wherein C is r For the feedback capacitance value of the chip, C r1 C is the feedback capacitance value of the first groove r2 And the feedback capacitance value of the second groove.
Further, two ends of the second groove are connected with the polysilicon layer of the active region through the through holes, and the polysilicon layer of the active region is connected with the active region transmitter of the power device through the through holes.
Accordingly, a second aspect of the embodiment of the present application provides a power device, which is an IGBT or a MOSFET including the above power device cell structure.
Accordingly, a third aspect of the embodiments of the present application provides a method for manufacturing a power device, which is characterized in that the method is used for manufacturing the power device, and includes the following steps:
etching a silicon surface to obtain a plurality of grooves which are arranged in parallel, wherein each groove comprises a plurality of first grooves and a plurality of second grooves which are arranged in parallel and are mutually independent, and the length difference between the second grooves and the first grooves in the horizontal direction is a preset value;
forming a first oxide layer on the surface of the groove and the silicon through an oxidation process to obtain a gate oxide layer;
depositing a polysilicon material on the gate oxide layer, and filling the first groove and the second groove to obtain a first gate and a second gate;
etching the polycrystalline silicon material to obtain an interdigital grid bus bar of a source region of the power device, wherein the interdigital grid bus bar is connected with a plurality of first grid trenches and is converged to a grid PAD;
depositing a second oxide layer on the tops of the first grid electrode and the second grid electrode, and performing coverage protection on the first grid electrode and the second grid electrode;
providing a via hole in the first gate and the source region;
depositing a first metal layer on the top of the second oxide layer, and respectively connecting the first metal layer with the gate region and the source region through the through holes;
and etching the first metal layer to obtain a grid electrode and a source electrode which are electrically isolated in the power device.
Further, the polysilicon material is a low-resistance highly doped polysilicon material.
Further, the depositing a first metal layer on top of the second oxide layer includes:
and depositing the first metal layer on the top of the second oxide layer by adopting a sputtering mode or an evaporation mode.
Accordingly, a fourth aspect of the embodiments of the present application provides a power device, which is an IGBT or a MOSFET including the above-mentioned cell structure.
Accordingly, a fifth aspect of the embodiments of the present application provides a method for manufacturing a power device, which is used for manufacturing the power device, including the following steps:
etching a silicon surface to obtain a plurality of grooves which are arranged in parallel, wherein each groove comprises a plurality of first grooves and a plurality of second grooves which are arranged in parallel and are mutually independent, and the length difference between the second grooves and the first grooves in the horizontal direction is a preset value;
forming a first oxide layer on the surface of the groove and the silicon through an oxidation process to obtain a gate oxide layer;
depositing a polysilicon material on the gate oxide layer, and filling the first groove and the second groove to obtain a first gate and a second gate;
etching the polycrystalline silicon material to obtain an interdigital grid bus bar of a source region of the power device, wherein the interdigital grid bus bar is connected with a plurality of first grid trenches and is converged to a grid PAD;
the second grid electrodes are connected with the polysilicon short circuit areas, and the polysilicon short circuit areas are positioned in the emitter areas and are disconnected with the polysilicon bus bars through an etching process;
depositing a second oxide layer on the tops of the first grid electrode and the second grid electrode, and performing coverage protection on the first grid electrode and the second grid electrode;
providing a via hole in the first gate and the source region;
depositing a first metal layer on the top of the second oxide layer in a sputtering or vapor deposition mode, and respectively connecting the first metal layer with the grid region and the source region through the through holes;
and etching the first metal layer to obtain a grid electrode and a source electrode which are electrically isolated in the power device.
The technical scheme provided by the embodiment of the application has the following beneficial technical effects:
the dummy gate structures are adopted to separate the Trench of the cell region mutually, so that the floating effect of the gate oxide layer of the Trench is generated, the floating effect is not counted in Cge or Cies, the input capacitance is further greatly reduced, and in addition, the input capacitance and the feedback capacitance can be regulated by regulating the number of the dummy gates.
Drawings
FIG. 1 is a schematic diagram of a prior art power device gate trench cell structure;
FIG. 2 is a schematic diagram of a conventional IGBT parasitic capacitance;
fig. 3 is a schematic diagram of a conventional IGBT parasitic capacitance;
FIG. 4 is a schematic diagram of a conventional cell structure;
fig. 5 is a schematic diagram of a cell structure of a power device according to an embodiment of the present application;
fig. 6 is a schematic diagram II of a cell structure of a power device according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a floating dummy gate layout provided by an embodiment of the present application;
FIG. 8 is a schematic diagram of a dummy gate layout I shorted to a source provided by an embodiment of the present application;
fig. 9 is a schematic diagram of a second dummy gate layout shorted to a source according to an embodiment of the present application.
Detailed Description
The objects, technical solutions and advantages of the present application will become more apparent by the following detailed description of the present application with reference to the accompanying drawings. It should be understood that the description is only illustrative and is not intended to limit the scope of the application. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present application.
Referring to fig. 5, a first aspect of an embodiment of the present application provides a cell structure of a power device, including: a plurality of grid grooves and grid electrodes corresponding to the grid grooves respectively; the gate trench includes: a plurality of first grooves and a plurality of second grooves which are arranged in parallel and are mutually independent; the first groove is connected with the grid bus bar, and two ends of the second groove are arranged in a floating mode; the grid electrode comprises: a first gate corresponding to the first trench, a second gate corresponding to the second trench.
The application provides a novel false gate primitive cell structure, and a layout implementation mode and a process implementation method thereof, so that the false gate primitive cell structure can adjust a capacitance Cge on the basis of adjusting a feedback capacitance Cgc in the prior art. In terms of a primitive cell structure, the application separates the Trench of the primitive cell region mutually, so that Cge generated by a part of thin gate oxide layer tiled on the surface of a chip can be reduced; although a thick oxide layer still exists on the surface, the capacitance generated by the thick oxide layer is almost negligible because the oxide layer is much thicker than the gate oxide layer. Instead of connecting the dummy gate to the gate G, the dummy gate can be floated or connected to the emitter E, which can generate a floating effect on the gate oxide of the root Trench, not included in Cge or Cies, and further greatly reduce the input capacitance. From the aspect of feedback capacitance, as no active region injection and no openings exist at two sides of the dummy gate, the P+ layer does not participate in voltage-withstanding depletion, and Cres can be reduced and regulated.
Further, the first groove is a first preset length, and the second groove is a second preset length; the length difference between the first preset length and the second preset length is a preset value.
Further, referring to fig. 6, at least two second trenches are disposed between the two first trenches; the input capacitance and the feedback capacitance of the power device are inversely related to the number of second trenches between the two first trenches.
With input capacitance C of the chip i For example, since the cell region of the chip is composed of innumerable repeating units connected in parallel, the input capacitance C of the chip i With each repeating unit C u There is a relationship of C i ＝A·C u The method comprises the steps of carrying out a first treatment on the surface of the Wherein A is the area factor of the chip. Since each cell consists of one first trench and a plurality of (n) second trenches C u ＝C i1 +nC i2 Then the input capacitance of the chip is related to the capacitance and number of the first and second trenches as follows:
C i ＝(C i1 +nC i2 )·[A/(1+n)]；
wherein A is the area factor of the chip, C u For the total input capacitance value, C, of each repeating unit of the chip cell region connected in parallel i1 C is the input capacitance value of the first groove i2 And n is the number of the second grooves and is the input capacitance value of the second grooves.
C after the second groove is short-circuited with the emitter by the technological means 2 Almost 0 is negligible, and the above formula becomes:
C i ＝C 1 ·[A/(1+n)]。
in addition, the feedback capacitance value C r The calculation formula of (2) is as follows:
C r ＝(C r1 +nC r2 )·[A/(1+n)]；
wherein C is r For the feedback capacitance value of the chip, C r1 A feedback capacitance value of the first groove C r2 Is the feedback capacitance value of the second trench.
The method is as follows: input capacitance C of power device i And feedback capacitance value C r A conclusion inversely related to the number of second trenches between two first trenches.
In addition, the number of the dummy gates can be increased according to design requirements, the dummy gates float or are connected to the emitter, the proportion of the dummy gates to the gates is adjusted, and then the input capacitance and the feedback capacitance of the IGBT are adjusted.
Accordingly, a second aspect of the embodiment of the present application provides a power device, which is an IGBT or a MOSFET including the above power device cell structure.
Specifically, the IGBT device has three electrodes: a gate G, an emitter and a collector C; wherein the grid electrode and the emitter electrode are formed through a front-side process, and the collector electrode is formed through a back-side process. The MOSFET has three electrodes: gate G, source S and drain D. The electrode names are slightly different, in substantial agreement with the front structure of the IGBT. The application is applicable to IGBT and MOSFET, so that the source electrode S or the emitter electrode E is suitable.
Accordingly, a third aspect of the embodiments of the present application provides a method for manufacturing a power device, which is characterized in that the method is used for manufacturing the power device, and includes the following steps:
step S110, etching a plurality of grooves which are arranged in parallel on the surface of silicon, wherein the grooves comprise a plurality of first grooves and a plurality of second grooves which are arranged in parallel and are mutually independent, and the length difference between the second grooves and the first grooves in the horizontal direction is a preset value.
And step S120, forming a first oxide layer on the surfaces of the groove and the silicon through an oxidation process to obtain a gate oxide layer.
And step S130, depositing a polysilicon material on the gate oxide layer, and filling the first groove and the second groove to obtain a first gate and a second gate.
Step S140, etching the polysilicon material to obtain an interdigital gate bus bar in the source region of the power device, where the interdigital gate bus bar is connected with the first gate trenches and is converged to the gate PAD.
And step S150, depositing a second oxide layer on the tops of the first grid electrode and the second grid electrode, and performing coverage protection on the first grid electrode and the second grid electrode.
In step S160, a via is provided in the first gate and source regions.
In step S170, a first metal layer is deposited on top of the second oxide layer and connected to the gate region and the source region respectively through the via holes.
And step S180, etching the first metal layer to obtain a grid electrode and a source electrode which are electrically isolated in the power device.
Referring to fig. 7, in the method for manufacturing a power device, a floating dummy gate layout can be obtained, and a gate Trench is connected with a gate bus bar in a chip, wherein the bus bar can be polysilicon or a metal layer, and the method is specifically implemented by adopting a corresponding process. Part of the trench is not connected to the gate nor to the emitter in the active region, that is to say is not connected to any potential, and is floating. The floating dummy gate is covered and isolated by an oxide layer, and the dummy gate is surrounded by the oxide layer, but the capacitor does not account for cge. The number ratio of the true grid electrode to the floating false grid electrode is determined according to design requirements, so that the purpose of adjusting the input capacitance and the feedback capacitance is achieved.
Further, the polysilicon material is a low-resistance highly doped polysilicon material.
Further, in step S170, a first metal layer is deposited on top of the second oxide layer, including:
in step S171, a first metal layer is deposited on top of the second oxide layer by sputtering or evaporation.
In addition, in the cell structure of the power device in the first aspect of the embodiment of the application, two ends of the second trench can be connected with the polysilicon layer of the active region through the through hole, and the polysilicon layer of the active region is connected with the active region transmitter of the power device through the through hole.
Correspondingly, the fourth aspect of the embodiment of the application also provides a power device, which is an IGBT or a MOSFET comprising the power device cell structure.
Accordingly, a fifth aspect of the embodiments of the present application provides a method for manufacturing a power device, which is used for manufacturing the power device, including the following steps:
step S210, etching a plurality of grooves which are arranged in parallel on the surface of silicon, wherein the grooves comprise a plurality of first grooves and a plurality of second grooves which are arranged in parallel and are mutually independent, and the length difference between the second grooves and the first grooves in the horizontal direction is a preset value.
In step S220, a first oxide layer is formed on the trench and the silicon surface by an oxidation process, so as to obtain a gate oxide layer.
In step S230, a polysilicon material is deposited on the gate oxide layer, and the first trench and the second trench are filled, thereby obtaining a first gate and a second gate.
Step S240, etching the polysilicon material to obtain an interdigital grid bus bar of the source region of the power device, wherein the interdigital grid bus bar is connected with a plurality of first grid trenches and is converged to a grid PAD.
In step S250, the plurality of second gates are connected to the polysilicon shorting regions, and the polysilicon shorting regions are located in the emitter region and disconnected from the polysilicon bus bars by an etching process.
Specifically, the second gates included in each of the cells are not connected to the gate bus bar, but connected to a polysilicon shorting region; the short-circuit area is positioned in the emitter area and is disconnected with the polysilicon bus bar through the same etching process; after the subsequent oxidation process, the second gate is connected to the emitter metal through the polysilicon shorting region by etching a metal via on the shorting region.
And step S260, depositing a second oxide layer on the tops of the first grid electrode and the second grid electrode, and performing coverage protection on the first grid electrode and the second grid electrode.
In step S270, a via is provided in the first gate and source regions.
In step S280, a first metal layer is deposited on top of the second oxide layer by sputtering or vapor deposition, and is connected to the gate region and the source region respectively through the via holes.
And step S290, etching the first metal layer to obtain a grid electrode and a source electrode which are electrically isolated in the power device.
Referring to fig. 8 and 9, the method for manufacturing the power device can obtain a source-connected dummy gate layout, and is suitable for a chip manufacturing process of a polysilicon bus bar. The gate on the chip is connected to a bus bar (yellow) formed of a polysilicon layer; an oxide layer exists on the polysilicon bus bar, and a hole (dark blue) needs to be opened, so that the polysilicon bus bar is connected with the surface metal layer. Part of the dummy gate Trench is not connected to the bus bar, but connected to the polysilicon layer in the active region, and a hole is formed in the oxide layer on the surface of the polysilicon layer and is directly connected to the emitter of the active region of the IGBT.
After the dummy gates are connected to the emitter, the gates do not contact the dummy gates of the source during the turn-on process of the IGBT, and therefore these dummy gates do not contribute to Cge. Similarly, since the dummy gate has no conductive cell and does not participate in the voltage-withstanding depletion, it does not contribute to Ccg. The aim of adjusting the input capacitance and the feedback capacitance can also be achieved by adjusting the quantity proportion of the true grid electrode to the false grid electrode connected with the source electrode.
The Trench is a groove, and the IGBT, the MOSFET and the like of the groove gate structure form a front primitive cell structure and a longitudinal conducting channel by etching comb-shaped grooves on the surface of a substrate.
According to the technical scheme, the dummy gate is utilized to connect a plurality of the gates together to form an independent gate structure, so that the influence of a gate oxide layer below polysilicon tiled on the surface of a chip on parasitic capacitance Cge is reduced; furthermore, through two false gate structures, the purposes of reducing parasitic capacitances Cge and Cgc can be simultaneously realized, and the functions of adjusting input capacitance and feedback capacitance are achieved.
The smaller input capacitance can improve the switching speed of the IGBT, and simultaneously can reduce the magnitude of the driving current, so that the dependence on a driving chip and a driving circuit is reduced. The smaller feedback capacitance enables the IGBT to cope with larger dv/dt in the turn-on process, and the dependence on a driving circuit can be reduced, for example, in order to reduce misleading of the IGBT in a larger dv/dt environment, a complex negative pressure driving circuit of-8V/+15V is often needed, and a simple 0V/+15V driving circuit can be used for adjusting good Cgc and Cge values and proportions.
In addition, the relation between the input capacitance and the feedback capacitance and the dynamic and static parameters of the chip can be adjusted by adjusting the number and the proportion of the true gates and the false gates, and great flexibility is provided in the IGBT design process.
The dummy gate can float, can be connected with the emitter and can exist with the true gate simultaneously, the structural design is very flexible, and a layout design mode of corresponding adjustable parasitic capacitance is provided: dummy gate layout of floating dummy gate and dummy gate layout of collector.
The embodiment of the application aims to protect a power device primitive cell structure, a power device and a preparation method thereof, wherein the power device primitive cell structure comprises the following components: a plurality of grid grooves and grid electrodes corresponding to the grid grooves respectively; the gate trench includes: a plurality of first grooves and a plurality of second grooves which are arranged in parallel and are mutually independent; the first groove is connected with the grid bus bar, and two ends of the second groove are arranged in a floating mode; the grid electrode comprises: a first gate corresponding to the first trench, a second gate corresponding to the second trench. The technical scheme has the following effects:
(1) The existing false gate technology is changed into an independent Trench structure by connecting a plurality of Trench together, so that the contribution of a gate oxide layer below a polysilicon layer tiled on the surface of a chip to Cge can be reduced;
(2) Two false grid modes (floating or emitter connection) are provided, and Cge and Cgc can be simultaneously reduced so as to achieve the effect of adjusting input capacitance and feedback capacitance;
(3) The relation between the input capacitance and the feedback capacitance and the dynamic and static parameters of the chip can be adjusted by adjusting the number and the proportion of the true gates and the false gates, and great flexibility is provided in the IGBT design process;
(4) The dummy grid can be arranged in a floating way or connected with the emitter, and can also exist with the true grid, so that the structural design is more flexible;
(5) The layout design modes corresponding to two adjustable parasitic capacitances: the layout of the floating type false gate and the dummy gate layout of the collector are correspondingly provided, and three simultaneous conditions of the vacuum gate, the floating type false gate and the dummy gate of the collector are correspondingly provided.
It is to be understood that the above-described embodiments of the present application are merely illustrative of or explanation of the principles of the present application and are in no way limiting of the application. Accordingly, any modification, equivalent replacement, improvement, etc. made without departing from the spirit and scope of the present application should be included in the scope of the present application. Furthermore, the appended claims are intended to cover all such changes and modifications that fall within the scope and boundary of the appended claims, or equivalents of such scope and boundary.

Claims (9)

1. A power device primitive structure, comprising: a plurality of gate trenches and gates corresponding to the gate trenches respectively;
the gate trench includes: a plurality of first grooves and a plurality of second grooves which are arranged in parallel and are mutually independent;
the first groove is connected with the grid bus bar, and two ends of the second groove are arranged in a floating mode;
the gate electrode includes: a first gate corresponding to the first trench and a second gate corresponding to the second trench;
at least two second grooves are arranged between the two first grooves;
input capacitance value C of the power device i And feedback capacitance value C r Inversely related to the number of said second grooves between two of said first grooves;
the input capacitance value C i The calculation formula of (2) is as follows:
C i ＝A·C u ；
wherein A is the area factor of the chip, C u The total input capacitance value of each repeating unit connected in parallel for the cell region of the chip;
C u ＝C i1 +nC i2 ；
C i ＝(C i1 +nC i2 )·[A/(1+n)]；
wherein C is i1 C is the input capacitance value of the first groove i2 The input capacitance value of the second grooves is obtained, and n is the number of the second grooves;
the feedback capacitance value C r The calculation formula of (2) is as follows:
C r ＝(C r1 +nC r2 )·[A/(1+n)]；
wherein C is r For the feedback capacitance value of the chip, C r1 C is the feedback capacitance value of the first groove r2 And the feedback capacitance value of the second groove.
2. The device cell structure of claim 1, wherein the power device cell structure comprises a plurality of cells,
the first groove is of a first preset length, and the second groove is of a second preset length;
the length difference between the first preset length and the second preset length is a preset value.
3. The device cell structure of claim 1, wherein the power device cell structure comprises a plurality of cells,
and two ends of the second groove are connected with the polysilicon layer of the active region through the through holes, and the polysilicon layer of the active region is connected with the emitter of the active region of the power device through the through holes.
4. A power device characterized by being an IGBT or a MOSFET comprising the power device cell structure of claim 1 or 2.
5. A method of manufacturing a power device according to claim 4, comprising the steps of:
etching a silicon surface to obtain a plurality of grooves which are arranged in parallel, wherein each groove comprises a plurality of first grooves and a plurality of second grooves which are arranged in parallel and are mutually independent, and the difference value of the lengths of the first grooves and the second grooves is a preset value;
forming a first oxide layer on the surface of the groove and the silicon through an oxidation process to obtain a gate oxide layer;
depositing a polysilicon material on the gate oxide layer, and filling the first groove and the second groove to obtain a first gate and a second gate;
etching the polycrystalline silicon material to obtain an interdigital grid bus bar of a power device source electrode area, wherein the interdigital grid bus bar is connected with a plurality of first grid trenches and is converged to a grid PAD;
depositing a second oxide layer on the tops of the first grid electrode and the second grid electrode, and performing coverage protection on the first grid electrode and the second grid electrode;
providing a via hole in the first gate and the source region;
depositing a first metal layer on the top of the second oxide layer, and respectively connecting the first metal layer with the gate region and the source region through the through holes;
and etching the first metal layer to obtain a grid electrode and a source electrode which are electrically isolated in the power device.
6. The method of manufacturing a power device according to claim 5, wherein,
the polysilicon material is a low-resistance high-doped polysilicon material, and is realized by an in-situ doping process in the process of depositing polysilicon, and the concentration of donor carriers reaches 1e20cm -3 。
7. The method of claim 5, wherein depositing a first metal layer on top of the second oxide layer comprises:
and depositing the first metal layer on the top of the second oxide layer by adopting a sputtering mode or an evaporation mode.
8. A power device characterized by being an IGBT or MOSFET comprising the power device cell structure of claim 3.
9. A method of manufacturing a power device according to claim 8, comprising the steps of:
etching a silicon surface to obtain a plurality of grooves which are arranged in parallel, wherein each groove comprises a plurality of first grooves and a plurality of second grooves which are arranged in parallel and are mutually independent, and the length difference between the second grooves and the first grooves in the horizontal direction is a preset value;
forming a first oxide layer on the surface of the groove and the silicon through an oxidation process to obtain a gate oxide layer;
depositing a polysilicon material on the gate oxide layer, and filling the first groove and the second groove to obtain a first gate and a second gate;
etching the polycrystalline silicon material to obtain an interdigital grid bus bar of a source region of the power device, wherein the interdigital grid bus bar is connected with a plurality of first grid trenches and is converged to a grid PAD;
the second grid electrodes are connected with the polysilicon short circuit areas, and the polysilicon short circuit areas are positioned in the emitter areas and are disconnected with the polysilicon bus bars through an etching process;
depositing a second oxide layer on the tops of the first grid electrode and the second grid electrode, and performing coverage protection on the first grid electrode and the second grid electrode;
providing a through hole in the first grid electrode and the source electrode region;
depositing a first metal layer on the top of the second oxide layer in a sputtering or vapor deposition mode, and respectively connecting the first metal layer with the grid region and the source region through the through holes;
and etching the first metal layer to obtain a grid electrode and a source electrode which are electrically isolated in the power device.
CN202310576995.5A 2023-05-19 2023-05-19 Power device primitive cell structure, power device and preparation method thereof Active CN116435352B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109755300A (en) * 2018-11-28 2019-05-14 株洲中车时代电气股份有限公司 A kind of trench IGBT chip
CN110379852A (en) * 2019-08-21 2019-10-25 江苏中科君芯科技有限公司 The groove-shaped IGBT device of miller capacitance can be reduced
CN111129129A (en) * 2018-10-30 2020-05-08 株洲中车时代电气股份有限公司 Accompany bars and float type trench gate IGBT chip
CN111916495A (en) * 2020-06-18 2020-11-10 南瑞联研半导体有限责任公司 Trench type IGBT chip active area edge structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009005914B4 (en) * 2008-01-28 2014-02-13 Denso Corporation Semiconductor device with insulated gate semiconductor element and insulated gate bipolar transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111129129A (en) * 2018-10-30 2020-05-08 株洲中车时代电气股份有限公司 Accompany bars and float type trench gate IGBT chip
CN109755300A (en) * 2018-11-28 2019-05-14 株洲中车时代电气股份有限公司 A kind of trench IGBT chip
CN110379852A (en) * 2019-08-21 2019-10-25 江苏中科君芯科技有限公司 The groove-shaped IGBT device of miller capacitance can be reduced
CN111916495A (en) * 2020-06-18 2020-11-10 南瑞联研半导体有限责任公司 Trench type IGBT chip active area edge structure

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