CN116387153A - IGBT wafer processing technology - Google Patents

IGBT wafer processing technology Download PDF

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Publication number
CN116387153A
CN116387153A CN202211106038.8A CN202211106038A CN116387153A CN 116387153 A CN116387153 A CN 116387153A CN 202211106038 A CN202211106038 A CN 202211106038A CN 116387153 A CN116387153 A CN 116387153A
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China
Prior art keywords
wafer
carrier plate
igbt
ild layer
front surface
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Pending
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CN202211106038.8A
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Inventor
严立巍
朱亦峰
刘文杰
马晴
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Zhejiang Tongxinqi Technology Co ltd
Zhongsheng Kunpeng Optoelectronic Semiconductor Co ltd
Original Assignee
Zhejiang Tongxinqi Technology Co ltd
Zhongsheng Kunpeng Optoelectronic Semiconductor Co ltd
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Priority to CN202211106038.8A priority Critical patent/CN116387153A/en
Publication of CN116387153A publication Critical patent/CN116387153A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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Abstract

The invention discloses an IGBT wafer processing technology, and belongs to the field of semiconductors. The method comprises the following steps: depositing an ILD layer on the front side of the IGBT wafer with the deep trench gate; attaching a first carrier plate to the front surface of a wafer with an ILD layer, coating a first blocking layer at the joint of the first carrier plate and the wafer to fix the wafer and the first carrier plate, implanting ions into the back surface of the wafer, and activating the implanted ions by high-temperature tempering; manufacturing a reverse side metal coating on the back of the tempered wafer; attaching a second carrier plate to the back surface of the wafer, disconnecting the first plug, removing the first carrier plate, and coating the second plug to fix the second carrier plate and the wafer; etching the ILD layer to form a gentle slope contact hole, and filling the contact hole by sputtering thick film Al to form an Emittor structure of the IGBT; performing metal coating, yellow light and etching on the front surface of the wafer to form a front surface metal pattern and a PAD bonding area; and breaking the second blocking, and releasing the fixation of the second carrier plate and the wafer to finish the processing of the IGBT wafer.

Description

IGBT wafer processing technology
Technical Field
The invention relates to the field of semiconductors, in particular to an IGBT wafer processing technology.
Background
An insulated gate Bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) is a novel composite power device developed on the basis of a metal oxide field effect transistor (MOSFET) and a Bipolar transistor (Bipolar), and has MOS input and Bipolar output functions. The IGBT integrates the advantages of small on-state voltage drop, high current-carrying density, high voltage resistance, small power MOSFET driving power, high switching speed, high input impedance and good thermal stability of the Bipolar device, and is widely applied to the fields of alternating current motors, frequency converters, switching power supplies, lighting circuits, traction transmission and the like. As a core device of the power electronic converter, the power electronic converter lays a foundation for high frequency, miniaturization, high performance and high reliability of an application device. In the existing IGBT process, the bearing structure of the wafer cannot be suitable for bearing in high-temperature environments such as ion activation, and the like, so that the process steps are complicated.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides an IGBT wafer processing technology.
The aim of the invention can be achieved by the following technical scheme:
an IGBT wafer processing technology comprises the following steps:
s1, depositing an ILD layer on the front surface of an IGBT wafer with a deep trench gate;
s2, attaching the front surface of the wafer with the ILD layer to a first carrier plate, and coating a first blocking layer at the joint of the first carrier plate and the wafer to fix the wafer and the first carrier plate;
s3, turning over the first carrier plate to finish thinning the back surface of the wafer, implanting ions into the back surface of the wafer, and activating the implanted ions through high-temperature tempering;
s4, manufacturing a reverse side metal coating on the back of the tempered wafer;
s5, attaching a second carrier plate to the back surface of the wafer, disconnecting the first plug, integrally overturning the second carrier plate and the wafer, removing the first carrier plate, and coating the second plug to fix the second carrier plate and the wafer;
the second carrier plate is provided with a plurality of through holes, the wafer is fixed by suction through a sucker in a negative pressure manner, and then the first carrier plate, the second carrier plate and the wafer are integrally turned over;
s6, etching the ILD layer to form a gentle slope contact hole, and completely filling the contact hole by sputtering thick film Al to form an Emittor structure of the IGBT;
s7, performing metal coating, yellow light and etching on the front surface of the wafer to form a front surface metal pattern and a PAD bonding area;
s8, disconnecting the second blocking, and releasing the fixation of the second carrier plate and the wafer to finish the processing of the IGBT wafer.
The invention has the beneficial effects that:
according to the invention, the limitation of high-temperature tempering temperature after the glass plate is temporarily bonded by the traditional process and the defect that deep ions cannot be activated by laser local ion activation are overcome by permanently bonding the silicon-based carrier plate, so that the ultra-thin IGBT wafer can be processed, and the processing cost of the IGBT wafer is reduced.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic molding diagram of the process step S1 of the present invention;
FIG. 2 is a schematic molding diagram of the process step S2 of the present invention;
FIG. 3 is a schematic diagram illustrating the molding of the process step S3 of the present invention;
FIG. 4 is a schematic diagram illustrating the molding of the process step S4 of the present invention;
FIG. 5 is a schematic diagram illustrating the molding of step S5 of the present invention;
FIG. 6 is a schematic diagram of the process step S6 of the present invention;
FIG. 7 is a schematic diagram of the process step S7 of the present invention;
FIGS. 8 and 9 are schematic diagrams illustrating the process step S8 of the present invention;
fig. 10 to 16 are partially enlarged schematic views of A, B, C, D, F, G, H in the above drawings, respectively.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In some embodiments of the present invention, a wafer processing method is disclosed, comprising the steps of:
s1, depositing an ILD layer 6 on the front surface of an IGBT wafer 1 with a deep trench 7 gate;
s2, attaching the front surface of the wafer with the ILD layer to the first carrier plate 3, and coating a first blocking layer 2 at the joint of the first carrier plate 3 and the wafer 1 to fix the wafer 1 and the first carrier plate 3;
s3, turning over the first carrier plate 3 to finish thinning the back surface of the wafer 1, implanting ions 8 into the back surface of the wafer 1, and activating the implanted ions through high-temperature tempering;
s4, manufacturing a reverse side metal coating 9 on the back side of the tempered wafer 1;
s5, attaching a second carrier plate 5 to the back surface of the wafer 1, disconnecting the first plug 2, integrally overturning the second carrier plate 5 and the wafer 1, removing the first carrier plate 3, and coating the second plug 4 to fix the second carrier plate 5 and the wafer 1;
the second carrier plate 5 is provided with a plurality of through holes 13, the wafer is fixed by suction through the suction disc 10 in a negative pressure manner, and then the whole overturning of the first carrier plate 3, the second carrier plate 5 and the wafer 1 is carried out;
s6, etching the ILD layer to form a gentle slope contact hole 11, and completely filling the contact hole by sputtering thick film Al to form an Emittor structure of the IGBT;
s7, performing metal coating, yellow light and etching on the front surface of the wafer to form a front metal pattern and a PAD bonding area 12;
s8, disconnecting the second plug 4, and releasing the fixation of the second carrier plate 5 and the wafer 1 to finish the processing of the IGBT wafer.
In the description of the present specification, the descriptions of the terms "one embodiment," "example," "specific example," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims.

Claims (6)

1. The IGBT wafer processing technology is characterized by comprising the following steps of:
s1, depositing an ILD layer on the front surface of an IGBT wafer with a deep trench gate;
s2, attaching the front surface of the wafer with the ILD layer to a first carrier plate, and coating a first blocking layer at the joint of the first carrier plate and the wafer to fix the wafer and the first carrier plate;
s3, turning over the first carrier plate to finish thinning the back surface of the wafer, implanting ions into the back surface of the wafer, and activating the implanted ions through high-temperature tempering;
s4, manufacturing a reverse side metal coating on the back of the tempered wafer;
s5, attaching a second carrier plate to the back surface of the wafer, disconnecting the first plug, integrally overturning the second carrier plate and the wafer, removing the first carrier plate, and coating the second plug to fix the second carrier plate and the wafer;
s6, etching the ILD layer to form a gentle slope contact hole, and completely filling the contact hole by sputtering thick film Al to form an Emittor structure of the IGBT;
s7, performing metal coating, yellow light and etching on the front surface of the wafer to form a front surface metal pattern and a PAD bonding area;
s8, disconnecting the second blocking, and releasing the fixation of the second carrier plate and the wafer to finish the processing of the IGBT wafer.
2. The IGBT wafer processing technology according to claim 1, wherein the sidewall inclination angle of the gentle slope contact hole in step S6 is 75 to 85 °, and the temperature is > 400 ℃ when sputtering thick film Al.
3. The IGBT wafer processing process according to claim 1, wherein the ILD layer deposition method in step S1 is one of LPCVD, APCVD, and PECVD, the LID layer bottom layer is undoped dielectric, and the ILD layer upper layer is P-doped dielectric.
4. The IGBT wafer processing technology according to claim 1, wherein the high temperature tempering temperature in step S202 is 800-1400 ℃, and the temperature rising rate of the high temperature furnace tube is less than 15 ℃/min.
5. The IGBT wafer processing technology according to claim 1, wherein the thickness of the thinned wafer back surface in step S3 is less than 150um, and the high temperature tempering is heated by a furnace tube or a rapid LAMP heating device RTP.
6. The IGBT wafer processing technology according to claim 1, wherein the second carrier plate is provided with a plurality of through holes, the wafer is fixed by suction of suction cup negative pressure, and then the first carrier plate, the second carrier plate and the wafer are integrally turned.
CN202211106038.8A 2022-09-09 2022-09-09 IGBT wafer processing technology Pending CN116387153A (en)

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Application Number Priority Date Filing Date Title
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