CN112786448B - Processing technology of IGBT wafer - Google Patents
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- CN112786448B CN112786448B CN202110273974.7A CN202110273974A CN112786448B CN 112786448 B CN112786448 B CN 112786448B CN 202110273974 A CN202110273974 A CN 202110273974A CN 112786448 B CN112786448 B CN 112786448B
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- 238000005516 engineering process Methods 0.000 title claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 61
- 239000010703 silicon Substances 0.000 claims abstract description 61
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 60
- 239000011521 glass Substances 0.000 claims abstract description 24
- 238000005496 tempering Methods 0.000 claims abstract description 22
- 150000002500 ions Chemical class 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 230000008569 process Effects 0.000 claims abstract description 11
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- 239000011248 coating agent Substances 0.000 claims abstract description 7
- 238000000576 coating method Methods 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims abstract description 6
- 230000003213 activating effect Effects 0.000 claims abstract description 3
- 238000010438 heat treatment Methods 0.000 claims description 12
- 238000004140 cleaning Methods 0.000 claims description 10
- 238000000227 grinding Methods 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 5
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 abstract description 90
- 230000004913 activation Effects 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 238000000465 moulding Methods 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
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Abstract
The invention discloses a processing technology of an IGBT wafer, which comprises the following steps: a processing technology of an IGBT wafer comprises the following steps: s1, depositing an ILD layer on the front surface of the IGBT wafer; s2, permanently bonding a silicon-based carrier plate on the front surface of the wafer; s3, thinning the back of the wafer, implanting ions and activating; s4, manufacturing a reverse metal coating; s5, bonding the glass carrier plate on the back of the wafer temporarily, and removing the silicon-based carrier plate; s6, etching the ILD layer to form a gradual slope contact hole, and sputtering thick film Al to fill the contact hole; s7, completing the front process of the wafer; and S8, bonding and removing the glass carrier plate. The invention overcomes the limitation of high-temperature tempering temperature after the glass plate is temporarily bonded in the traditional process and the defect that deep ions can not be activated by laser local ion activation by permanently bonding the silicon-based carrier plate, can process ultrathin IGBT wafers and reduces the processing cost of I GBT wafers.
Description
Technical Field
The invention relates to the field of IGBT chip processing, in particular to a processing technology of an IGBT wafer.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a novel composite power device developed on the basis of a metal oxide field effect Transistor (MOSFET) and a Bipolar Transistor (Bipolar), and has MOS input and Bipolar output functions. The IGBT integrates the advantages of small on-state voltage drop, large current-carrying density, high voltage resistance, small driving power of the power MOSFET, high switching speed, high input impedance and good thermal stability, and is widely applied to the fields of alternating current motors, frequency converters, switching power supplies, lighting circuits, traction transmission and the like. As a core device of the power electronic converter, the power electronic converter lays a foundation for high frequency, miniaturization, high performance and high reliability of application devices.
The IGBT chip is structurally composed of tens of thousands of cells (repeating units), and is manufactured technically by using a large-scale integrated circuit technology and a power device technology. Each cell structure can be divided into three parts, namely a body structure, a front-side MOS structure and a back-side collector region structure. The processing of the ultrathin wafer is realized by bonding the glass carrier plate in the existing IGBT chip manufacturing process so as to overcome the problem that the ultrathin wafer is fragile, but a high-temperature manufacturing process can not be carried out after the glass carrier plate is bonded, for example, high-temperature tempering is needed to activate ions after back ion implantation, so that laser local activation is usually adopted after the back ion implantation in the existing IGBT chip manufacturing process, but laser can only carry out shallow ion activation, and deep ion activation is not easy to realize.
Disclosure of Invention
In order to solve the defects mentioned in the background technology, the invention aims to provide a processing technology of an IGBT wafer, the invention skips the step of opening contact holes after an ILD layer is manufactured, the ILD layer is permanently bonded with a silicon wafer, back ion implantation and activation are directly performed, a glass carrier plate is temporarily bonded on the back of the wafer after the back process of the wafer is manufactured, then the silicon wafer is ground and etched to remove the silicon wafer, and then the ILD layer is opened and the subsequent processes are performed.
The purpose of the invention can be realized by the following technical scheme:
a processing technology of an IGBT wafer comprises the following steps:
s1, depositing an ILD layer on the front surface of the IGBT wafer with the deep trench gate;
s2, permanently bonding the silicon-based carrier plate on the front surface of the wafer with the well-made ILD layer;
s3, turning over the silicon-based carrier plate to finish thinning the back of the wafer, implanting ions into the back of the wafer, and activating the implanted ions through high-temperature tempering;
s4, manufacturing a reverse metal coating on the back of the wafer after tempering treatment;
s5, bonding the glass carrier plate on the back of the wafer temporarily, turning over the glass carrier plate, and removing the silicon-based carrier plate by grinding and etching;
s6, etching the ILD layer to form a gentle slope contact hole, and completely filling the contact hole by sputtering thick film Al to form an Emittor structure of the IGBT;
s7, performing metal plating, yellow light and etching on the front surface of the wafer to form a front metal pattern and a PAD bonding area;
and S8, debonding, removing the glass carrier plate, cleaning and removing the adhesion layer, and finishing the processing of the IGBT wafer.
Further preferably, the ILD layer deposition method in step S1 is one of LPCVD, APCVD and PECVD, the bottom layer of the LID layer is an undoped dielectric, and the upper layer of the ILD layer is a P-doped dielectric.
Further preferably, the method for permanently bonding the silicon-based carrier on the front surface of the wafer in step S2 includes the following steps:
s201, cleaning the surfaces of the silicon-based carrier plate and the IGBT wafer ILD layer, removing a natural oxide layer, and exciting the atomic active bonds of the silicon-based carrier plate by processing the surface of the silicon-based carrier plate through plasma;
s202, bonding the IGBT wafer on the surface of the silicon-based carrier plate, and then putting the IGBT wafer and the silicon-based carrier plate together into a high-temperature furnace tube for high-temperature tempering to enable the IGBT wafer LID layer and the silicon-based carrier plate to form a permanent bonding structure.
Further preferably, the temperature of the high temperature tempering in the step S202 is 800-.
Further preferably, in step S3, the wafer back side is thinned to a thickness of < 150um, and the wafer is heated by a furnace tube or a rapid LAMP heating device RTP during high temperature tempering.
Further preferably, the inclination angle of the side wall of the gentle slope contact hole in the step S6 is 75-85 ℃, and the temperature is more than 400 ℃ when thick film Al is sputtered.
The invention has the beneficial effects that:
compared with the traditional IGBT wafer manufacturing process, the processing process of the IGBT wafer provided by the invention has the advantages that the step of opening the contact hole is skipped after the ILD layer is manufactured, the ILD layer is permanently bonded with the silicon wafer, back side ion implantation and activation are directly performed, the back side of the wafer is temporarily bonded with the glass carrier plate after the wafer back side manufacturing process is completed, then the silicon wafer is ground and etched to remove the silicon wafer, and then the ILD layer is opened and the subsequent manufacturing process is performed. The invention overcomes the limitation of high-temperature tempering temperature after the glass plate is temporarily bonded in the traditional process and the defect that deep ions can not be activated by laser local ion activation by permanently bonding the silicon-based carrier plate, can process ultrathin IGBT wafers and reduces the processing cost of the IGBT wafers.
Drawings
The invention will be further described with reference to the accompanying drawings.
FIG. 1 is a schematic molding diagram of step S1 of the process of the present invention;
FIG. 2 is a schematic molding diagram of step S2 of the process of the present invention;
FIG. 3 is a schematic molding diagram of step S3 of the present invention;
FIG. 4 is a schematic molding diagram of step S4 of the present invention;
FIG. 5 is a schematic molding diagram of step S5 of the present invention;
FIG. 6 is a schematic molding diagram of step S6 of the present invention;
FIG. 7 is a schematic molding diagram of process step S7 according to the present invention;
FIG. 8 is a schematic molding diagram of step S8 of the present invention;
in the figure:
the manufacturing method comprises the steps of 1-IGBT wafer, 2-ILD layer, 3-deep groove, 4-silicon substrate, 5-ion implantation layer, 6-back metal coating, 7-adhesion layer, 8-glass substrate, 9-contact hole and 10-front surface PAD.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "opening," "upper," "lower," "thickness," "top," "middle," "length," "inner," "peripheral," and the like are used in an orientation or positional relationship that is merely for convenience in describing and simplifying the description, and do not indicate or imply that the referenced component or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the present invention.
Example 1
A processing technology of an IGBT wafer comprises the following steps:
s1, depositing an ILD layer on the front surface of the IGBT wafer with the deep trench gate through LPCVD, wherein the bottom layer of the LID layer is an undoped dielectric medium, and the upper layer of the ILD layer is a dielectric medium doped with P;
s2, permanently bonding the silicon-based carrier plate on the front surface of the wafer with the well-made ILD layer;
s3, turning over the silicon-based carrier plate to thin the back of the wafer to 40um, implanting ions into the back of the wafer, heating the wafer through a furnace tube or a rapid LAMP heating device RTP, and performing high-temperature tempering to activate the implanted ions;
s4, manufacturing a reverse metal coating on the back of the wafer after tempering treatment;
s5, bonding the glass carrier plate on the back of the wafer temporarily, turning over the glass carrier plate, and removing the silicon-based carrier plate by grinding and etching;
s6, etching the ILD layer to form a gentle slope contact hole with a side wall inclination angle of 75 degrees, sputtering thick film Al at 450 ℃, and completely filling the contact hole to form an Emittor structure of the IGBT;
s7, performing metal plating, yellow light and etching on the front surface of the wafer to form a front metal pattern and a PAD bonding area;
and S8, debonding, removing the glass carrier plate, cleaning and removing the adhesion layer, and finishing the processing of the IGBT wafer.
The method for permanently bonding the silicon-based carrier plate to the front surface of the wafer in the step S2 includes the following steps:
s201, cleaning the surfaces of the silicon-based carrier plate and the IGBT wafer ILD layer, removing a natural oxide layer, and exciting the atomic active bonds of the silicon-based carrier plate by processing the surface of the silicon-based carrier plate through plasma;
s202, bonding the IGBT wafer on the surface of the silicon-based carrier plate, then putting the IGBT wafer and the silicon-based carrier plate together into a high-temperature furnace tube, heating to 1200 ℃ at the speed of 10 ℃/min, and carrying out high-temperature tempering to enable the IGBT wafer LID layer and the silicon-based carrier plate to form a permanent bonding structure.
Example 2
A processing technology of an IGBT wafer comprises the following steps:
s1, depositing an ILD layer on the front surface of the IGBT wafer with the deep trench gate through APCVD, wherein the bottom layer of the LID layer is an undoped dielectric medium, and the upper layer of the ILD layer is a dielectric medium doped with P;
s2, permanently bonding the silicon-based carrier plate on the front surface of the wafer with the well-made ILD layer;
s3, turning over the silicon-based carrier plate to thin the back of the wafer to 80um, implanting ions into the back of the wafer, heating the wafer by a furnace tube or a rapid LAMP heating device RTP, and performing high-temperature tempering to activate the implanted ions;
s4, manufacturing a reverse metal coating on the back of the wafer after tempering treatment;
s5, bonding the glass carrier plate on the back of the wafer temporarily, turning the glass carrier plate, and removing the silicon-based carrier plate by grinding and etching;
s6, etching the ILD layer to form a gentle slope contact hole with the side wall inclined angle of 80 degrees, sputtering thick film Al at 500 ℃, and completely filling in the contact hole to form an Emittor structure of the IGBT;
s7, performing metal plating, yellow light and etching on the front surface of the wafer to form a front metal pattern and a PAD bonding area;
and S8, laser de-bonding, removing the glass carrier plate, cleaning and removing the adhesion layer, and finishing the processing of the IGBT wafer.
The method for permanently bonding the silicon-based carrier plate to the front surface of the wafer in the step S2 includes the following steps:
s201, cleaning the surfaces of the silicon-based carrier plate and the IGBT wafer ILD layer, removing a natural oxide layer, and exciting the atomic active bonds of the silicon-based carrier plate by processing the surface of the silicon-based carrier plate through plasma;
s202, bonding the IGBT wafer on the surface of the silicon-based carrier plate, then putting the IGBT wafer and the silicon-based carrier plate together into a high-temperature furnace tube, heating to 1400 ℃ at the speed of 8 ℃/min, and carrying out high-temperature tempering to enable the IGBT wafer LID layer and the silicon-based carrier plate to form a permanent bonding structure.
Example 3
A processing technology of an IGBT wafer comprises the following steps:
s1, depositing an ILD layer on the front surface of the IGBT wafer with the deep trench gate through PECVD, wherein the bottom layer of the LID layer is an undoped dielectric medium, and the upper layer of the ILD layer is a dielectric medium doped with P;
s2, permanently bonding the silicon-based carrier plate on the front surface of the wafer with the well-made ILD layer;
s3, turning over the silicon-based carrier plate to thin the back of the wafer to 140um, implanting ions into the back of the wafer, heating the wafer by a furnace tube or a rapid LAMP heating device RTP, and performing high-temperature tempering to activate the implanted ions;
s4, manufacturing a reverse metal coating on the back of the wafer after tempering treatment;
s5, bonding the glass carrier plate on the back of the wafer temporarily, turning over the glass carrier plate, and removing the silicon-based carrier plate by grinding and etching;
s6, etching the ILD layer to form a gentle slope contact hole with the side wall inclined angle of 85 degrees, sputtering thick film Al at 550 ℃, and completely filling in the contact hole to form an Emittor structure of the IGBT;
s7, performing metal plating, yellow light and etching on the front surface of the wafer to form a front metal pattern and a PAD bonding area;
and S8, laser de-bonding, removing the glass carrier plate, cleaning and removing the adhesion layer, and finishing the processing of the IGBT wafer.
The method for permanently bonding the silicon-based carrier plate to the front surface of the wafer in the step S2 includes the following steps:
s201, cleaning the surfaces of the silicon-based carrier plate and the IGBT wafer ILD layer, removing a natural oxide layer, and exciting the atomic active bonds of the silicon-based carrier plate by processing the surface of the silicon-based carrier plate through plasma;
s202, bonding the IGBT wafer on the surface of the silicon-based carrier plate, then putting the IGBT wafer and the silicon-based carrier plate together into a high-temperature furnace tube, heating to 800 ℃ at the speed of 12 ℃/min, and carrying out high-temperature tempering to enable the IGBT wafer LID layer and the silicon-based carrier plate to form a permanent bonding structure.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (5)
1. The processing technology of the IGBT wafer is characterized by comprising the following steps:
s1, depositing an ILD layer on the front surface of the IGBT wafer with the deep trench gate;
s2, permanently bonding the silicon-based carrier plate on the front surface of the wafer with the well-prepared ILD layer;
s3, turning over the silicon-based carrier plate to finish thinning the back of the wafer, implanting ions into the back of the wafer, and activating the implanted ions through high-temperature tempering;
s4, manufacturing a reverse metal coating on the back of the wafer after tempering treatment;
s5, bonding the glass carrier plate on the back of the wafer temporarily, turning over the glass carrier plate, and removing the silicon-based carrier plate by grinding and etching;
s6, etching the ILD layer to form a gentle slope contact hole, and completely filling the contact hole by sputtering thick film Al to form an Emittor structure of the IGBT;
s7, performing metal plating, yellow light and etching on the front surface of the wafer to form a front metal pattern and a PAD bonding area;
s8, bonding, removing the glass carrier plate, cleaning and removing the adhesion layer to complete the processing of the IGBT wafer;
the method for permanently bonding the silicon-based carrier plate to the front surface of the wafer in the step S2 includes the following steps:
s201, cleaning the surfaces of the silicon-based carrier plate and the IGBT wafer ILD layer, removing a natural oxide layer, and exciting the atomic active bonds of the silicon-based carrier plate by processing the surface of the silicon-based carrier plate through plasma;
s202, bonding the IGBT wafer on the surface of the silicon-based carrier plate, and then putting the IGBT wafer and the silicon-based carrier plate together into a high-temperature furnace tube for high-temperature tempering to enable the IGBT wafer LID layer and the silicon-based carrier plate to form a permanent bonding structure.
2. The process of claim 1, wherein the ILD layer deposition method in step S1 is one of LPCVD, APCVD and PECVD, the bottom ILD layer is undoped dielectric, and the top ILD layer is P-doped dielectric.
3. The processing technology of the IGBT wafer according to claim 1, wherein the temperature of the high temperature tempering in the step S202 is 800-1400 ℃, and the temperature rise rate of the high temperature furnace tube is less than 15 ℃/min.
4. The processing technology of the IGBT wafer according to claim 1, wherein the thickness of the wafer back side is reduced to be less than 150um in the step S3, and the high-temperature tempering is performed by heating through a furnace tube or a rapid LAMP heating device (RTP).
5. The processing technology of the IGBT wafer according to claim 1, wherein the side wall inclination angle of the gentle slope-shaped contact hole in the step S6 is 75-85 degrees, and the temperature is more than 400 ℃ when thick film Al is sputtered.
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| CN103050480B (en) * | 2012-08-14 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | The back-patterned process of silicon chip |
| US20140306284A1 (en) * | 2013-04-12 | 2014-10-16 | Infineon Technologies Austria Ag | Semiconductor Device and Method for Producing the Same |
| CN111799178B (en) * | 2020-07-17 | 2022-02-01 | 绍兴同芯成集成电路有限公司 | Double-sided copper-plating thick film process for ultrathin wafer |
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| CN106531700A (en) * | 2016-12-06 | 2017-03-22 | 江阴长电先进封装有限公司 | Chip packaging structure and packaging method |
| CN110379780A (en) * | 2019-07-31 | 2019-10-25 | 中国电子科技集团公司第五十八研究所 | A kind of silicon substrate fan-out-type wafer-level packaging method and structure |
| CN111599754A (en) * | 2020-06-19 | 2020-08-28 | 绍兴同芯成集成电路有限公司 | Ultrathin wafer processing technology |
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