CN116321817A - Manufacturing method of high-lamination-precision LTCC circuit substrate - Google Patents
Manufacturing method of high-lamination-precision LTCC circuit substrate Download PDFInfo
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- CN116321817A CN116321817A CN202310377521.8A CN202310377521A CN116321817A CN 116321817 A CN116321817 A CN 116321817A CN 202310377521 A CN202310377521 A CN 202310377521A CN 116321817 A CN116321817 A CN 116321817A
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- 239000000758 substrate Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000000919 ceramic Substances 0.000 claims abstract description 109
- 230000003068 static effect Effects 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 31
- 230000005611 electricity Effects 0.000 claims abstract description 29
- 238000003475 lamination Methods 0.000 claims abstract description 28
- 238000002955 isolation Methods 0.000 claims abstract description 23
- 229910052573 porcelain Inorganic materials 0.000 claims abstract description 16
- 238000007731 hot pressing Methods 0.000 claims abstract description 14
- 239000002390 adhesive tape Substances 0.000 claims abstract description 12
- 238000001179 sorption measurement Methods 0.000 claims abstract description 8
- 238000005538 encapsulation Methods 0.000 claims abstract description 5
- 238000005245 sintering Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims 2
- 238000010344 co-firing Methods 0.000 abstract description 4
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 19
- 229910000831 Steel Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000010959 steel Substances 0.000 description 5
- 239000000084 colloidal system Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 239000000741 silica gel Substances 0.000 description 4
- 229910002027 silica gel Inorganic materials 0.000 description 4
- 238000009461 vacuum packaging Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/061—Lamination of previously made multilayered subassemblies
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/068—Features of the lamination press or of the lamination process, e.g. using special separator sheets
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a manufacturing method of a high lamination precision LTCC circuit substrate, which comprises the following steps: in the lamination process, a plane carrying platform is arranged for placing the isolating film and the green ceramic chip, and the carrying platform is placed on an insulating table top; fixing the isolation film on the carrier by using an adhesive tape, aligning the ceramic surface of the first raw ceramic chip with the isolation film downwards, and adsorbing the raw ceramic chip on the isolation film by using static electricity generated by the static electricity generator; removing the back film of the raw ceramic chip, inhibiting deformation of the raw ceramic chip by electrostatic adsorption at the moment, and then sequentially generating static electricity, aligning and removing the back film of the rest raw ceramic chips according to the same method to complete lamination; tearing off the adhesive tape, and dispensing and fixing the side wall of the stacked multilayer circuit green porcelain body; and the green ceramic stacked body and the isolating film are encapsulated by using a vacuum encapsulation bag and then subjected to hot pressing, and the co-firing treatment of the LTCC circuit substrate is completed through a co-firing process, so that the high lamination precision of the LTCC circuit substrate is realized and the performance of the LTCC circuit substrate is improved.
Description
Technical Field
The invention relates to the field of LTCC substrates, in particular to a manufacturing method of a high-lamination-precision LTCC circuit substrate.
Background
LTCC (low temperature cofired ceramic) technology is a high density, multilayer wiring circuit substrate and packaging technology that utilizes mechanical or laser drilling, via metallization, conductor printing, lamination, and sintering processes to achieve fabrication of the circuit substrate. The LTCC technology can form passive elements inside the circuit substrate, and combines the surface mounting technology of the active devices to realize the manufacture of high-density and high-integration assemblies, so that the LTCC technology is a preferred mode for integrating and modularizing electronic devices in the future.
The lamination process of LTCC substrates is a very demanding process for precision. After the through hole metallization and the precise routing printing are finished on the single-layer green ceramic chip, the green ceramic chip with the circuit pattern becomes weaker, and particularly after the constraint of the back film is removed, the green ceramic chip can shrink freely to generate deformation, the deformation of the green ceramic chip is aggravated in the subsequent processing and carrying processes of the single-layer green ceramic chip, so that the alignment deviation among the green ceramic chip layers in the lamination process is increased, and the electrical property of the substrate is finally affected. Meanwhile, in the subsequent assembly process of the substrate, the alignment precision deviation between the substrate layers can increase the transmission loss of signals and influence the electrical performance of the component.
At present, two methods for controlling the lamination precision of the substrate are mainly used:
mode one: the method needs to remove the back film of the raw ceramic chip and then open and laminate the cavity, has higher requirements on the consistency of the operation method of operators, and is generally suitable for manufacturing high-frequency circuit substrates with low frequency or partial alignment requirements. According to different circuit pattern designs, a plurality of pin plates with the same or different sizes are required in the processing process, and the production and management cost is increased. The use rate and the production efficiency of the green ceramic chip are reduced by designing and processing the positioning holes on the green ceramic chip.
Mode two: the alignment hole is designed, automatic lamination equipment is used for alignment and lamination, the lamination equipment carries the raw ceramic chips to an operation carrying table through a vacuum suction nozzle, then CCD is used for visual alignment, the raw ceramic chips are fixed between layers in a hot pressing or dispensing mode, the alignment precision is relatively high, the pressure generated during hot pressing can cause certain deformation of each layer of raw ceramic chips, and the accumulated deformation when the number of layers of the substrate is more can influence or even exceed the range of a required value; the method of dispensing needs to remove the back film in advance and then carry the raw ceramic chip to a carrying platform for dispensing and fixing, and the deformation is increased due to the lack of back film support of the raw ceramic chip in the carrying process.
Disclosure of Invention
In order to overcome the defects in the prior art and obtain the LTCC substrate with higher lamination precision, the invention provides a manufacturing method of the circuit substrate, which reduces the signal transmission loss and improves the electrical performance of the component. The invention solves the technical problems that: overcomes the defects of the prior art, and provides the LTCC substrate with high lamination precision, which is obtained by utilizing static electricity generated by a static generator and adopting a mode of applying force to the surface to adsorb the raw ceramic chips, and then tearing the film and laminating the film.
In order to achieve the above object, the present invention provides the following technical solutions:
a manufacturing method of a high lamination precision LTCC circuit substrate comprises the following steps:
step one: in the lamination process, a plane carrying platform is arranged for placing the isolating film and the green ceramic chip, and the carrying platform is required to be placed on an insulating table top;
step two: fixing the isolation film on the carrier by using an adhesive tape, aligning the ceramic surface of the first raw ceramic chip with the isolation film downwards, and adsorbing the raw ceramic chip on the isolation film by using static electricity generated by the static electricity generator;
step three: removing the back film of the raw ceramic chip in the second step, wherein the raw ceramic chip inhibits deformation by electrostatic adsorption, and then sequentially generating static electricity, aligning and removing the back film of the rest raw ceramic chips according to the same method to complete lamination;
step four: tearing the adhesive tape in the second step, and dispensing and fixing the side wall of the multi-layer circuit green porcelain body stacked in the third step.
Step five: and (3) encapsulating the raw ceramic stacked body and the isolating film in the fourth step by using a vacuum encapsulation bag, and then performing hot pressing and sintering to finish the manufacture of the LTCC circuit substrate with high lamination precision, thereby realizing the high lamination precision of the LTCC circuit substrate.
In the first step, a planar carrier is required to be set in advance when the products are laminated, the carrier is made of metal materials, the size of the carrier is larger than that of the isolating film, and the isolating film is required to be provided with alignment holes with the same positions and sizes as the green ceramic chips in advance, and the size of the alignment holes is not smaller than that of the green ceramic chips.
In the second step, four corners of the isolation film are fixed on the carrier by using adhesive tapes, static electricity is generated on the surface of the isolation film by using the output end of the static electricity generator, the first green ceramic chip is placed on the isolation film with the ceramic surface facing downwards, and after the first green ceramic chip is aligned with the isolation film by positioning Kong Jingzhun, the green ceramic chip is adsorbed on the surface of the isolation film.
Further, in the second step, the length of the output end of the electrostatic generator is larger than the size of the isolating film, and when the output end moves above the isolating film and the green ceramic chip, the moving area covers the surfaces of the isolating film and the green ceramic chip.
Further, in the second step, the power of the static generator is set to be 3 KV-30 KV, the distance between the output end and the raw ceramic chip is 1-20 cm, and the moving speed of the output end is 1-10 cm/s.
In the second step, the positioning holes on the green ceramic chip and the isolation film are made in a mechanical or laser mode, and the positions and the sizes of the positioning holes of each green ceramic chip and the isolation film are consistent.
Further, in the third step, removing the back film adsorbed with the green ceramic chips, and sequentially aligning, adsorbing and removing the back film of the rest green ceramic chips according to the same method based on the sequence of circuit design until stacking of all the green ceramic chips is completed.
Further, in the third step, when the back film of each green ceramic tile is peeled off, the peeling direction of each green ceramic tile is kept consistent.
Further, in the third step, the electrostatic generator makes the surface of the green ceramic tile from which the back film has been removed generate static electricity, and the electrostatic force between the green ceramic tile and the green ceramic tile to be stacked is greater than the binding force between the green ceramic tile to be stacked and the back film thereof. When the back film is removed, one corner of the green ceramic chip is lifted by using the anti-static tweezers and is slowly torn off along the diagonal direction, and the lifted back film needs to be kept in the horizontal direction.
In the third step, the last green ceramic tile is stacked, the adhesive tape on the isolating film is torn off after the back film of the green ceramic tile is torn off, and the stacked green ceramic blank and the isolating film are peeled off from the carrying platform.
In the fourth step, the colloid is smeared on the peripheral side walls of the green porcelain body, the positions of the green porcelain pieces are reinforced, and the colloid cannot flow into the product area.
Further, in the fifth step, a hot pressing device is used for hot pressing, and the pressure applied to the green body is uniformly applied.
Further, the hot pressing pressure is 3 Mpa-30 Mpa, the duration is 1-60 min, and the temperature is 30-90 ℃.
Further, in the fifth step, the green ceramic stacked body is hot-pressed for 1 to 10 times.
When the conventional LTCC is manufactured, the back film is required to be torn off before lamination or cavity opening is carried out on the raw ceramic chips, the binding is lost after the back film is torn off, and the interlayer alignment accuracy is reduced due to deformation of the raw ceramic chips. The high-lamination-precision LTCC substrate is obtained by utilizing static electricity generated by the static electricity generator, adopting a mode of applying force on a surface to adsorb raw ceramic chips, and then tearing and laminating the raw ceramic chips. Compared with the prior art, the invention has the following advantages:
(1) According to the invention, electrostatic adsorption is added in the lamination process, so that deformation can be inhibited by electrostatic adsorption after the back film is torn off from the raw porcelain, thereby improving interlayer alignment precision and improving the performance of the LTCC circuit substrate.
(2) The method has strong compatibility, has no special requirement on the state of the metal layer on the surface of the substrate, is suitable for stacking products of various base materials, can be compatible with stacking of substrates with various thickness and external dimensions, and can greatly improve the interlayer alignment precision of products with any thickness.
Drawings
Fig. 1 is a flow chart of a method for manufacturing a circuit substrate according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a laminate according to an embodiment of the present invention.
Detailed Description
The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
Fig. 1 schematically shows a flow chart of a method for manufacturing a circuit substrate according to an embodiment of the invention.
As shown in fig. 1, the method includes operation steps S101 to S105.
In operation S101, a planar stage is provided for placing a separator and green ceramic chips in a lamination process.
According to an embodiment of the invention, the carrier is a steel plate with the dimensions of 250mm by 250mm, the size of the isolating film is 203mm by 203mm, and the size of the raw ceramic chip is 203mm by 203mm.
According to the embodiment of the invention, the alignment holes of the isolating film and the green ceramic chip are round holes with phi 1mm, and are distributed at four corners of the green ceramic chip and the isolating film.
Fig. 2 schematically shows a sequence diagram of a stack.
According to the embodiment of the invention, the number of the carrying platform layers is 0-0, the number of the isolating film layers is 0-1, and a reference layer is provided for all raw ceramics to be laminated.
According to an embodiment of the present invention, the number of substrate layers is divided into top, 1, 2, 3, 4.
According to the embodiment of the invention, if the top layer green ceramic chip is processed with the cavity, the isolating film can process the cavity which is the same as the top layer green ceramic chip, so that the edge of the cavity of the top layer green ceramic chip is prevented from being damaged in the subsequent lamination.
In operation S102, the separation film is fixed on the carrier by using the adhesive tape, and the first green ceramic tile is aligned with the separation film, and then the green ceramic tile is adsorbed on the separation film by using the static electricity generated by the static electricity generator.
According to an embodiment of the present invention, the barrier film is attached to the carrier using a transparent adhesive tape, which may be attached to four corners of the barrier film.
According to the embodiment of the invention, the output end of the static generator is arranged above the isolating film, static electricity is generated on the surface of the isolating film, and after the top layer green ceramic chip and the isolating film are precisely aligned by utilizing the alignment holes at four corners, the top layer green ceramic chip is fixed on the isolating film.
According to the embodiment of the invention, in the subsequent lamination process, the object of static electricity generated by the output end of the static electricity generator is always a fixed green ceramic tile.
According to the embodiment of the invention, when the top layer of the product is laminated, the ceramic surface of the green ceramic chip is opposite to the isolating film, and the back film is upwards.
According to an embodiment of the present invention, the power of the electrostatic generator is set to 10KV.
According to an embodiment of the invention, the output end of the electrostatic generator is 15cm away from the green ceramic tile.
According to an embodiment of the invention, the movement speed of the output end of the static electricity generator is 2cm/s.
According to the embodiment of the invention, when static electricity is applied to the output end of the static electricity generator, the displacement direction is required to exceed the distance of 5cm from the front to the back of the green ceramic chip, so that the moving area of the output end is ensured to completely cover the surfaces of the isolation film and the green ceramic chip.
According to the embodiment of the invention, the green ceramic tile subjected to static electricity application through the static electricity generator is not placed for more than 2 hours, so that the reduction of static electricity effect and the influence on the interlayer adsorption strength of the green ceramic tile are avoided.
In operation S103, the back film of the adsorbed green ceramic tile is removed, and the rest green ceramic tiles are sequentially operated in the same manner.
According to the embodiment of the invention, the stripping treatment comprises the steps of using an anti-static tweezers to lift one corner of the back film of the top layer of the raw ceramic tile after the raw ceramic tile is tightly sucked by utilizing the electrostatic adsorption force, and tearing off the back film of the raw ceramic tile along the diagonal direction of the raw ceramic tile.
According to the embodiment of the invention, when the back film is removed from the raw ceramic chip, the lifted back film needs to be kept in a horizontal direction and removed slowly.
According to the embodiment of the invention, the 2 nd, 3 rd and 4 th layers are stacked together by static electricity according to a circuit design drawing, and static electricity generation, alignment and back film tearing are sequentially performed.
According to the embodiment of the invention, the green ceramic chip is subjected to electrostatic adsorption to avoid deformation generated after the back film is torn off.
In operation S104, the adhesive tape is torn off, and the side wall of the stacked multilayer circuit green ceramic body is fixed by dispensing.
According to the embodiment of the invention, the transparent adhesive tapes adhered to the four corners of the isolating film are slowly lifted, the isolating film and the raw porcelain stacking body are taken out from the carrying platform, and the isolating film of the raw porcelain stacking body is upwards placed on the tabletop.
According to the embodiment of the invention, a hairbrush is used for dipping the colloid, the colloid is smeared on the side wall of the raw porcelain stacking body for reinforcement, two points can be respectively smeared on each side of the raw porcelain stacking body, and the smearing width is 10 mm-20 mm.
In operation S105, the green ceramic stack and the isolation film are encapsulated by a vacuum encapsulation bag and then thermally pressed, and the co-firing process of the LTCC circuit board is completed by a co-firing process.
According to an embodiment of the present invention, the green ceramic stack and the separator are placed on a steel plate, the steel plate size being larger than the separator size.
According to the embodiment of the invention, the silica gel protective film is covered on the isolating film to relieve the pressure on the surface of the raw porcelain stacking body in the hot pressing process. The size of the silica gel protective film is required to be larger than that of the isolating film, and the silica gel protective film is fixed on the steel plate, the isolating film and the raw porcelain stacking body.
According to the embodiment of the invention, the silica gel protective film, the steel plate, the isolating film and the raw porcelain stacking body are put into a vacuum packaging bag together, and the vacuum packaging device is used for vacuumizing and sealing so as to prevent water from polluting the raw porcelain stacking body during subsequent warm water hot pressing.
According to an embodiment of the invention, the green ceramic stack after encapsulation is placed in a hot press apparatus at 70 ℃ and preheated for 5min, set at a pressure of 20MPa and pressurized for 10min.
According to the embodiment of the invention, after the hot pressing is finished, the water on the surface of the vacuum packaging bag is wiped clean, and the raw porcelain stacking body is taken out of the vacuum packaging bag.
According to the embodiment of the invention, the raw porcelain stacking body is placed into a sintering furnace for sintering, and the interlayer alignment precision of the LTCC circuit substrate after sintering is less than or equal to +/-15 mu m.
The foregoing embodiments have been provided for the purpose of illustrating the general principles of the present invention, and are not meant to limit the scope of the invention, but to limit the invention thereto.
What is not described in detail in the present specification is a known technology to those skilled in the art.
Claims (10)
1. The manufacturing method of the high-lamination-precision LTCC circuit substrate is characterized by comprising the following steps of:
step one: in the lamination process, a plane carrying platform is arranged for placing the isolating film and the green ceramic chip, and the carrying platform is placed on an insulating table top;
step two: fixing the isolation film on the carrier by using an adhesive tape, aligning the ceramic surface of the first raw ceramic chip with the isolation film downwards, and adsorbing the raw ceramic chip on the isolation film by using static electricity generated by the static electricity generator;
step three: removing the back film of the raw ceramic chip in the second step, wherein the raw ceramic chip inhibits deformation by electrostatic adsorption, and then carrying out static electricity generation, alignment and back film removal on the rest raw ceramic chips to complete lamination;
step four: tearing off the adhesive tape in the second step, and dispensing and fixing the side wall of the multilayer circuit green porcelain body stacked in the third step;
step five: and (3) encapsulating the raw ceramic stacked body and the isolating film in the fourth step by using a vacuum encapsulation bag, and then performing hot pressing and sintering to finish the manufacture of the high-lamination-precision LTCC circuit substrate.
2. The method of manufacturing a high overlay accuracy LTCC circuit board as recited in claim 1, wherein in the first step, the planar carrier is larger than the spacer, and the spacer is not smaller than the green tile.
3. The method of manufacturing a high overlay accuracy LTCC circuit board as recited in claim 1, wherein in the second step, the length of the output end of the electrostatic generator is greater than the size of the isolation film, and the moving area covers the surfaces of the isolation film and the green tile when the output end moves over the isolation film and the green tile.
4. The method of manufacturing a high lamination precision LTCC circuit board as defined in claim 1, wherein in the second step, the power of the electrostatic generator is set to 3 KV-30 KV, the output terminal is 1-20 cm away from the green ceramic chip, and the moving speed of the output terminal is 1-10 cm/s.
5. The method of manufacturing a high overlay accuracy LTCC circuit board as claimed in claim 1, wherein in the second step, the positioning holes on the green ceramic chip and the isolation film are made by mechanical or laser methods, and the positions and sizes of the positioning holes of each green ceramic chip and the isolation film are consistent.
6. The method of manufacturing a high overlay accuracy LTCC circuit board as recited in claim 1, wherein in the third step, the peeling direction of each green tile is kept uniform when the green tile back film is peeled.
7. The method of manufacturing a LTCC circuit board with high lamination accuracy as claimed in claim 1, wherein in the third step, the electrostatic generator generates static electricity on the surface of the green ceramic tile from which the back film has been peeled off, and the electrostatic force between the green ceramic tile and the green ceramic tile to be stacked is greater than the bonding force between the green ceramic tile to be stacked and the back film thereof.
8. The method of manufacturing a high overlay accuracy LTCC circuit board as recited in claim 1, wherein in step five, the hot pressing is performed using a hot pressing apparatus, and the pressure applied to the green body is uniform.
9. The method of manufacturing a high lamination precision LTCC circuit board as claimed in claim 8, wherein the hot pressing is performed at a pressure of 3Mpa to 30Mpa, a duration of 1 to 60min, and a temperature of 30 to 90 ℃.
10. The method of manufacturing a high overlay accuracy LTCC circuit board as recited in claim 1, wherein in step five, the green ceramic stack is hot pressed 1-10 times.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310377521.8A CN116321817A (en) | 2023-04-11 | 2023-04-11 | Manufacturing method of high-lamination-precision LTCC circuit substrate |
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| CN202310377521.8A CN116321817A (en) | 2023-04-11 | 2023-04-11 | Manufacturing method of high-lamination-precision LTCC circuit substrate |
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| CN116321817A true CN116321817A (en) | 2023-06-23 |
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| CN202310377521.8A Pending CN116321817A (en) | 2023-04-11 | 2023-04-11 | Manufacturing method of high-lamination-precision LTCC circuit substrate |
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