CN116314503A - Epitaxial wafer for Micro-LED, preparation method of epitaxial wafer and Micro-LED - Google Patents
Epitaxial wafer for Micro-LED, preparation method of epitaxial wafer and Micro-LED Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 230000004888 barrier function Effects 0.000 claims abstract description 28
- 230000000903 blocking effect Effects 0.000 claims abstract description 27
- 230000006911 nucleation Effects 0.000 claims abstract description 20
- 238000010899 nucleation Methods 0.000 claims abstract description 20
- 230000000737 periodic effect Effects 0.000 claims abstract description 13
- 239000012159 carrier gas Substances 0.000 claims description 47
- 229910052739 hydrogen Inorganic materials 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 5
- 238000005036 potential barrier Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 55
- 235000012431 wafers Nutrition 0.000 description 31
- 239000007789 gas Substances 0.000 description 14
- 230000000052 comparative effect Effects 0.000 description 11
- 229910002704 AlGaN Inorganic materials 0.000 description 10
- 230000006872 improvement Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 238000005452 bending Methods 0.000 description 5
- 230000010287 polarization Effects 0.000 description 5
- 229910052594 sapphire Inorganic materials 0.000 description 5
- 239000010980 sapphire Substances 0.000 description 5
- 238000005204 segregation Methods 0.000 description 5
- 230000009467 reduction Effects 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 230000005428 wave function Effects 0.000 description 2
- 229910018509 Al—N Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
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Abstract
The invention discloses an epitaxial wafer for a Micro-LED, a preparation method thereof and the Micro-LED, and relates to the field of semiconductor photoelectric devices. The epitaxial wafer for the Micro-LED comprises a substrate, and a nucleation layer, an intrinsic GaN layer, an N-GaN layer, a multiple quantum well layer, an electron blocking layer and a P-GaN layer which are sequentially arranged on the substrate, wherein the multiple quantum well layer is of a periodic structure, each period comprises a potential well layer and a barrier layer, and the potential well layer comprises an AlInN layer, an InN layer and an InGaN layer which are sequentially laminated; which is a kind ofWherein the AlInN layer surface is provided with a plurality of H-channels 2 And etching to obtain the nano holes. By implementing the invention, the luminous efficiency of the light-emitting diode can be improved, the uniformity of luminous wavelength can be improved, and the shift of luminous wavelength can be reduced.
Description
Technical Field
The invention relates to the field of semiconductor photoelectric devices, in particular to an epitaxial wafer for a Micro-LED, a preparation method of the epitaxial wafer and the Micro-LED.
Background
Currently, gaN-based light emitting diodes have been widely used in the field of solid state lighting as well as in the field of display, attracting more and more attention. Micro-LEDs are expected to promote the development of display screens to be light and thin, miniaturized, low in power consumption and high in brightness, and are known as the technology of the next-generation Micro-displays. At present, micro-LEDs provide higher requirements for external structures: (1) Under the conditions of the same epitaxial structure and the same chip structure, the Micro-LED can bring about the reduction of single-core brightness due to the reduction of the size and the surface area, so that the requirement on the luminous efficiency is higher; (2) Micro-LEDs cannot use traditional LED chip picking and sorting techniques, so that Micro-LED epitaxial wafers require higher wavelength uniformity; (3) Because of energy band bending caused by multi-quantum well lamination electric polarization, the light-emitting wavelength shifts when current with different magnitudes is injected, and the uniformity of Micro-LED display is not facilitated.
Disclosure of Invention
The invention aims to solve the technical problem of providing an epitaxial wafer for Micro-LEDs and a preparation method thereof, which can improve the luminous efficiency of the LEDs, improve the uniformity of luminous wavelength and reduce the shift of luminous wavelength.
The invention also solves the technical problems of providing a Micro-LED which has high luminous efficiency, good luminous wavelength uniformity and small luminous wavelength deviation.
In order to solve the problems, the invention discloses an epitaxial wafer for Micro-LEDs, which comprises a substrate, a nucleation layer, an intrinsic GaN layer, an N-GaN layer, a multiple quantum well layer, an electron blocking layer and a P-GaN layer which are sequentially arranged on the substrate, the multi-quantum well layer is of a periodic structure, each period comprises a potential well layer and a potential barrier layer, and the potential well layer comprises an AlInN layer, a barrier layer and a barrier layer which are sequentially laminated,An InN layer and an InGaN layer; wherein the AlInN layer surface is provided with a plurality of H-channels 2 And etching to obtain the nano holes.
As an improvement of the technical scheme, the ratio of Al component in the AlInN layer is 0.1-0.2, the ratio of in component is 0.3-0.5, and the thickness of the AlInN layer is 2-5 nm;
the ratio of an In component In the InN layer is 0.4-0.6, and the thickness of the InN layer is 0.5-2 nm;
the proportion of In components In the InGaN layer is 0.1-0.4, and the thickness of the InGaN layer is 0.5-2 nm.
As an improvement of the technical proposal, H 2 Etching treatment time is 10s-30s, treatment temperature is 900-1000 ℃, H 2 The inlet amount is 40slm-60slm.
As an improvement of the technical proposal, H is adopted for the InN layer 2 Atmosphere treatment, wherein the treatment time is 1s-5s, the treatment temperature is 900-1000 ℃, H 2 The inlet amount is 4slm-6slm.
As an improvement of the technical proposal, the electron blocking layer is of a periodic structure, the period number is 3-15, and each period comprises Al which are laminated in turn a Ga 1-a N layer and In b Ga 1-b An N layer, wherein a is 0.05-0.2, and b is 0.1-0.5;
single Al a Ga 1-a The thickness of the N layer is 2nm-8nm, and single In b Ga 1-b The thickness of the N layer is 2nm-8nm.
Correspondingly, the invention also discloses a preparation method of the epitaxial wafer for the Micro-LED, which is used for preparing the epitaxial wafer for the Micro-LED and comprises the following steps:
providing a substrate, and sequentially growing a nucleation layer, an intrinsic GaN layer, an N-GaN layer, a multiple quantum well layer, an electron blocking layer and a P-GaN layer on the substrate, wherein the multiple quantum well layer is of a periodic structure, each period comprises a potential well layer and a barrier layer, and the potential well layer comprises an AlInN layer, an InN layer and an InGaN layer which are sequentially laminated;
wherein, after the AlInN layer is grown, H is adopted 2 And etching to form a plurality of nano holes on the surface of the AlInN layer.
As an improvement of the technical scheme, the growth temperature of the AlInN layer is 700-800 ℃, the growth pressure is 100-500torr, and the carrier gas adopted in the growth is N 2 ；
The growth temperature of the InN layer is 700-800 ℃, the growth pressure is 100-500torr, and the carrier gas adopted in the growth is N 2 ；
The growth temperature of the InGaN layer is 700-800 ℃, the growth pressure is 100-500torr, and the carrier gas adopted in the growth is N 2 。
As an improvement of the technical proposal, H is adopted for the InN layer 2 Etching treatment is carried out;
H 2 the carrier gas adopted in the etching treatment is H 2 The method comprises the steps of carrying out a first treatment on the surface of the Or (b)
H 2 The carrier gas adopted in the etching treatment is H 2 And N 2 ，H 2 And N 2 The molar ratio of (2) to (1) to (10) to (1).
As an improvement of the above technical solution, the electron blocking layer includes Al a Ga 1-a N layer and In b Ga 1-b An N layer;
the Al is a Ga 1-a The growth temperature of the N layer is 900-1000 ℃ and the growth pressure is 100-500 torr;
the In is b Ga 1-b The growth temperature of the N layer is 900-1000 ℃ and the growth pressure is 100-500 torr.
Correspondingly, the invention also discloses a Micro-LED, which comprises the epitaxial wafer for the Micro-LED.
The implementation of the invention has the following beneficial effects:
1. in the epitaxial wafer for the Micro-LED, the potential well layer comprises an AlInN layer, an InN layer and an InGaN layer which are sequentially laminated; wherein, the surface of the AlInN layer is provided with a plurality of H-channels 2 And etching to obtain the nano holes.
Firstly, in the AlInN layer, as the bond energy of the Al-N bond is strong, the lattice stability can be improved, al atoms are smaller, and the lattice quality of the AlInN layer is better, so that the lattice quality of an epitaxial wafer can be improved and the luminous efficiency can be improved by arranging the AlInN layer;
secondly, the AlInN layer surface is provided with a plurality of nano holes, and the potential well layer with the nano holes forms a stress release space when receiving the compressive stress from the barrier layer, so that the compressive stress in the multi-quantum well layer is reduced, the piezoelectric polarization is reduced, the energy band bending is reduced, and the superposition of electrons and hole wave functions of the multi-quantum well layer is increased, thereby improving the luminous efficiency; in addition, due to the reduction of piezoelectric polarization, the energy band bending of the multiple quantum well layer is reduced, so that the generated wavelength offset is obviously reduced when the light-emitting diode is injected with currents of different magnitudes, and the consistency of the light-emitting diode under the currents of different magnitudes is greatly enhanced;
in addition, the InN layer grows on the AlInN layer, and the nano holes on the AlInN layer fully release the compressive stress from the barrier layer, so that the In component In the InN layer is more uniformly distributed, and the segregation phenomenon of the In component is obviously reduced due to the segmentation of the physical area of the nano holes, so that the uniformity of the luminous wavelength of the light-emitting diode is improved by combining the InN layer with the nano holes;
finally, according to the invention, the InGaN layer is grown on the InN layer, on one hand, the compensation of the In component is realized, and on the other hand, the InGaN material is more stable than the InN material, and the diffusion of the In component to the barrier layer is not easy to occur at the position close to the barrier layer.
2. In the epitaxial wafer for Micro-LEDs of the invention, a small amount of H is used 2 And (3) treating the surface of the InN layer, opening In clusters, desorbing an In component with poor growth lattice quality and low bond energy, further reducing In segregation In the potential well layer, and improving the uniformity of the light emitting wavelength.
Drawings
FIG. 1 is a schematic diagram of an epitaxial wafer for Micro-LEDs according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a well layer according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an electron blocking layer according to an embodiment of the present invention;
fig. 4 is a flowchart of a method for preparing an epitaxial wafer for Micro-LEDs according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below in order to make the objects, technical solutions and advantages of the present invention more apparent.
Referring to fig. 1-2, the invention discloses an epitaxial wafer for Micro-LEDs, which comprises a substrate 1, and a nucleation layer 2, an intrinsic GaN layer 3, an N-GaN layer 4, a multiple quantum well layer 5, an electron blocking layer 6 and a P-GaN layer 7 which are sequentially arranged on the substrate 1, wherein the multiple quantum well layer 5 is of a periodic structure, the number of periods is 3-15, and each period comprises a potential well layer 51 and a barrier layer 52.
The well layer 51 includes an AlInN layer 511, an InN layer 512, and an InGaN layer 513, which are sequentially stacked.
In the AlInN layer 511 of the present invention, since the al—n bond energy is strong, the lattice stability can be improved, and the Al atoms are smaller, and the lattice quality of the AlInN layer 511 is better, the lattice quality of the epitaxial wafer can be improved, and the light emitting efficiency can be improved by the arrangement of the AlInN layer 511. Wherein the radius of In atoms In AlInN layer 511 is larger, followed by H 2 Will be in contact with H during etching 2 And (3) performing reaction desorption to form nano holes. Specifically, the Al component in AlInN layer 511 has a ratio of 0.05 to 0.3, and if the Al component has a ratio of less than 0.05, it is difficult to effectively improve the lattice quality of potential well layer 51; if the Al component is more than 0.3, H is hindered 2 The etching of the nano holes is made to be smaller. Preferably, the Al component in the AlInN layer 511 has a ratio of 0.1 to 0.2, and exemplary is 0.12, 0.14, 0.16, or 0.18, but is not limited thereto.
Specifically, the In component has a ratio of 0.2 to 0.55, and if the In component has a ratio of < 0.2, the In component has a ratio too small to form nanoholes, and if the In component has a ratio of > 0.55, the lattice quality is degraded. Preferably, the AlInN layer 511 has an In component of 0.3 to 0.5, and exemplary is 0.32, 0.34, 0.36, 0.38, 0.4, 0.42, 0.44, 0.46, or 0.48, but is not limited thereto.
Specifically, the thickness of the AlInN layer 511 is 1nm-6nm, and if the thickness of the AlInN layer 511 is less than 1nm, the depth of the formed nano holes is too shallow, so that it is difficult to effectively improve the luminous efficiency; if the AlInN layer 511 has a thickness of > 6nm, excessive defects are caused. Preferably, the AlInN layer 511 has a thickness of 2nm to 5nm, and is exemplified by, but not limited to, 2.5nm, 3nm, 3.5nm, 4nm, or 4.5 nm.
Wherein the AlInN layer 511 has a plurality of H-channels on its surface 2 And etching to obtain the nano holes. The potential well layer 51 with the nano holes forms a stress release space when receiving the compressive stress from the barrier layer 52, reduces the compressive stress in the multiple quantum well layer 5, reduces piezoelectric polarization, reduces energy band bending, and increases the superposition of electron and hole wave functions of the multiple quantum well layer 5, thereby improving the luminous efficiency; in addition, due to the reduction of piezoelectric polarization, the energy band bending of the multiple quantum well layer 5 is reduced, so that the generated wavelength shift is obviously reduced when the light emitting diode is injected with currents of different magnitudes, and the consistency of the light emitting diode under the currents of different magnitudes is greatly enhanced.
Specifically, H 2 Etching treatment time is 10s-30s, treatment temperature is 900-1000 ℃, H 2 The inlet amount is 40slm-60slm. If the treatment time is less than 10s, the nano holes cannot be formed; if the treatment time is more than 30s, the uniformity of the nano holes is poor. Exemplary, H 2 The processing time is 15s, 20s or 25s, but is not limited thereto. If H 2 The inlet amount is less than 40slm, and the depth of the formed nano holes is smaller; if H 2 The amount of the introduced material is more than 60slm, which causes In loss. Exemplary, H 2 The amount of the air flow is 45slm, 50slm or 55slm, but is not limited thereto. The temperature of the treatment is exemplified by, but not limited to, 930 ℃, 950 ℃, or 980 ℃.
The InN layer 512 is grown on the etched AlInN layer 511, and the nano holes on the AlInN layer 511 fully release the compressive stress from the barrier layer 52, so that the In component In the InN layer 512 is more uniformly distributed, and the In component segregation phenomenon is obviously reduced due to the division of the physical area of the nano holes, and the light emitting wavelength uniformity of the light emitting diode is improved by combining the two.
Specifically, the In component In the InN layer 512 has a duty ratio of 0.3-0.65, and if the In component has a duty ratio less than 0.3, the light emitting efficiency of the diode is low; if the In component is more than 0.65, in clusters are caused. Preferably, the In composition In InN layer 512 has a ratio of 0.4 to 0.6, and exemplary is 0.42, 0.44, 0.46, 0.48, 0.5, 0.52, 0.54, 0.56, or 0.58, but is not limited thereto.
Specifically, the thickness of the InN layer 512 is 0.3nm-2.5nm, if the thickness is less than 0.3nm, the luminous efficiency of the diode is low; if the thickness is > 2.5nm, the lattice quality is deteriorated. Preferably, the InN layer 512 has a thickness of 0.5nm to 2nm, and exemplary, but not limited to, 0.8nm, 1nm, 1.2nm, 1.4nm, 1.6nm, or 1.8 nm.
Preferably, in one embodiment of the present invention, H is employed for InN layer 512 2 Atmosphere treatment with small amounts of H 2 The InN layer 512 surface is treated, in clusters are opened, in components with poor growth lattice quality and low bond energy are desorbed, in segregation In the potential well layer 51 is further reduced, and the uniformity of the light emitting wavelength is improved.
Specifically, H 2 The treatment time is 1s-5s, the treatment temperature is 900-1000 ℃, H 2 The inlet amount is 4slm-6slm. If the treatment time is less than 1s, the In segregation cannot be effectively reduced; if the processing time is > 5s, in loss is caused. Exemplary, H 2 The processing time is 2s, 3s or 4s, but is not limited thereto. If H 2 The In cluster cannot be opened when the inlet amount is less than 4 slm; if H 2 The amount of the introduced material is more than 6slm, which causes In loss. Exemplary, H 2 The amount of the gas introduced is 4.5slm, 5slm or 5.5slm, but is not limited thereto. The temperature of the treatment is exemplified by, but not limited to, 930 ℃, 950 ℃, or 980 ℃.
Wherein the InGaN layer 513 is grown on the InN layer 512, on the one hand, the compensation of the In composition is realized, and on the other hand, the InGaN material is more stable than the InN material, and the diffusion of the In composition to the barrier layer 52 is not easy to occur at a position close to the barrier layer 52.
Specifically, the In component In the InGaN layer 513 has a ratio of 0.05 to 0.45, and if the In component has a ratio of less than 0.05, the In compensation effect cannot be achieved; if the In component is more than 0.45, the lattice quality is lowered. Preferably, the In composition of the InGaN layer 513 has a duty ratio of 0.1 to 0.4, and exemplary is 0.15, 0.2, 0.25, 0.3, or 0.35, but is not limited thereto.
Specifically, the thickness of the InGaN layer 513 is 0.3nm to 2.5nm, and if the thickness is less than 0.3nm, the In compensation effect cannot be achieved; if the thickness is > 2.5nm, the lattice quality is reduced. Preferably, the thickness of the InGaN layer 513 is 0.5nm to 2nm, and exemplary is 0.8nm, 1nm, 1.2nm, 1.5nm, or 1.8nm, but is not limited thereto.
The barrier layer 52 is a GaN layer, but is not limited thereto. The thickness of the single barrier layer 52 is 6nm to 15nm, and is exemplified by 8nm, 10nm, 12nm, or 14nm, but is not limited thereto.
Among them, the substrate 1 may be a sapphire substrate, a silicon carbide substrate, but is not limited thereto.
The nucleation layer 2 may be an AlN layer and/or an AlGaN layer, but is not limited thereto. The thickness of the nucleation layer 2 is 20nm to 100nm, and is exemplified by 30nm, 40nm, 50nm, 60nm, 70nm, 80nm or 90nm, but not limited thereto.
Among them, the intrinsic GaN layer 3 has a thickness of 300nm to 800nm, and exemplary are 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, or 750nm, but not limited thereto.
Wherein the doping element of the N-GaN layer 4 is Si, but is not limited thereto. The doping concentration of the N-GaN layer 4 was 5×10 18 cm -3 -1×10 19 cm -3 The thickness is 1 μm-3 μm.
The electron blocking layer 6 is an AlGaN layer with a high Al composition (Al composition ratio is 0.4 to 0.6) or an AlInGaN layer, but is not limited thereto. The thickness of the electron blocking layer 6 is 20nm to 100nm, and is exemplified by 25nm, 40nm, 55nm, 60nm, 75nm, 90nm, or 95nm, but not limited thereto.
Preferably, referring to FIG. 3, in one embodiment of the present invention the electron blocking layer 6 is Al a Ga 1-a N layer 61 (a=0.05-0.2) and In b Ga 1-b A periodic structure in which N layers 62 (b=0.1 to 0.5) are alternately grown, the number of periods being 3 to 15; wherein, single Al a Ga 1-a N layer 61 has a thickness of 2nm to 8nm, a single In b Ga 1-b The thickness of the N layer 62 is 2nm-8nm.
Wherein the doping element in the P-GaN layer 7 is Mg, but is not limited thereto. The doping concentration of Mg in the P-GaN layer 7 was 5×10 17 cm -3 -1×10 20 cm -3 . The thickness of the P-GaN layer 7 is 200nm-300nm.
Correspondingly, referring to fig. 4, the invention also discloses a preparation method of the epitaxial wafer for the Micro-LED, which is used for preparing the epitaxial wafer for the Micro-LED, and comprises the following steps:
s100: providing a substrate;
specifically, the substrate is a sapphire substrate, a silicon carbide substrate, but is not limited thereto. A sapphire substrate is preferred.
Preferably, in one embodiment of the present invention, the substrate is loaded into MOCVD and annealed at 1000-1200 deg.C, 200-600 torr, hydrogen atmosphere for 5-8 min to remove impurities such as particles, oxides, etc. on the substrate surface.
S200: growing a nucleation layer on the substrate;
specifically, the MOCVD grown AlGaN layer may be used as the nucleation layer, or the PVD grown AlN layer may be used as the nucleation layer, but is not limited thereto. Preferably, the AlGaN layer is grown by MOCVD, the growth temperature is 500-700 ℃, and the growth pressure is 200-400 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As an N source; by H 2 And N 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas.
S300: growing an intrinsic GaN layer on the nucleation layer;
specifically, the intrinsic GaN layer is grown in MOCVD at 1100-1150 deg.c and 100-500 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As an N source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
S400: growing an N-GaN layer on the intrinsic GaN layer;
specifically, an N-GaN layer is grown in MOCVD at 1100-1150 deg.C under 100-500 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, siH is introduced 4 As an N-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
S500: growing a multi-quantum well layer on the N-GaN layer;
specifically, a potential well layer and a barrier layer are periodically grown in MOCVD to form a multiple quantum well layer. Wherein the growth temperature of the barrier layer is 800-900 ℃ and the growth pressure is highThe force is 100-500torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As a carrier gas, TEGa was introduced as a Ga source.
Specifically, in one embodiment of the present invention, growing the potential well layer includes the steps of:
s510: growing an AlInN layer on the N-GaN layer;
specifically, in one embodiment of the present invention, an AlInN layer is grown in MOCVD. Specifically, by N 2 Or Ar as carrier gas (not containing H 2 ) TMIn is used as an In source, TMAL is used as an Al source, and NH is used 3 As an N source, the growth temperature is 700-800 ℃ and the growth pressure is 100-500 torr. Preferably, in N 2 As a carrier gas.
S520: by H 2 Etching the AlInN layer;
specifically, after AlInN layer growth is completed, H is adopted 2 Etching treatment is carried out to form a plurality of nano holes on the surface of the AlInN layer. Specifically, all MO sources are turned off and only H is introduced 2 Or H 2 、N 2 Is a mixed gas of (a) and (b). Specifically, N is adopted 2 And H 2 The mixed gas is used as carrier gas, H 2 And N 2 Molar ratio > 2, preferably (2-10): 1.h 2 Etching treatment time is 10s-30s, treatment temperature is 900-1000 ℃, H 2 The inlet amount is 40slm-60slm.
S530: growing an InN layer on the AlInN layer;
specifically, in one embodiment of the present invention, the InN layer is grown in MOCVD. Specifically, by N 2 Or Ar as carrier gas (not containing H 2 ) TMIn is used as an In source, and NH is used 3 As an N source, the growth temperature is 700-800 ℃ and the growth pressure is 100-500 torr. Preferably, in N 2 As a carrier gas.
S540: by H 2 Etching the InN layer;
specifically, in one embodiment of the present invention, H is employed 2 And etching the InN layer. Specifically, all MO sources are turned off and only H is introduced 2 Or H 2 、N 2 Is a mixed gas of (a) and (b). Specifically, N is adopted 2 And H 2 The mixed gas is used as carrier gas, H 2 And N 2 Molar ratio > 2, preferably (2-10): 1.h 2 Etching treatment time is 1s-5s, treatment temperature is 900-1000 ℃, H 2 The inlet amount is 4slm-6slm.
S550: growing an InGaN layer on the InN layer;
specifically, an InGaN layer is grown in MOCVD. The growth temperature is 700-800 deg.c and the growth pressure is 100-500 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source.
S600: growing an electron blocking layer on the multiple quantum well layer;
specifically, periodically growing Al in MOCVD a Ga 1-a N layer and In b Ga 1-b And an N layer serving as an electron blocking layer. Wherein Al is a Ga 1-a The growth temperature of the N layer is 900-1000 ℃, and the growth pressure is 100-500 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 And H 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas. In (In) b Ga 1-b The growth temperature of the N layer is 900-1000 ℃, and the growth pressure is 100-500 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 And H 2 As a carrier gas, TMIn was introduced as an In source, and TMGa was introduced as a Ga source.
S700: growing a P-GaN layer on the electron blocking layer;
specifically, the P-GaN layer is grown in MOCVD at 800-1000 deg.C and 100-300 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, cp is introduced 2 Mg is used as a P-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
The invention is further illustrated by the following examples:
example 1
The present embodiment provides an epitaxial wafer for Micro-LEDs, referring to fig. 1 to 3, which includes a substrate 1 and a nucleation layer 2, an intrinsic GaN layer 3, an N-GaN layer 4, a multiple quantum well layer 5, an electron blocking layer 6, and a P-GaN layer 7 sequentially provided on the substrate 1.
Wherein the substrate 1 is a sapphire substrate; the nucleation layer 2 is an AlGaN layer, and the thickness of the AlGaN layer is 30nm; the thickness of the intrinsic GaN layer 3 is 400nm; the doping concentration of Si in the N-GaN layer 4 was 7×10 18 cm -3 The thickness thereof was 2. Mu.m.
Wherein the multiple quantum well layer 5 has a periodic structure with a period number of 10, and each period includes a potential well layer 51 and a barrier layer 52.
The well layer 51 includes an AlInN layer 511, an InN layer 512, and an InGaN layer 513, which are sequentially stacked. Wherein the Al component of the AlInN layer 511 has a ratio of 0.14, the in component has a ratio of 0.4, and the AlInN layer 511 has a thickness of 3nm. Wherein the AlInN layer 511 has a plurality of H-channels on its surface 2 Nano holes obtained by etching treatment, H 2 Etching treatment time is 20s, treatment temperature is 950 ℃, H 2 The amount of the gas introduced was 50slm. The In composition of the InN layer 512 had a duty ratio of 0.5, and the InN layer 512 had a thickness of 1nm. The In composition of the InGaN layer 513 was 0.25, and the thickness of the InGaN layer 513 was 1nm.
Wherein the barrier layer 52 is a GaN layer, and the thickness of the single barrier layer 52 is 10nm.
Wherein the electron blocking layer 6 is Al a Ga 1-a N layers (a=0.12) and In b Ga 1-b Periodic structure with N layers (b=0.3) alternately grown, with a period of 8, single Al a Ga 1-a The thickness of the N layer is 6nm, single In b Ga 1-b The thickness of the N layer was 6nm. The doping element of the P-GaN layer 7 is Mg, and the doping concentration is 3.5X10 19 cm -3 The thickness was 250nm.
The preparation method of the epitaxial wafer for the Micro-LED in the embodiment comprises the following steps:
(1) Providing a substrate; the substrate was loaded into MOCVD and annealed at 1120℃under a 400torr atmosphere of hydrogen for 6min.
(2) Growing a nucleation layer on the substrate;
specifically, MOCVD is adopted to grow the AlGaN layer, the growth temperature is 620 ℃, and the growth pressure is 250torr. Raw materialsIntroducing NH into MOCVD reaction chamber for a long time 3 As an N source; by H 2 And N 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas.
(3) Growing an intrinsic GaN layer on the nucleation layer;
specifically, MOCVD is adopted to grow an intrinsic GaN layer, the growth temperature is 1100 ℃, the growth pressure is 250torr, and NH is introduced into an MOCVD reaction chamber during growth 3 As an N source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
(4) Growing an N-GaN layer on the intrinsic GaN layer;
specifically, MOCVD is adopted to grow an N-GaN layer, the growth temperature is 1120 ℃, and the growth pressure is 150torr; during growth, NH is introduced into the MOCVD reaction chamber 3 As N source, siH is introduced 4 As an N-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
(5) Growing a multi-quantum well layer on the N-GaN layer;
specifically, a potential well layer and a barrier layer are periodically grown in MOCVD to form a multiple quantum well layer. Wherein the growth temperature of the barrier layer is 850 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As a carrier gas, TEGa was introduced as a Ga source.
Specifically, the growing the potential well layer includes the steps of:
growing an AlInN layer on the N-GaN layer;
specifically, an AlInN layer is grown in MOCVD. By N 2 As a carrier gas, TMIn as an In source, TMAL as an Al source, and NH 3 As an N source, the growth temperature was 750℃and the growth pressure was 300torr.
(II) use of H 2 Etching the AlInN layer;
specifically, after AlInN layer growth is completed, H is adopted 2 Etching treatment is carried out to form a plurality of nano holes on the surface of the AlInN layer. Specifically, all MO sources are turned off, N is adopted 2 And H 2 The mixed gas is used as carrier gas, H 2 And N 2 Molar ratio of (2)10：1。H 2 Etching treatment time is 20s, treatment temperature is 950 ℃, H 2 The amount of the gas introduced was 30slm.
(iii) growing an InN layer on the AlInN layer;
specifically, in MOCVD, an InN layer is periodically grown. Specifically, by N 2 As carrier gas (not containing H 2 ) TMIn is used as an In source, and NH is used 3 As an N source, the growth temperature was 750℃and the growth pressure was 300torr.
(iv) growing an InGaN layer on the InN layer;
specifically, an InGaN layer is grown in MOCVD. The growth temperature was 750℃and the growth pressure was 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source.
(6) Growing an electron blocking layer on the multiple quantum well layer;
specifically, periodically growing Al in MOCVD a Ga 1-a N layer and In b Ga 1-b And an N layer serving as an electron blocking layer. Wherein Al is a Ga 1-a The growth temperature of the N layer is 950 ℃ and the growth pressure is 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 And H 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas. In (In) b Ga 1-b The growth temperature of the N layer is 950 ℃ and the growth pressure is 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 And H 2 As a carrier gas, TMIn was introduced as an In source, and TMGa was introduced as a Ga source.
(7) Growing a P-GaN layer on the electron blocking layer;
specifically, the P-GaN layer is grown in MOCVD at 900 ℃ under a growth pressure of 200torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, cp is introduced 2 Mg is used as a P-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
Example 2
The present embodiment provides an epitaxial wafer for Micro-LEDs, referring to fig. 1 to 3, which includes a substrate 1 and a nucleation layer 2, an intrinsic GaN layer 3, an N-GaN layer 4, a multiple quantum well layer 5, an electron blocking layer 6, and a P-GaN layer 7 sequentially provided on the substrate 1.
Wherein the substrate 1 is a sapphire substrate; the nucleation layer 2 is an AlGaN layer, and the thickness of the AlGaN layer is 30nm; the thickness of the intrinsic GaN layer 3 is 400nm; the doping concentration of Si in the N-GaN layer 4 was 7×10 18 cm -3 The thickness thereof was 2. Mu.m.
Wherein the multiple quantum well layer 5 has a periodic structure with a period number of 10, and each period includes a potential well layer 51 and a barrier layer 52.
The well layer 51 includes an AlInN layer 511, an InN layer 512, and an InGaN layer 513, which are sequentially stacked. Wherein the Al component of the AlInN layer 511 has a ratio of 0.14, the in component has a ratio of 0.4, and the AlInN layer 511 has a thickness of 3nm. Wherein the AlInN layer 511 has a plurality of H-channels on its surface 2 Nano holes obtained by etching treatment, H 2 Etching treatment time is 20s, treatment temperature is 950 ℃, H 2 The amount of the gas introduced was 50slm. The In composition of the InN layer 512 had a duty ratio of 0.5, and the InN layer 512 had a thickness of 1nm. Employing H for InN layer 512 2 Atmosphere treatment, H 2 The treatment time is 3s, the treatment temperature is 950 ℃, H 2 The amount of the gas introduced was 5slm. The In composition of the InGaN layer 513 was 0.25, and the thickness of the InGaN layer 513 was 1nm.
Wherein the barrier layer 52 is a GaN layer, and the thickness of the single barrier layer 52 is 10nm.
Wherein the electron blocking layer 6 is Al a Ga 1-a N layers (a=0.12) and In b Ga 1-b Periodic structure with N layers (b=0.3) alternately grown, with a period of 8, single Al a Ga 1-a The thickness of the N layer is 6nm, single In b Ga 1-b The thickness of the N layer was 6nm. The doping element of the P-GaN layer 7 is Mg, and the doping concentration is 3.5X10 19 cm -3 The thickness was 250nm.
The preparation method of the epitaxial wafer for the Micro-LED in the embodiment comprises the following steps:
(1) Providing a substrate; the substrate was loaded into MOCVD and annealed at 1120℃under a 400torr atmosphere of hydrogen for 6min.
(2) Growing a nucleation layer on the substrate;
specifically, MOCVD is adopted to grow the AlGaN layer, the growth temperature is 620 ℃, and the growth pressure is 250torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As an N source; by H 2 And N 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas.
(3) Growing an intrinsic GaN layer on the nucleation layer;
specifically, MOCVD is adopted to grow an intrinsic GaN layer, the growth temperature is 1100 ℃, the growth pressure is 250torr, and NH is introduced into an MOCVD reaction chamber during growth 3 As an N source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
(4) Growing an N-GaN layer on the intrinsic GaN layer;
specifically, MOCVD is adopted to grow an N-GaN layer, the growth temperature is 1120 ℃, and the growth pressure is 150torr; during growth, NH is introduced into the MOCVD reaction chamber 3 As N source, siH is introduced 4 As an N-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
(5) Growing a multi-quantum well layer on the N-GaN layer;
specifically, a potential well layer and a barrier layer are periodically grown in MOCVD to form a multiple quantum well layer. Wherein the growth temperature of the barrier layer is 850 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As a carrier gas, TEGa was introduced as a Ga source.
Specifically, the growing the potential well layer includes the steps of:
growing an AlInN layer on the N-GaN layer;
specifically, an AlInN layer is grown in MOCVD. By N 2 As a carrier gas, TMIn as an In source, TMAL as an Al source, and NH 3 As an N source, the growth temperature was 750℃and the growth pressure was 300torr.
(II) use of H 2 Etching the AlInN layer;
specifically, after AlInN layer growth is completed, H is adopted 2 Etching to form multiple nanometer holes on AlInN layer surfaceA hole. Specifically, all MO sources are turned off, N is adopted 2 And H 2 The mixed gas is used as carrier gas, H 2 And N 2 The mol ratio of (2) is 10:1.h 2 Etching treatment time is 20s, treatment temperature is 950 ℃, H 2 The amount of the gas introduced was 30slm.
(iii) growing an InN layer on the AlInN layer;
specifically, in MOCVD, an InN layer is periodically grown. Specifically, by N 2 As carrier gas (not containing H 2 ) TMIn is used as an In source, and NH is used 3 As an N source, the growth temperature was 750℃and the growth pressure was 300torr.
(IV) use of H 2 Etching the InN layer;
specifically, H is adopted 2 And etching the InN layer. Specifically, all MO sources are turned off, N is adopted 2 And H 2 The mixed gas is used as carrier gas, H 2 And N 2 The molar ratio of (2) is 10:1.h 2 Etching treatment time is 3s, treatment temperature is 950 ℃, H 2 The amount of the gas introduced was 5slm.
(V) growing an InGaN layer on the InN layer obtained in the step (IV);
specifically, an InGaN layer is grown in MOCVD. The growth temperature was 750℃and the growth pressure was 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source.
(6) Growing an electron blocking layer on the multiple quantum well layer;
specifically, periodically growing Al in MOCVD a Ga 1-a N layer and In b Ga 1-b And an N layer serving as an electron blocking layer. Wherein Al is a Ga 1-a The growth temperature of the N layer is 950 ℃ and the growth pressure is 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 And H 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas. In (In) b Ga 1-b The growth temperature of the N layer is 950 ℃ and the growth pressure is 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 And H 2 As a carrier gas, TMIn was introduced as an In source, and TMGa was introduced as a Ga source.
(7) Growing a P-GaN layer on the electron blocking layer;
specifically, the P-GaN layer is grown in MOCVD at 900 ℃ under a growth pressure of 200torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, cp is introduced 2 Mg is used as a P-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
Comparative example 1
This comparative example provides an epitaxial wafer for Micro-LEDs, which is different from embodiment 1 in that AlInN layer 511 and InN layer 512 are not included in potential well layer 51. Accordingly, the preparation steps of the above two layers were not provided in the preparation method, and the rest was the same as in example 1.
Comparative example 2
This comparative example provides an epitaxial wafer for Micro-LEDs, which is different from example 1 in that AlInN layer 511 is not included in potential well layer 51, and accordingly, in the manufacturing method, the manufacturing step of this layer is not provided, and the rest is the same as example 1.
Comparative example 3
This comparative example provides an epitaxial wafer for Micro-LEDs, which is different from embodiment 1 in that InN layer 512 is not included in potential well layer 51, and alinn layer 511 is not provided with nanoholes. Accordingly, in the manufacturing method, the manufacturing step of the InN layer 512 is not provided, and the AlInN layer 511 is not etched, and the rest is the same as in example 1.
Comparative example 4
This comparative example provides an epitaxial wafer for Micro-LEDs, which differs from example 1 in that InN layer 512 is not included in potential well layer 51, and accordingly, in the manufacturing method, the manufacturing step of this layer is not provided, and the remainder is the same as example 1.
The epitaxial wafers for Micro-LEDs obtained in examples 1-2 and comparative examples 1-4 were tested as follows:
(1) Preparing epitaxial wafer into chip with vertical structure of 5mil×7mil, and testing the luminescence brightness;
(2) The prepared epitaxial wafer adopts an IM-1130 type PL spectrometer to measure the luminous wavelength and luminous uniformity;
(3) The epitaxial wafer is subjected to an electrofluorescence test (specific reference Li Yangfeng. GaN-based yellow-green LED epitaxial growth and carrier transport characteristic research [ D ] in a multiple quantum well, university of Chinese academy of sciences (institute of physics), 2017.) and test currents of 1mA and 5mA respectively, so that wavelengths under different test currents are obtained, and wavelength offset is calculated according to the following formula:
wavelength shift = test wavelength 1 (1 mA) -test wavelength 2 (5 mA).
The specific results are as follows:
as can be seen from the table, after the conventional potential well layer (comparative example 1) was changed into the potential well layer in the present invention, the luminance was improved from 24mcd to 29mcd, the uniformity of the light emission wavelength was improved from 1.32nm to 1.02nm, and the wavelength shift was reduced from 8.5nm to 4.3nm, indicating that the potential well layer in the present invention can effectively improve the luminance, the uniformity of the light emission wavelength, and the uniformity of the wavelength. Further, as can be seen from a comparison of example 1 with comparative examples 2 to 4, when the potential well layer structure in the present invention is changed, it is difficult to effectively exert the effects of improving the luminance, improving the uniformity of the emission wavelength, and improving the wavelength uniformity.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.
Claims (10)
1. The epitaxial wafer for the Micro-LED comprises a substrate, and a nucleation layer, an intrinsic GaN layer, an N-GaN layer, a multiple quantum well layer, an electron blocking layer and a P-GaN layer which are sequentially arranged on the substrate, wherein the multiple quantum well layer is of a periodic structure, each period comprises a potential well layer and a potential barrier layer, and the epitaxial wafer is characterized in that the potential well layer comprises an AlInN layer, an InN layer and an InGaN layer which are sequentially laminated;
wherein the AlInN layer surface is provided with a plurality of H-channels 2 And etching to obtain the nano holes.
2. The epitaxial wafer for Micro-LED according to claim 1, wherein the Al component in the AlInN layer has a ratio of 0.1 to 0.2, the in component has a ratio of 0.3 to 0.5, and the AlInN layer has a thickness of 2nm to 5nm;
the ratio of an In component In the InN layer is 0.4-0.6, and the thickness of the InN layer is 0.5-2 nm;
the proportion of In components In the InGaN layer is 0.1-0.4, and the thickness of the InGaN layer is 0.5-2 nm.
3. The epitaxial wafer for Micro-LEDs according to claim 1, wherein H 2 Etching treatment time is 10s-30s, treatment temperature is 900-1000 ℃, H 2 The inlet amount is 40slm-60slm.
4. The epitaxial wafer for Micro-LEDs according to any one of claims 1 to 3, wherein H is used for the InN layer 2 Atmosphere treatment, wherein the treatment time is 1s-5s, the treatment temperature is 900-1000 ℃, H 2 The inlet amount is 4slm-6slm.
5. The epitaxial wafer for Micro-LEDs according to claim 1, wherein the electron blocking layer has a periodic structure with a period of 3 to 15, each period comprising Al laminated in sequence a Ga 1-a N layer and In b Ga 1-b An N layer, wherein a is 0.05-0.2, and b is 0.1-0.5;
single Al a Ga 1-a The thickness of the N layer is 2nm-8nm, and single In b Ga 1-b The thickness of the N layer is 2nm-8nm.
6. A method for producing an epitaxial wafer for Micro-LEDs, which is used for producing the epitaxial wafer for Micro-LEDs according to any one of claims 1 to 5, characterized by comprising:
providing a substrate, and sequentially growing a nucleation layer, an intrinsic GaN layer, an N-GaN layer, a multiple quantum well layer, an electron blocking layer and a P-GaN layer on the substrate, wherein the multiple quantum well layer is of a periodic structure, each period comprises a potential well layer and a barrier layer, and the potential well layer comprises an AlInN layer, an InN layer and an InGaN layer which are sequentially laminated;
wherein, after the AlInN layer is grown, H is adopted 2 And etching to form a plurality of nano holes on the surface of the AlInN layer.
7. The method of manufacturing an epitaxial wafer for Micro-LEDs according to claim 6, wherein the AlInN layer is grown at a temperature of 700-800 ℃ and a growth pressure of 100-500torr, and the carrier gas used for the growth is N 2 ；
The growth temperature of the InN layer is 700-800 ℃, the growth pressure is 100-500torr, and the carrier gas adopted in the growth is N 2 ；
The growth temperature of the InGaN layer is 700-800 ℃, the growth pressure is 100-500torr, and the carrier gas adopted in the growth is N 2 。
8. The method for producing an epitaxial wafer for Micro-LEDs according to claim 6 or 7, wherein H is used for the InN layer 2 Etching treatment is carried out;
H 2 the carrier gas adopted in the etching treatment is H 2 The method comprises the steps of carrying out a first treatment on the surface of the Or (b)
H 2 The carrier gas adopted in the etching treatment is H 2 And N 2 ，H 2 And N 2 The molar ratio of (2) to (1) to (10) to (1).
9. The method for manufacturing an epitaxial wafer for Micro-LEDs according to claim 6, wherein the electron blocking layer comprises Al a Ga 1-a N layer and In b Ga 1-b An N layer;
the Al is a Ga 1-a The growth temperature of the N layer is 900-1000 ℃ and the growth pressure is 100-500 torr;
the In is b Ga 1-b The growth temperature of the N layer is 900-1000 ℃ and the growth pressure is 100-500 torr.
10. A Micro-LED comprising an epitaxial wafer for a Micro-LED according to any one of claims 1 to 5.
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