CN116169216A - Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode - Google Patents

Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode Download PDF

Info

Publication number
CN116169216A
CN116169216A CN202310232249.4A CN202310232249A CN116169216A CN 116169216 A CN116169216 A CN 116169216A CN 202310232249 A CN202310232249 A CN 202310232249A CN 116169216 A CN116169216 A CN 116169216A
Authority
CN
China
Prior art keywords
layer
source
sub
emitting diode
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310232249.4A
Other languages
Chinese (zh)
Inventor
张彩霞
印从飞
程金连
刘春杨
胡加辉
金从龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangxi Zhao Chi Semiconductor Co Ltd
Original Assignee
Jiangxi Zhao Chi Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangxi Zhao Chi Semiconductor Co Ltd filed Critical Jiangxi Zhao Chi Semiconductor Co Ltd
Priority to CN202310232249.4A priority Critical patent/CN116169216A/en
Publication of CN116169216A publication Critical patent/CN116169216A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/0641—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/18—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Led Devices (AREA)

Abstract

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, and relates to the field of semiconductor photoelectric devices. The light-emitting diode epitaxial wafer comprises a substrate, and a nucleation layer, an intrinsic GaN layer and an N-type semiconductor which are sequentially arranged on the substrateThe semiconductor device comprises a body layer, a multiple quantum well layer, an electron blocking layer and a P-type semiconductor layer; the electron blocking layer comprises a first sub-layer and a second sub-layer which are sequentially laminated; wherein the first sub-layer is an MgInGaN layer; the second sub-layer comprises Ga laminated in sequence 2 O 3 A layer and a MgGaN layer. By implementing the invention, the luminous efficiency of the light-emitting diode can be improved, and the working voltage can be reduced.

Description

Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
Technical Field
The invention relates to the field of semiconductor photoelectric devices, in particular to a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode.
Background
Currently, gaN-based light emitting diodes have been widely used in the field of solid state lighting as well as in the field of display, attracting more and more attention. The epitaxial structure has a great influence on the photoelectric performance of the light emitting diode. The conventional light emitting diode epitaxial wafer includes: the semiconductor device comprises a substrate, and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer and a P-type semiconductor layer which are sequentially grown on the substrate. Because the electron mobility is high, the AlGaN material or AlGaN/InGaN superlattice material doped with high Al is adopted as the electron blocking layer at the present stage, but the high Al component can bring high working voltage and has a certain negative effect of blocking holes, and the phenomenon of electron overflow is caused due to the fact that the mobility of Al atoms is low, the viscous effect is high, the distribution of Al atoms is uneven, the electron blocking is influenced, and the luminous efficiency is reduced.
Disclosure of Invention
The invention aims to solve the technical problem of providing a light-emitting diode epitaxial wafer and a preparation method thereof, which can reduce the working voltage of a light-emitting diode and improve the light-emitting efficiency.
The invention also solves the technical problem of providing a light-emitting diode which has high luminous efficiency and low working voltage.
In order to solve the problems, the invention discloses a light-emitting diode epitaxial wafer which comprises a substrate, a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer and a P-type semiconductor layer, wherein the nucleation layer, the intrinsic GaN layer, the N-type semiconductor layer, the multiple quantum well layer, the electron blocking layer and the P-type semiconductor layer are sequentially arranged on the substrate; the electron blocking layer comprises a first sub-layer and a second sub-layer which are sequentially laminated;
wherein the first sub-layer is an MgInGaN layer;
the second sub-layer comprises Ga laminated in sequence 2 O 3 A layer and a MgGaN layer.
As an improvement of the above technical solution, the In component In the MgInGaN layer gradually decreases from 0.2 to 0.4 to 0 along the epitaxial direction.
As an improvement of the technical proposal, the doping concentration of Mg in the MgInGaN layer is 1 multiplied by 10 15 cm -3 -1×10 16 cm -3 The thickness of the MgInGaN layer is 5nm-50nm.
As an improvement of the technical scheme, the In source In the MgInGaN layer is intermittently introduced, wherein the interruption time is 1s-5s, and the introduction time is 5s-10s;
the Ga source In the MgInGaN layer is intermittently introduced, and when the In source is interrupted, the Ga source is introduced, and the Ga source introduction time is the same as the In source interruption time; when the In source is turned on, the Ga source is interrupted, and the Ga source interruption time is the same as the In source on time.
As an improvement of the above technical scheme, the Ga 2 O 3 The thickness of the layer is 15nm-200nm;
the MgGaN layer has a thickness of 3nm-50nm and a doping concentration of 1×10 Mg 17 cm -3 -1×10 18 cm -3 。
As an improvement of the technical scheme, the second sub-layer is of a periodic structure, and the period number is 3-10;
wherein, the Ga is singly 2 O 3 The thickness of the layer is 5nm-20nm;
the thickness of the MgGaN layer is 1nm-5nm.
Correspondingly, the invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps:
providing a substrate, and sequentially growing a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer and a P-type semiconductor layer on the substrate; the electron blocking layer comprises a first sub-layer and a second sub-layer which are sequentially laminated;
wherein the first sub-layer is an MgInGaN layer;
the second sub-layer comprises Ga laminated in sequence 2 O 3 A layer and a MgGaN layer.
As an improvement of the technical scheme, the growth temperature of the first sub-layer is gradually increased from 750 ℃ to 800 ℃ to 850 ℃ to 900 ℃ and the growth pressure is 100torr to 300torr;
the growth temperature of the second sub-layer is 950-1000 ℃, and the growth pressure is 100-300 torr.
As an improvement of the technical proposal, the carrier gas adopted in the growth of the first sub-layer and the second sub-layer is N 2 。
Correspondingly, the invention also discloses a light-emitting diode, which comprises the light-emitting diode epitaxial wafer.
The implementation of the invention has the following beneficial effects:
1. in the light-emitting diode epitaxial wafer, the electron blocking layer comprises a first sub-layer and a second sub-layer which are sequentially stacked, wherein the first sub-layer is an MgInGaN layer. Firstly, partial holes can be generated by Mg doping in the MgInGaN layer, partial electrons are consumed, electron overflow is reduced, electron hole pairs are increased, and luminous efficiency is improved; and secondly, the first sub-layer is connected with the multi-quantum well layer, and the material similar to the multi-quantum well layer is adopted, so that lattice mismatch with the multi-quantum well layer can be reduced, the lattice quality is improved, energy band peaks caused by overlarge energy band change between the traditional electron blocking layer and the multi-quantum well layer are reduced, hole injection is prevented from being influenced, and the luminous efficiency is improved.
Wherein the second sub-layer comprises Ga sequentially laminated 2 O 3 A layer and a MgGaN layer. First, ga 2 O 3 The material has large forbidden bandwidth, good electron blocking effect and low on-resistance, so compared with the traditional method of adopting high Al doped AlGaN material or AlGaN/InGaN material as an electron blocking layer, ga 2 O 3 Not only can block the electron from entering, but also can not cause workersRaising the voltage; secondly, the MgGaN layer can increase the hole concentration, so that the hole concentration entering the multi-quantum well layer is increased, and the luminous efficiency is improved; finally, the carrier is Ga 2 O 3 The mobility of the material is higher, and holes generated by the MgGaN layer pass through Ga 2 O 3 The layer enters the multi-quantum well layer, so that the injection of holes of the multi-quantum well layer is further increased, and the luminous efficiency is improved.
2. In the light-emitting diode epitaxial wafer, the proportion of the In component In the MgInGaN layer is gradually reduced from 0.2 to 0.4 to 0 along the epitaxial growth direction, so that the energy level between the electron blocking layer and the multiple quantum well layer and between the electron blocking layer and the P-type semiconductor layer is In smooth transition, the injection of holes In the multiple quantum well layer is increased, and the light-emitting efficiency is improved.
3. In the light-emitting diode epitaxial wafer, an In source and a Ga source In the MgInGaN layer are intermittently introduced, and when the In source is interrupted, the Ga source is introduced; when the In source is turned on, the Ga source is interrupted. The growth method that the In source and the Ga source are intermittently introduced and the N source is continuously supplied without interruption is beneficial to eliminating defects such as In clusters, in drops and the like formed on the surface of the material, improving the lattice quality, avoiding the defects from becoming non-radiative recombination centers and improving the luminous efficiency.
4. In the light-emitting diode epitaxial wafer, the second sub-layer is of a periodic structure. The periodic lamination can generate a stronger built-in electric field, so that the acceptor energy level can be reduced, two-dimensional hole gas is generated, the mobility of holes is increased, the concentration of holes entering the multi-quantum well layer is increased, and the luminous efficiency is improved.
Drawings
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an electron blocking layer according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a first sub-layer according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a second sub-layer according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a second sub-layer according to another embodiment of the present invention;
fig. 6 is a flowchart of a method for manufacturing an led epitaxial wafer according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below in order to make the objects, technical solutions and advantages of the present invention more apparent.
Referring to fig. 1 to 4, the invention discloses a light emitting diode epitaxial wafer, which comprises a substrate 1, a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, a multiple quantum well layer 5, an electron blocking layer 6 and a P-type semiconductor layer 7 which are sequentially arranged on the substrate 1; wherein the electron blocking layer 6 comprises a first sub-layer 61 and a second sub-layer 62, which are laminated in sequence. Wherein the first sub-layer 61 is a MgInGaN layer 611. Firstly, the Mg doping in the MgInGaN layer 611 can generate partial holes, consume partial electrons, reduce electron overflow, increase electron hole pairs and improve luminous efficiency; and secondly, the first sub-layer 61 is connected with the multiple quantum well layer 5, and the material similar to the multiple quantum well layer 5 is adopted, so that lattice mismatch with the multiple quantum well layer 5 can be reduced, the lattice quality is improved, energy band peaks caused by overlarge energy band change between the traditional electron blocking layer and the multiple quantum well layer are reduced, hole injection is avoided, and the luminous efficiency is improved.
Preferably, in one embodiment of the present invention, the ratio of In component In MgInGaN layer 611 gradually decreases from 0.2 to 0.4 to 0 along the epitaxial growth direction, so that the energy level between electron blocking layer 6 and multiple quantum well layer 5 and P-type semiconductor layer 7 is smoothly transited, the injection of holes In multiple quantum well layer 5 is increased, and the light emitting efficiency is improved.
Wherein the doping concentration of Mg in the MgInGaN layer 611 is 5×10 14 cm -3 -5×10 16 cm -3 When the doping concentration is less than 5×10 14 cm -3 It is difficult to provide sufficient holes; when the doping concentration is more than 5 multiplied by 10 16 cm -3 Excessive drawbacks can be brought about. Preferably, the Mg doping concentration in MgInGaN layer 611 is 1×10 15 cm -3 -1×10 16 cm -3 Exemplary is 2X 10 15 cm -3 、3×10 15 cm -3 、4×10 15 cm -3 、5×10 15 cm -3 、6×10 15 cm -3 、7×10 15 cm -3 、8×10 15 cm -3 Or 9X 10 15 cm -3 But is not limited thereto.
The MgInGaN layer 611 has a thickness of 3nm to 60nm, and when its thickness is < 3nm, it is difficult to provide sufficient holes; when the thickness is more than 60nm, excessive defects are brought. Preferably, the MgInGaN layer 611 has a thickness of 5nm-50nm, and exemplary is 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, or 45nm, but is not limited thereto.
Preferably, in another embodiment of the present invention, the In source In the MgInGaN layer 611 is intermittently introduced, wherein the interruption time is 1s-5s and the introduction time is 5s-10s; the Ga source In the MgInGaN layer is intermittently introduced, and when the In source is interrupted, the Ga source is introduced, and the Ga source introduction time is the same as the In source interruption time; when the In source is turned on, the Ga source is interrupted, and the Ga source interruption time is the same as the In source on time. The growth method that the In source and the Ga source are intermittently introduced and the N source is continuously supplied without interruption is beneficial to eliminating defects such as In clusters, in drops and the like formed on the surface of the material, improving the lattice quality, avoiding the defects from becoming non-radiative recombination centers and improving the luminous efficiency.
Wherein the second sub-layer 62 comprises Ga laminated in sequence 2 O 3 Layer 621 and MgGaN layer 622. First, ga 2 O 3 The material has large forbidden bandwidth, good electron blocking effect and low on-resistance, so compared with the traditional method of adopting high Al doped AlGaN material or AlGaN/InGaN material as an electron blocking layer, ga 2 O 3 Not only can block electron from entering, but also can not cause the rise of working voltage; secondly, the MgGaN layer 622 can increase the hole concentration, so that the hole concentration entering the multi-quantum well layer 5 is increased, and the luminous efficiency is improved; finally, the carrier is Ga 2 O 3 The mobility in the material is higher, and holes generated by the MgGaN layer 622 pass through Ga 2 O 3 The layer 621 enters the multiple quantum well layer 5, further increasing injection of holes of the multiple quantum well layer 5, and improving light emitting efficiency.
Specifically, ga 2 O 3 Layer 621 has a thickness of 10nm to 220nm. When the thickness is less than 10nm, the electron blocking effect is difficult to effectively play; when the thickness is more than 220nm, the preparation effect is highThe rate is too low. Preferably, ga 2 O 3 The thickness of layer 621 is 15nm to 200nm, and is exemplified by, but not limited to, 20nm, 30nm, 50nm, 80nm, 100nm, 120nm, 150nm, 170nm, or 180 nm.
The MgGaN layer 622 has a thickness of 2nm-60nm, and when the thickness is less than 2nm, it is difficult to effectively increase the hole concentration; when the thickness is more than 60nm, excessive defects are brought. Preferably, the MgGaN layer 622 has a thickness of 3nm to 50nm, and exemplary is 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, or 45nm, but is not limited thereto.
The Mg doping concentration in MgGaN layer 622 is 5×10 16 cm -3 -5×10 18 cm -3 . When the doping concentration of Mg is less than 5 multiplied by 10 16 cm -3 It is difficult to effectively increase the hole concentration; when the doping concentration of Mg is more than 5 multiplied by 10 18 cm -3 Excessive drawbacks can be brought about. Preferably, the doping concentration of Mg is 1×10 17 cm -3 -1×10 18 cm -3 Exemplary is 2X 10 17 cm -3 、3×10 17 cm -3 、4×10 17 cm -3 、5×10 17 cm -3 、6×10 17 cm -3 、7×10 17 cm -3 、8×10 17 cm -3 Or 9X 10 17 cm -3 But is not limited thereto.
Preferably, in another embodiment of the present invention, referring to fig. 5, the second sub-layer 62 is of a periodic structure with a period of 3-10, illustratively 4, 5, 6, 7, 8 or 9, but is not limited thereto. The periodic lamination can generate a stronger built-in electric field, so that the acceptor energy level can be reduced, two-dimensional hole gas is generated, the mobility of holes is increased, the concentration of holes entering the multi-quantum well layer 5 is increased, and the luminous efficiency is improved.
Specifically, a single Ga 2 O 3 The layer 621 has a thickness of 5nm to 20nm, and is exemplified by 8nm, 10nm, 12nm, 14nm, 16nm, or 18nm, but not limited thereto.
The thickness of the single MgGaN layer 622 is 1nm-5nm, and is exemplified by, but not limited to, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, or 4.5 nm.
Among them, the substrate 1 may be a sapphire substrate, a silicon carbide substrate, but is not limited thereto.
The nucleation layer 2 may be an AlN layer and/or an AlGaN layer, but is not limited thereto. The thickness of the nucleation layer 2 is 20nm to 100nm, and is exemplified by 30nm, 40nm, 50nm, 60nm, 70nm, 80nm or 90nm, but not limited thereto.
Among them, the intrinsic GaN layer 3 has a thickness of 300nm to 800nm, and exemplary are 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, or 750nm, but not limited thereto.
The doping element of the N-type semiconductor layer 4 is Si, but is not limited thereto. The doping concentration of the N-type semiconductor layer 4 is 5×10 18 cm -3 -1×10 19 cm -3 The thickness is 1 μm-3 μm.
The multiple quantum well layer 5 is an InGaN quantum well layer and a GaN quantum barrier layer which are alternately stacked, and the stacking period number is 3-15. The thickness of the single InGaN quantum well layer is 2nm-5nm, and the thickness of the single GaN quantum barrier layer is 6nm-15nm.
The doping element in the P-type semiconductor layer 7 is Mg, but is not limited thereto. The doping concentration of Mg in the P-type semiconductor layer 7 was 5×10 17 cm -3 -1×10 20 cm -3 . The thickness of the P-type semiconductor layer 7 is 6nm to 60nm.
Correspondingly, referring to fig. 6, the invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps:
s100: providing a substrate;
specifically, the substrate is a sapphire substrate, a silicon carbide substrate, but is not limited thereto. A sapphire substrate is preferred.
Preferably, in one embodiment of the present invention, the substrate is loaded into MOCVD and annealed at 1000-1200 deg.C, 200-600 torr, hydrogen atmosphere for 5-8 min to remove impurities such as particles, oxides, etc. on the substrate surface.
S200: growing a nucleation layer on the substrate;
specifically, MOCVD is adopted to grow an AlGaN layer as a nucleation layer, or PVD is adopted to grow an AlN layer as a nucleation layer,but is not limited thereto. Preferably, the AlGaN layer is grown by MOCVD, the growth temperature is 500-700 ℃, and the growth pressure is 200-400 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As an N source; by H 2 And N 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas.
S300: growing an intrinsic GaN layer on the nucleation layer;
specifically, the intrinsic GaN layer is grown in MOCVD at 1100-1150 deg.c and 100-500 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As an N source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
S400: growing an N-type semiconductor layer on the intrinsic GaN layer;
specifically, an N-type semiconductor layer is grown in MOCVD at 1100-1150 deg.C under 100-500 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, siH is introduced 4 As an N-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
S500: growing a multi-quantum well layer on the N-type semiconductor layer;
specifically, a quantum well layer and a quantum barrier layer are periodically grown in MOCVD to form a multi-quantum well layer. Wherein the growth temperature of the quantum well layer is 700-800 ℃, the growth pressure is 100-500 torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source. Wherein the growth temperature of the quantum barrier layer is 800-900 ℃, the growth pressure is 100-500 torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As carrier gas, TEGa was introduced as a Ga source.
S600: growing an electron blocking layer on the multiple quantum well layer;
specifically, in one embodiment of the present invention, S600 includes:
s610: growing a first sub-layer on the multiple quantum well layer;
specifically, an MgInGaN layer is grown in MOCVD, and as a first sub-layer, the first sub-layer is grown under the same growth conditions as those of an MgInGaN layer commonly used in the art. Preferably, in one embodiment of the invention, the growth temperature of the first sub-layer is gradually increased from 750 ℃ to 800 ℃ to 850 ℃ to 900 ℃ and the growth pressure is 100torr to 300torr, and NH is introduced 3 As N source, let in CP 2 Mg is used as a Mg source, TMIn is introduced as an In source, TEGa is introduced as a Ga source, and carrier gas adopted during growth is N 2 . By N 2 As a carrier gas, incorporation of the In component is facilitated. The lower growth temperature is adopted first, the low temperature is favorable for the incorporation of the In component, and the In component gradually decreases along the epitaxial direction, so that the growth temperature gradually increases, and the improvement of the lattice quality is favorable.
Preferably, in another embodiment of the present invention, the In source and the Ga source are intermittently turned on, and when the In source is turned off, the Ga source is turned on, and the Ga source is turned on for the same time as the In source is turned off; when the In source is turned on, the Ga source is interrupted, and the Ga source interruption time is the same as the In source on time. The growth method that the In source and the Ga source are intermittently introduced and the N source is continuously supplied without interruption is beneficial to eliminating defects such as In clusters, in drops and the like formed on the surface of the material, improving the lattice quality, avoiding the defects from becoming non-radiative recombination centers and improving the luminous efficiency.
S620: growing a second sub-layer on the first sub-layer;
specifically, ga is grown sequentially in a layered manner in MOCVD 2 O 3 A layer and a MgGaN layer as a second sub-layer. Preferably, in one embodiment of the present invention, ga is grown periodically in a layer-by-layer manner in MOCVD 2 O 3 A layer and a MgGaN layer as a second sub-layer. The growth temperature of the second sub-layer is 950-1000 ℃ and the growth pressure is 100-300 torr. Specifically, ga is grown 2 O 3 In the layer, let in O 2 As O source, TEGa is introduced as Ga source, and carrier gas adopted in growth is N 2 . When growing MgGaN layer, NH is introduced 3 As N source, let in CP 2 Mg is used as a Mg source, TEGa is introduced as a Ga source, and carrier gas adopted in growth is N 2 。
Growth of Ga 2 O 3 The carrier gas used in the layer is N 2 Avoiding H 2 Forming excessive H as carrier gas 2 O affects Ga 2 O 3 And (5) generating. The carrier gas adopted in the growth of MgGaN layer is N 2 Preventing the formation of Mg-H complexes, affecting Mg activation.
S700: growing a P-type semiconductor layer on the electron blocking layer;
specifically, the P-type semiconductor layer is grown in MOCVD at 800-1000 deg.C and at 100-300 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, cp is introduced 2 Mg is used as a P-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
The invention is further illustrated by the following examples:
example 1
The embodiment provides a light emitting diode epitaxial wafer, referring to fig. 1-4, which comprises a substrate 1, and a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, a multiple quantum well layer 5, an electron blocking layer 6 and a P-type semiconductor layer 7 which are sequentially arranged on the substrate 1.
Wherein the substrate 1 is a sapphire substrate; the nucleation layer 2 is an AlGaN layer, and the thickness of the AlGaN layer is 30nm; the thickness of the intrinsic GaN layer 3 is 400nm; the doping concentration of Si in the N-type semiconductor layer 4 was 7×10 18 cm -3 The thickness thereof was 2. Mu.m. The multi-quantum well layer 5 is an InGaN quantum well layer and a GaN quantum barrier layer which are alternately stacked, the stacking cycle number is 10, the thickness of a single InGaN quantum well layer is 3nm, and the thickness of a single GaN quantum barrier layer is 10nm.
Wherein the electron blocking layer 6 comprises a first sub-layer 61 and a second sub-layer 62, which are laminated in sequence. Wherein the first sub-layer 61 is a MgInGaN layer 611. The MgInGaN layer 611 has an In composition of 0.3 and a doping concentration of 5×10 Mg 15 cm -3 The thickness thereof was 15nm.
Wherein the second sub-layer 62 comprises Ga laminated in sequence 2 O 3 Layer 621 and MgGaN layer 622. Wherein Ga 2 O 3 Layer 621 has a thickness of 50nm. The Mg doping concentration in MgGaN layer 622 is 5×10 17 cm -3 The thickness thereof was 20nm.
P-type semi-solidThe doping element of the conductor layer 7 is Mg, and the doping concentration is 3.5X10 19 cm -3 The thickness was 10nm.
The preparation method of the light-emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate; the substrate was loaded into MOCVD and annealed at 1120℃under a 400torr atmosphere of hydrogen for 6min.
(2) Growing a nucleation layer on the substrate;
specifically, MOCVD is adopted to grow the AlGaN layer, the growth temperature is 620 ℃, and the growth pressure is 250torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As an N source; by H 2 And N 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas.
(3) Growing an intrinsic GaN layer on the nucleation layer;
specifically, MOCVD is adopted to grow an intrinsic GaN layer, the growth temperature is 1100 ℃, the growth pressure is 250torr, and NH is introduced into an MOCVD reaction chamber during growth 3 As an N source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
(4) Growing an N-type semiconductor layer on the intrinsic GaN layer;
specifically, MOCVD is adopted to grow an N-type semiconductor layer, the growth temperature is 1120 ℃, and the growth pressure is 150torr; during growth, NH is introduced into the MOCVD reaction chamber 3 As N source, siH is introduced 4 As an N-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
(5) Growing a multi-quantum well layer on the N-type semiconductor layer;
specifically, periodically growing a quantum well layer and a quantum barrier layer in MOCVD to obtain a multi-quantum well layer;
wherein the growth temperature of the quantum well layer is 750 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with N 2 As carrier gas, introducing TEGa as Ga source, and introducing TMIn as In source; wherein the growth temperature of the quantum barrier layer is 820 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As carrier gas, TEGa was introduced as a Ga source.
(6) Growing an electron blocking layer on the multiple quantum well layer;
specifically, the preparation method of each electron blocking layer comprises the following steps:
growing a first sub-layer on the multiple quantum well layer;
specifically, a MgInGaN layer was grown in MOCVD as the first sub-layer. The growth temperature of the first sub-layer is 780 ℃, the growth pressure is 200torr, and NH is introduced 3 As N source, let in CP 2 Mg is used as a Mg source, TMIn is introduced as an In source, TEGa is introduced as a Ga source, and carrier gas adopted during growth is N 2 。
(ii) growing a second sub-layer on the first sub-layer;
specifically, ga is grown sequentially in a layered manner in MOCVD 2 O 3 A layer and a MgGaN layer as a second sub-layer. The growth temperature of the second sub-layer was 980℃and the growth pressure was 200torr. Specifically, ga is grown 2 O 3 In the layer, let in O 2 As O source, TEGa is introduced as Ga source, and carrier gas adopted in growth is N 2 . When growing MgGaN layer, NH is introduced 3 As N source, let in CP 2 Mg is used as a Mg source, TEGa is introduced as a Ga source, and carrier gas adopted in growth is N 2 。
(7) Growing a P-type semiconductor layer on the electron blocking layer;
specifically, the P-type semiconductor layer is grown in MOCVD at 900℃and at a growth pressure of 200torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, cp is introduced 2 Mg is used as a P-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
Example 2
The embodiment provides a light emitting diode epitaxial wafer, referring to fig. 1-4, which comprises a substrate 1, and a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, a multiple quantum well layer 5, an electron blocking layer 6 and a P-type semiconductor layer 7 which are sequentially arranged on the substrate 1.
Wherein the substrate 1 is a sapphire substrate; the nucleation layer 2 is an AlGaN layer with a thickness30nm; the thickness of the intrinsic GaN layer 3 is 400nm; the doping concentration of Si in the N-type semiconductor layer 4 was 7×10 18 cm -3 The thickness thereof was 2. Mu.m. The multi-quantum well layer 5 is an InGaN quantum well layer and a GaN quantum barrier layer which are alternately stacked, the stacking cycle number is 10, the thickness of a single InGaN quantum well layer is 3nm, and the thickness of a single GaN quantum barrier layer is 10nm.
Wherein the electron blocking layer 6 comprises a first sub-layer 61 and a second sub-layer 62, which are laminated in sequence. Wherein the first sub-layer 61 is a MgInGaN layer 611. The In component of the MgInGaN layer 611 gradually decreases from 0.3 to 0 along the epitaxial growth direction, and the doping concentration of Mg is 5×10 15 cm -3 The thickness thereof was 15nm.
Wherein the second sub-layer 62 comprises Ga laminated in sequence 2 O 3 Layer 621 and MgGaN layer 622. Wherein Ga 2 O 3 Layer 621 has a thickness of 50nm. The Mg doping concentration in MgGaN layer 622 is 5×10 17 cm -3 The thickness thereof was 20nm.
The doping element of the P-type semiconductor layer 7 is Mg, and the doping concentration is 3.5X10 19 cm -3 The thickness was 10nm.
The preparation method of the light-emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate; the substrate was loaded into MOCVD and annealed at 1120℃under a 400torr atmosphere of hydrogen for 6min.
(2) Growing a nucleation layer on the substrate;
specifically, MOCVD is adopted to grow the AlGaN layer, the growth temperature is 620 ℃, and the growth pressure is 250torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As an N source; by H 2 And N 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas.
(3) Growing an intrinsic GaN layer on the nucleation layer;
specifically, MOCVD is adopted to grow an intrinsic GaN layer, the growth temperature is 1100 ℃, the growth pressure is 250torr, and NH is introduced into an MOCVD reaction chamber during growth 3 As an N source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
(4) Growing an N-type semiconductor layer on the intrinsic GaN layer;
specifically, MOCVD is adopted to grow an N-type semiconductor layer, the growth temperature is 1120 ℃, and the growth pressure is 150torr; during growth, NH is introduced into the MOCVD reaction chamber 3 As N source, siH is introduced 4 As an N-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
(5) Growing a multi-quantum well layer on the N-type semiconductor layer;
specifically, periodically growing a quantum well layer and a quantum barrier layer in MOCVD to obtain a multi-quantum well layer;
wherein the growth temperature of the quantum well layer is 750 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with N 2 As carrier gas, introducing TEGa as Ga source, and introducing TMIn as In source; wherein the growth temperature of the quantum barrier layer is 820 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As carrier gas, TEGa was introduced as a Ga source.
(6) Growing an electron blocking layer on the multiple quantum well layer;
specifically, the preparation method of each electron blocking layer comprises the following steps:
growing a first sub-layer on the multiple quantum well layer;
specifically, a MgInGaN layer was grown in MOCVD as the first sub-layer. The growth temperature of the first sub-layer is gradually increased from 780 ℃ to 880 ℃, the growth pressure is 200torr, and NH is introduced 3 As N source, let in CP 2 Mg is used as a Mg source, TMIn is introduced as an In source, TEGa is introduced as a Ga source, and carrier gas adopted during growth is N 2 。
(ii) growing a second sub-layer on the first sub-layer;
specifically, ga is grown sequentially in a layered manner in MOCVD 2 O 3 A layer and a MgGaN layer as a second sub-layer. The growth temperature of the second sub-layer was 980℃and the growth pressure was 200torr. Specifically, ga is grown 2 O 3 In the layer, let in O 2 As O source, TEGa is introduced as Ga source, and carrier gas adopted in growth is N 2 . When growing MgGaN layer, NH is introduced 3 As N source, let in CP 2 Mg is used as a Mg source, TEGa is introduced as a Ga source, and carrier gas adopted in growth is N 2 。
(7) Growing a P-type semiconductor layer on the electron blocking layer;
specifically, the P-type semiconductor layer is grown in MOCVD at 900℃and at a growth pressure of 200torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, cp is introduced 2 Mg is used as a P-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
Example 3
The embodiment provides a light emitting diode epitaxial wafer, referring to fig. 1-4, which comprises a substrate 1, and a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, a multiple quantum well layer 5, an electron blocking layer 6 and a P-type semiconductor layer 7 which are sequentially arranged on the substrate 1.
Wherein the substrate 1 is a sapphire substrate; the nucleation layer 2 is an AlGaN layer, and the thickness of the AlGaN layer is 30nm; the thickness of the intrinsic GaN layer 3 is 400nm; the doping concentration of Si in the N-type semiconductor layer 4 was 7×10 18 cm -3 The thickness thereof was 2. Mu.m. The multi-quantum well layer 5 is an InGaN quantum well layer and a GaN quantum barrier layer which are alternately stacked, the stacking cycle number is 10, the thickness of a single InGaN quantum well layer is 3nm, and the thickness of a single GaN quantum barrier layer is 10nm.
Wherein the electron blocking layer 6 comprises a first sub-layer 61 and a second sub-layer 62, which are laminated in sequence. Wherein the first sub-layer 61 is a MgInGaN layer 611. The In component of the MgInGaN layer 611 gradually decreases from 0.3 to 0 along the epitaxial growth direction, and the doping concentration of Mg is 5×10 15 cm -3 The thickness thereof was 15nm. The In source In the MgInGaN layer 611 is intermittently introduced, wherein the interruption time is 3s, and the introduction time is 8s; the Ga source In the MgInGaN layer is intermittently introduced, and when the In source is interrupted, the Ga source is introduced, and the Ga source introduction time is 3s; when the In source is turned on, the Ga source is interrupted, and the Ga source interruption time is 8s.
Wherein the second sub-layer 62 comprises Ga laminated in sequence 2 O 3 Layer 621 and MgGaN layer 622. Wherein Ga 2 O 3 Layer 621 has a thickness of 50nm. Mg in MgGaN layer 622The doping concentration is 5 multiplied by 10 17 cm -3 The thickness thereof was 20nm.
The doping element of the P-type semiconductor layer 7 is Mg, and the doping concentration is 3.5X10 19 cm -3 The thickness was 10nm.
The preparation method of the light-emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate; the substrate was loaded into MOCVD and annealed at 1120℃under a 400torr atmosphere of hydrogen for 6min.
(2) Growing a nucleation layer on the substrate;
specifically, MOCVD is adopted to grow the AlGaN layer, the growth temperature is 620 ℃, and the growth pressure is 250torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As an N source; by H 2 And N 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas.
(3) Growing an intrinsic GaN layer on the nucleation layer;
specifically, MOCVD is adopted to grow an intrinsic GaN layer, the growth temperature is 1100 ℃, the growth pressure is 250torr, and NH is introduced into an MOCVD reaction chamber during growth 3 As an N source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
(4) Growing an N-type semiconductor layer on the intrinsic GaN layer;
specifically, MOCVD is adopted to grow an N-type semiconductor layer, the growth temperature is 1120 ℃, and the growth pressure is 150torr; during growth, NH is introduced into the MOCVD reaction chamber 3 As N source, siH is introduced 4 As an N-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
(5) Growing a multi-quantum well layer on the N-type semiconductor layer;
specifically, periodically growing a quantum well layer and a quantum barrier layer in MOCVD to obtain a multi-quantum well layer;
wherein the growth temperature of the quantum well layer is 750 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with N 2 As carrier gas, introducing TEGa as Ga source, and introducing TMIn as In source; wherein the growth temperature of the quantum barrier layerThe temperature is 820 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As carrier gas, TEGa was introduced as a Ga source.
(6) Growing an electron blocking layer on the multiple quantum well layer;
specifically, the preparation method of each electron blocking layer comprises the following steps:
growing a first sub-layer on the multiple quantum well layer;
specifically, a MgInGaN layer was grown in MOCVD as the first sub-layer. The growth temperature of the first sub-layer is gradually increased from 780 ℃ to 880 ℃, the growth pressure is 200torr, and NH is introduced 3 As N source, let in CP 2 Mg is used as a Mg source, TMIn is introduced as an In source, TEGa is introduced as a Ga source, and carrier gas adopted during growth is N 2 . The In source and the Ga source are intermittently introduced, and when the In source is interrupted, the Ga source is introduced, and the Ga source introduction time is the same as the In source interruption time; when the In source is turned on, the Ga source is interrupted, and the Ga source interruption time is the same as the In source on time.
(ii) growing a second sub-layer on the first sub-layer;
specifically, ga is grown sequentially in a layered manner in MOCVD 2 O 3 A layer and a MgGaN layer as a second sub-layer. The growth temperature of the second sub-layer was 980℃and the growth pressure was 200torr. Specifically, ga is grown 2 O 3 In the layer, let in O 2 As O source, TEGa is introduced as Ga source, and carrier gas adopted in growth is N 2 . When growing MgGaN layer, NH is introduced 3 As N source, let in CP 2 Mg is used as a Mg source, TEGa is introduced as a Ga source, and carrier gas adopted in growth is N 2 。
(7) Growing a P-type semiconductor layer on the electron blocking layer;
specifically, the P-type semiconductor layer is grown in MOCVD at 900℃and at a growth pressure of 200torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, cp is introduced 2 Mg is used as a P-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
Example 4
The present embodiment provides a light emitting diode epitaxial wafer, referring to fig. 1, 2, 3, and 5, which includes a substrate 1, and a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, a multiple quantum well layer 5, an electron blocking layer 6, and a P-type semiconductor layer 7 sequentially disposed on the substrate 1.
Wherein the substrate 1 is a sapphire substrate; the nucleation layer 2 is an AlGaN layer, and the thickness of the AlGaN layer is 30nm; the thickness of the intrinsic GaN layer 3 is 400nm; the doping concentration of Si in the N-type semiconductor layer 4 was 7×10 18 cm -3 The thickness thereof was 2. Mu.m. The multi-quantum well layer 5 is an InGaN quantum well layer and a GaN quantum barrier layer which are alternately stacked, the stacking cycle number is 10, the thickness of a single InGaN quantum well layer is 3nm, and the thickness of a single GaN quantum barrier layer is 10nm.
Wherein the electron blocking layer 6 comprises a first sub-layer 61 and a second sub-layer 62, which are laminated in sequence. Wherein the first sub-layer 61 is a MgInGaN layer 611. The In component of the MgInGaN layer 611 gradually decreases from 0.3 to 0 along the epitaxial growth direction, and the doping concentration of Mg is 5×10 15 cm -3 The thickness thereof was 15nm. The In source In the MgInGaN layer 611 is intermittently introduced, wherein the interruption time is 3s, and the introduction time is 8s; the Ga source In the MgInGaN layer is intermittently introduced, and when the In source is interrupted, the Ga source is introduced, and the Ga source introduction time is 3s; when the In source is turned on, the Ga source is interrupted, and the Ga source interruption time is 8s.
Wherein the second sub-layer 62 comprises Ga periodically and sequentially laminated 2 O 3 Layer 621 and MgGaN layer 622, with a cycle number of 6. Wherein, single Ga 2 O 3 Layer 621 has a thickness of 10nm. The thickness of the single MgGaN layer 622 is 5nm, and the doping concentration of Mg is 5×10 17 cm -3 。
The doping element of the P-type semiconductor layer 7 is Mg, and the doping concentration is 3.5X10 19 cm -3 The thickness was 10nm.
The preparation method of the light-emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate; the substrate was loaded into MOCVD and annealed at 1120℃under a 400torr atmosphere of hydrogen for 6min.
(2) Growing a nucleation layer on the substrate;
specifically, MOCVD is adoptedAnd growing AlGaN layer at 620 deg.C and 250torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As an N source; by H 2 And N 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas.
(3) Growing an intrinsic GaN layer on the nucleation layer;
specifically, MOCVD is adopted to grow an intrinsic GaN layer, the growth temperature is 1100 ℃, the growth pressure is 250torr, and NH is introduced into an MOCVD reaction chamber during growth 3 As an N source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
(4) Growing an N-type semiconductor layer on the intrinsic GaN layer;
specifically, MOCVD is adopted to grow an N-type semiconductor layer, the growth temperature is 1120 ℃, and the growth pressure is 150torr; during growth, NH is introduced into the MOCVD reaction chamber 3 As N source, siH is introduced 4 As an N-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
(5) Growing a multi-quantum well layer on the N-type semiconductor layer;
specifically, periodically growing a quantum well layer and a quantum barrier layer in MOCVD to obtain a multi-quantum well layer;
wherein the growth temperature of the quantum well layer is 750 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with N 2 As carrier gas, introducing TEGa as Ga source, and introducing TMIn as In source; wherein the growth temperature of the quantum barrier layer is 820 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As carrier gas, TEGa was introduced as a Ga source.
(6) Growing an electron blocking layer on the multiple quantum well layer;
specifically, the preparation method of each electron blocking layer comprises the following steps:
growing a first sub-layer on the multiple quantum well layer;
specifically, a MgInGaN layer was grown in MOCVD as the first sub-layer. The growth temperature of the first sub-layer is gradually increased from 780 ℃ to 880 DEG CThe growth pressure is 200torr, and NH is introduced 3 As N source, let in CP 2 Mg is used as a Mg source, TMIn is introduced as an In source, TEGa is introduced as a Ga source, and carrier gas adopted during growth is N 2 . The In source and the Ga source are intermittently introduced, and when the In source is interrupted, the Ga source is introduced, and the Ga source introduction time is the same as the In source interruption time; when the In source is turned on, the Ga source is interrupted, and the Ga source interruption time is the same as the In source on time.
(ii) growing a second sub-layer on the first sub-layer;
specifically, ga is grown periodically in a layer-by-layer manner in MOCVD 2 O 3 A layer and a MgGaN layer as a second sub-layer. The growth temperature of the second sub-layer was 980℃and the growth pressure was 200torr. Specifically, ga is grown 2 O 3 In the layer, let in O 2 As O source, TEGa is introduced as Ga source, and carrier gas adopted in growth is N 2 . When growing MgGaN layer, NH is introduced 3 As N source, let in CP 2 Mg is used as a Mg source, TEGa is introduced as a Ga source, and carrier gas adopted in growth is N 2 。
(7) Growing a P-type semiconductor layer on the electron blocking layer;
specifically, the P-type semiconductor layer is grown in MOCVD at 900℃and at a growth pressure of 200torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, cp is introduced 2 Mg is used as a P-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
Comparative example 1
This comparative example provides a light emitting diode epitaxial wafer which is different from example 1 in that the electron blocking layer 6 in the epitaxial wafer is an AlGaN layer, the Al component in the AlGaN layer is 0.6 in proportion, and the thickness thereof is 50nm. Accordingly, in the production method, the growth temperature of the AlGaN layer was 980℃and the growth pressure was 200torr, and the rest was the same as in example 1.
Comparative example 2
This comparative example provides a light emitting diode epitaxial wafer, which is different from example 1 in that the electron blocking layer 6 in the epitaxial wafer is Al a Ga 1-a N layers (a=0.12) and In b Ga 1-b N layer (b=0.3 A periodic structure with a period of 8, a single Al a Ga 1-a The thickness of the N layer is 5nm, single In b Ga 1-b The thickness of the N layer was 1nm, and accordingly, in the production method, the growth temperature of the electron blocking layer 6 was 980 ℃, the growth pressure was 200torr, and the rest was the same as in example 1.
Comparative example 3
This comparative example provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that the second sub-layer 62 is not included in the electron blocking layer 6. Accordingly, the preparation step of this layer was not provided in the preparation method, and the rest was the same as in example 1.
Comparative example 4
This comparative example provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that the first sub-layer 61 is not included in the electron blocking layer 6. Accordingly, the preparation step of this layer was not provided in the preparation method, and the rest was the same as in example 1.
Comparative example 5
This comparative example provides a light emitting diode epitaxial wafer which is different from example 1 in that Ga is not included in the electron blocking layer 6 2 O 3 Layer 621. Accordingly, the preparation step of this layer was not provided in the preparation method, and the rest was the same as in example 1.
The light emitting diode epitaxial wafers obtained in examples 1 to 4 and comparative examples 1 to 5 were subjected to brightness and operating voltage tests, and the specific test methods were as follows:
(1) Preparing the epitaxial wafer into a chip with a vertical structure of 10mil multiplied by 24mil, and testing the luminous brightness of the chip;
(2) Operating voltage: the operating voltage test was performed using a Keithley2450 digital source table.
The specific results are as follows:
brightness (mW) Working voltage (V)
Example 1 194.3 3.14
Example 2 195.1 3.13
Example 3 195.5 3.11
Example 4 196.8 3.09
Comparative example 1 190.6 3.23
Comparative example 2 192.1 3.21
Comparative example 3 192.2 3.19
Comparative example 4 192.7 3.18
Comparative example 5 193.1 3.18
As can be seen from the table, when the conventional electron blocking layer (comparative example 1) was changed to the electron blocking layer structure of the present invention, the brightness was increased from 190.6mW to 194.3mW, and the operating voltage was decreased from 3.23V to 3.14V, which indicates that the electron blocking layer of the present invention can effectively increase the brightness and decrease the operating voltage. Further, as can be seen from a comparison of example 1 with comparative examples 2 to 5, when the electron blocking layer structure in the present invention is changed, it is difficult to effectively achieve the effects of increasing luminance and lowering operating voltage.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.

Claims (10)

1. A light-emitting diode epitaxial wafer comprises a substrate, and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer and a P-type semiconductor layer which are sequentially arranged on the substrate; the electron blocking layer is characterized by comprising a first sub-layer and a second sub-layer which are sequentially laminated;
wherein the first sub-layer is an MgInGaN layer;
the second sub-layer comprises Ga laminated in sequence 2 O 3 A layer and a MgGaN layer.
2. The led epitaxial wafer of claim 1, wherein the In composition of the MgInGaN layer gradually decreases from 0.2-0.4 to 0 along the epitaxial growth direction.
3. The led epitaxial wafer of claim 1, wherein the Mg concentration in the MgInGaN layer is 1 x 10 15 cm -3 -1×10 16 cm -3 The thickness of the MgInGaN layer is 5nm-50nm.
4. The light-emitting diode epitaxial wafer of claim 1, wherein the In source In the MgInGaN layer is intermittently introduced, wherein the interruption time is 1s-5s and the introduction time is 5s-10s;
the Ga source In the MgInGaN layer is intermittently introduced, and when the In source is interrupted, the Ga source is introduced, and the Ga source introduction time is the same as the In source interruption time; when the In source is turned on, the Ga source is interrupted, and the Ga source interruption time is the same as the In source on time.
5. The light-emitting diode epitaxial wafer of claim 1, wherein the Ga 2 O 3 The thickness of the layer is 15nm-200nm;
the MgGaN layer has a thickness of 3nm-50nm and a doping concentration of 1×10 Mg 17 cm -3 -1×10 18 cm -3 。
6. The light-emitting diode epitaxial wafer of any one of claims 1-5, wherein the second sub-layer is of a periodic structure, and the number of periods is 3-10;
wherein, the Ga is singly 2 O 3 The thickness of the layer is 5nm-20nm;
the thickness of the MgGaN layer is 1nm-5nm.
7. A method for preparing a light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer according to any one of claims 1 to 6, and is characterized by comprising:
providing a substrate, and sequentially growing a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer and a P-type semiconductor layer on the substrate; the electron blocking layer comprises a first sub-layer and a second sub-layer which are sequentially laminated;
wherein the first sub-layer is an MgInGaN layer;
the second sub-layer comprises Ga laminated in sequence 2 O 3 A layer and a MgGaN layer.
8. The method for preparing a light-emitting diode epitaxial wafer according to claim 7, wherein the growth temperature of the first sub-layer is gradually increased from 750 ℃ to 800 ℃ to 850 ℃ to 900 ℃ and the growth pressure is 100torr to 300torr;
the growth temperature of the second sub-layer is 950-1000 ℃, and the growth pressure is 100-300 torr.
9. The method of claim 7, wherein the carrier gas used for growing the first and second sub-layers is N 2 。
10. A light emitting diode comprising the light emitting diode epitaxial wafer according to any one of claims 1 to 6.
CN202310232249.4A 2023-03-10 2023-03-10 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode Pending CN116169216A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310232249.4A CN116169216A (en) 2023-03-10 2023-03-10 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310232249.4A CN116169216A (en) 2023-03-10 2023-03-10 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Publications (1)

Publication Number Publication Date
CN116169216A true CN116169216A (en) 2023-05-26

Family

ID=86418298

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310232249.4A Pending CN116169216A (en) 2023-03-10 2023-03-10 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Country Status (1)

Country Link
CN (1) CN116169216A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116504895A (en) * 2023-06-29 2023-07-28 江西兆驰半导体有限公司 LED epitaxial wafer, preparation method thereof and LED
CN116632137A (en) * 2023-07-24 2023-08-22 江西乾照光电有限公司 Antistatic capability improvement layer, preparation method thereof, epitaxial wafer and light-emitting diode
CN117894898A (en) * 2024-03-15 2024-04-16 江西兆驰半导体有限公司 Deep ultraviolet LED epitaxial wafer, preparation method thereof and deep ultraviolet LED

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116504895A (en) * 2023-06-29 2023-07-28 江西兆驰半导体有限公司 LED epitaxial wafer, preparation method thereof and LED
CN116504895B (en) * 2023-06-29 2023-09-05 江西兆驰半导体有限公司 LED epitaxial wafer, preparation method thereof and LED
CN116632137A (en) * 2023-07-24 2023-08-22 江西乾照光电有限公司 Antistatic capability improvement layer, preparation method thereof, epitaxial wafer and light-emitting diode
CN116632137B (en) * 2023-07-24 2023-10-10 江西乾照光电有限公司 Antistatic capability improvement layer, preparation method thereof, epitaxial wafer and light-emitting diode
CN117894898A (en) * 2024-03-15 2024-04-16 江西兆驰半导体有限公司 Deep ultraviolet LED epitaxial wafer, preparation method thereof and deep ultraviolet LED
CN117894898B (en) * 2024-03-15 2024-06-11 江西兆驰半导体有限公司 Deep ultraviolet LED epitaxial wafer, preparation method thereof and deep ultraviolet LED

Similar Documents

Publication Publication Date Title
CN116053378B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN116093223B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN116169216A (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN116581217B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN115832138B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN115775853B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN115881865B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN116072780B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117253950B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN114597293A (en) Light emitting diode epitaxial wafer and preparation method thereof
CN117253948B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN116759508A (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN116454186A (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN116504895A (en) LED epitaxial wafer, preparation method thereof and LED
CN117393671B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN116014041B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN115799415B (en) LED epitaxial wafer, preparation method thereof and LED
CN116682914A (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode epitaxial wafer
CN116914049A (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN217641376U (en) LED epitaxial wafer and LED chip
CN116093218A (en) GaN-based light-emitting diode epitaxial wafer, preparation method thereof and GaN-based light-emitting diode
CN109461802B (en) GaN-based light emitting diode epitaxial wafer and preparation method thereof
CN116581219B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117810324B (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN116404079A (en) Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination