CN116454186A - Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode - Google Patents
Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
- H01L33/325—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen characterised by the doping materials
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, and relates to the field of semiconductor photoelectric devices. The light-emitting diode epitaxial wafer comprises a substrate, an N-type semiconductor layer, a first V-shaped pit opening layer, a first multi-quantum well layer, a V-shaped pit adjusting layer, a second multi-quantum well layer and a P-type semiconductor layer which are sequentially laminated on the substrate; the cycle number of the first multi-quantum well layer is more than or equal to that of the second multi-quantum well layer; the V-shaped pit adjusting layer comprises a V-shaped pit filling layer and a second V-shaped pit opening layer; the first V-shaped pit opening layer is opened to obtain a first V-shaped pit, the V-shaped pit filling layer is used for filling the first V-shaped pit, and the second V-shaped pit opening layer is opened to obtain a second V-shaped pit; the opening size of the second V-shaped pit is smaller than the opening size of the first V-shaped pit. By implementing the invention, the luminous efficiency and antistatic capability of the LED epitaxial wafer can be improved.
Description
Technical Field
The invention relates to the field of semiconductor photoelectric devices, in particular to a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode.
Background
In light emitting diodes, V-pit technology is an important means of improving the luminous efficiency. The V-shaped side wall of the V-shaped pit is in a V-shaped shape and penetrates through the whole active region, holes are easily injected into a deeper luminescent quantum well through the V-shaped side wall due to the special geometric structure of the V-shaped pit, the working voltage can be reduced, the uneven distribution of electrons and holes in space can be improved, and the luminous efficiency can be improved. However, V-shaped pits are generated along the dislocation of the underlying layer, which is a natural leakage path, and can affect the antistatic ability of the light emitting diode. In addition, in the growth process of the V-shaped pit, a plurality of defects are easily introduced, and the V-shaped pit becomes a non-radiative recombination center to capture carriers, so that the internal quantum efficiency is influenced, and the luminous efficiency is influenced. But also has an effect on the surface flatness of the epitaxial layer.
Disclosure of Invention
The invention aims to solve the technical problem of providing a light-emitting diode epitaxial wafer and a preparation method thereof, which can improve the light-emitting efficiency and antistatic capability of a light-emitting diode.
The invention also solves the technical problem of providing a light-emitting diode which has high luminous efficiency and strong antistatic energy.
In order to solve the problems, the invention discloses a light-emitting diode epitaxial wafer, which comprises a substrate, an N-type semiconductor layer, a first V-shaped pit opening layer, a first multi-quantum well layer, a V-shaped pit adjusting layer, a second multi-quantum well layer and a P-type semiconductor layer, wherein the N-type semiconductor layer, the first V-shaped pit opening layer, the first multi-quantum well layer, the V-shaped pit adjusting layer, the second multi-quantum well layer and the P-type semiconductor layer are sequentially laminated on the substrate;
the cycle number of the first multi-quantum well layer is more than or equal to the cycle number of the second multi-quantum well layer;
the V-shaped pit adjusting layer comprises a V-shaped pit filling layer and a second V-shaped pit opening layer; the first V-shaped pit opening layer is opened to obtain a first V-shaped pit, the V-shaped pit filling layer is used for filling the first V-shaped pit, and the second V-shaped pit opening layer is opened to obtain a second V-shaped pit;
the opening size of the second V-shaped pit is smaller than the opening size of the first V-shaped pit.
As an improvement of the above technical solution, the number of cycles of the first multiple quantum well layer is 1-3 more than the number of cycles of the second multiple quantum well layer;
the opening size of the first V-shaped pit is 150nm-300nm, and the opening size of the second V-shaped pit is 10nm-150nm.
As an improvement of the above technical solution, the first V-shaped pit opening layer has a periodic structure, the number of periods is 2-10, and each period includes a first InGaN layer and a GaN layer laminated in sequence; the thickness of each first InGaN layer is 2nm-6nm, and the thickness of each GaN layer is 8nm-15nm.
As an improvement of the technical proposal, the V-shaped pit filling layer is P-In x Al y Ga 1-x-y And an N layer, wherein x is 0.01-0.1, y is 0.1-0.3, and the thickness of the N layer is 10nm-50nm.
As an improvement of the technical proposal, the V-shaped pit filling layer is P-In x Al y Ga 1-x-y An N layer, wherein x is 0.05-0.1, and y is 0.2-0.3;
the opening size of the first V-shaped pit is 250nm-350nm.
As an improvement of the above technical solution, the second V-shaped pit opening layer has a periodic structure, the number of periods is 2-10, and each period includes an AlGaN layer and a second InGaN layer which are sequentially stacked; the thickness of each AlGaN layer is 5nm-15nm, and the thickness of each second InGaN layer is 1nm-3nm;
the Al component In the AlGaN layer accounts for 0.05-0.15, and the In component In the second InGaN layer accounts for 0.02-0.1.
As an improvement of the technical scheme, the semiconductor material further comprises a nucleation layer, an intrinsic semiconductor layer and an electron blocking layer;
the nucleation layer and the intrinsic semiconductor layer are sequentially laminated between the substrate and the N-type semiconductor layer, and the electron blocking layer is arranged between the second multi-quantum well layer and the P-type semiconductor layer;
the intrinsic semiconductor layer is an intrinsic GaN layer, the N-type semiconductor layer is an N-type GaN layer, and the P-type semiconductor layer is a P-type GaN layer;
the first multi-quantum well layer and the second multi-quantum well layer are periodic structures formed by alternately stacking InGaN well layers and GaN barrier layers.
Correspondingly, the invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps:
providing a substrate, and sequentially forming an N-type semiconductor layer, a first V-shaped pit opening layer, a first multi-quantum well layer, a V-shaped pit adjusting layer, a second multi-quantum well layer and a P-type semiconductor layer on the substrate;
the cycle number of the first multi-quantum well layer is more than or equal to the cycle number of the second multi-quantum well layer;
the V-shaped pit adjusting layer comprises a V-shaped pit filling layer and a second V-shaped pit opening layer; the first V-shaped pit opening layer is opened to obtain a first V-shaped pit, the V-shaped pit filling layer is used for filling the first V-shaped pit, and the second V-shaped pit opening layer is opened to obtain a second V-shaped pit;
the opening size of the second V-shaped pit is smaller than the opening size of the first V-shaped pit.
As an improvement of the technical scheme, the growth temperature of the first V-shaped pit opening layer is 700-900 ℃ and the growth pressure is 100-500 torr;
the growth temperature of the V-shaped pit filling layer is 900-1000 ℃ and the growth pressure is 100-300 torr;
the growth temperature of the second V-shaped pit opening layer is 850-950 ℃ and the growth pressure is 100-300 torr.
Correspondingly, the invention also discloses a light-emitting diode, which comprises the light-emitting diode epitaxial wafer.
The implementation of the invention has the following beneficial effects:
1. the light-emitting diode epitaxial wafer is provided with a first V-shaped pit opening layer, a first multi-quantum well layer, a V-shaped pit adjusting layer, a second multi-quantum well layer and a P-type semiconductor layer which are sequentially stacked; the V-shaped pit adjusting layer comprises a V-shaped pit filling layer and a second V-shaped pit opening layer, wherein the V-shaped pit filling layer is used for filling the first V-shaped pit, and the second V-shaped pit opening layer is used for opening to obtain a second V-shaped pit; and the opening size of the second V-shaped pit is smaller than the opening size of the first V-shaped pit. Namely, the V-shaped pit is divided into two parts, the first V-shaped pit with larger opening size is adopted in the first multi-quantum well layer close to the N-type semiconductor layer, and the second V-shaped pit with smaller opening size is adopted in the second multi-quantum well layer close to the P-type semiconductor layer, so that a leakage channel is effectively reduced, the antistatic capability of the light emitting diode epitaxial wafer is improved, and meanwhile, the surface flatness of the light emitting diode epitaxial wafer is also improved. Further, since the second multiple quantum well layer is close to the P-type semiconductor layer, the hole concentration is relatively high; the first multi-quantum well layer is close to the N-type semiconductor layer, and the hole concentration of the first multi-quantum well layer is low; by adopting the technology of combining the first V-shaped pit and the second V-shaped pit, the efficiency of injecting holes into the first multi-quantum well layer from the side wall of the first V-shaped pit is improved by adopting the first V-shaped pit with large opening size, and the crystal quality of the second multi-quantum well layer is improved by adopting the second V-shaped pit with small size, so that defects are reduced. The two are combined, so that the radiation recombination efficiency is effectively improved, and the luminous efficiency of the LED epitaxial wafer is improved. In addition, the cycle number of the first multi-quantum well layer is more than or equal to that of the second multi-quantum well layer, and based on the arrangement, the hole concentration of the whole multi-quantum well region can be balanced better, and the luminous efficiency of the LED epitaxial wafer is improved.
2. The V-shaped pit filling layer of the invention is P-In x Al y Ga 1-x-y The N layer not only plays a role in filling and leveling, but also can provide holes, and the number of the holes entering the first multi-quantum well layer through the first V-shaped pit opening layer can be increased, so that the electron-hole recombination efficiency of the first multi-quantum well layer is increased, and the luminous efficiency is improved. Furthermore, by controlling P-In x Al y Ga 1-x-y The content of In component and Al component In the N layer can effectively improve the lattice quality of the N layer, and improve the lattice matching of the V-shaped pit filling layer and the first multi-quantum well layer, so that the opening of the first V-shaped pit opening layer can be larger, thereby being beneficial to hole injectionAnd the first multi-quantum well layer is arranged, so that a larger process window is provided for the antistatic capability and the surface flatness.
3. The second V-shaped pit opening layer is of a periodical structure formed by repeatedly stacking AlGaN/InGaN. The Al atoms in AlGaN are smaller, so that lattice defects can be reduced as complementary atoms, and the opening of the generated V-shaped pit is easier to control, so that a second V-shaped pit with smaller opening is formed.
Drawings
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
FIG. 2 is a schematic view showing the structure of a first V-shaped pit opening layer according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a second V-shaped pit opening layer according to an embodiment of the present invention;
fig. 4 is a flowchart of a method for manufacturing an led epitaxial wafer according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below in order to make the objects, technical solutions and advantages of the present invention more apparent.
Referring to fig. 1 and 2, the invention discloses a light emitting diode epitaxial wafer, which comprises a substrate 1, an N-type semiconductor layer 2, a first V-shaped pit opening layer 3, a first multi-quantum well layer 4, a V-shaped pit adjusting layer 5, a second multi-quantum well layer 6 and a P-type semiconductor layer 7 which are sequentially stacked on the substrate 1. The V-shaped pit adjustment layer 5 includes a V-shaped pit filling layer 51 and a second V-shaped pit opening layer 52; the first V-shaped pit opening layer 3 is opened to obtain a first V-shaped pit 3a, the V-shaped pit filling layer 51 fills the first V-shaped pit 3a, and the second V-shaped pit opening layer 52 is opened to obtain a second V-shaped pit 52a; the opening size of the second V-shaped pit 52a < the opening size of the first V-shaped pit 3 a.
The first V-shaped pit opening layer 3 is of a periodic structure, the period number is 2-10, and each period comprises a first InGaN layer 31 and a GaN layer 32 which are sequentially stacked; the opening size of the first V-shaped pit 3a opened based on the structure is large, 100nm to 400nm, and is exemplified by 120nm, 140nm, 180nm, 240nm, 280nm, 300nm, 340nm, or 380nm, but not limited thereto. Preferably 150nm to 300nm. The first V-shaped pit 3a can effectively promote holes to flow into the first multi-quantum well layer 4, and improve luminous efficiency. Here, the opening size of the first V-shaped pit 3a refers to the width of the top surface of the first V-shaped pit 3a when it extends to the top of the first multiple quantum well layer 4 (the V-shaped pit is hexagonal-like, and the width refers to the width of the top surface at the two most distant vertexes, i.e., D in fig. 1).
The thickness of each first InGaN layer 31 is 1nm to 10nm, and is exemplified by 2nm, 4nm, 6nm, 8nm, or 9nm, but is not limited thereto. Preferably 2nm to 6nm. The thickness of each GaN layer 32 is 5nm-15nm, and is exemplified by, but not limited to, 6nm, 8nm, 10nm, 12nm, or 14 nm.
The V-shaped pit filling layer 51 may be made of GaN or AlGaN, but is not limited thereto. Preferably, in one embodiment of the present invention, V-shaped pit filling layer 51 is P-In x Al y Ga 1-x-y And an N layer, wherein x is 0.01-0.1, and y is 0.1-0.3. The V-shaped pit filling layer 51 made of this material can not only fill up the first V-shaped pit 3a but also provide a cavity. The Al-N bond strength introduced by Al in the V-shaped pit filling layer 51 is higher than the Ga-N bond strength, and the lattice quality of the V-shaped pit filling layer is higher. In V-pit filling layer 51 may reduce lattice mismatch with first multi-quantum well layer 4.
Preferably, in one embodiment of the present invention, x is controlled to be 0.05-0.1 and y is controlled to be 0.2-0.3. The lattice quality of the V-shaped pit filling layer 51 is high, so that the first V-shaped pit opening layer 3 can form a first V-shaped pit 3a with a larger size, and specifically, the opening size of the first V-shaped pit 3a based on the material can reach 250nm-350nm.
The thickness of the V-shaped pit filling layer 51 is 10nm to 100nm, and when the thickness thereof is < 10nm, it is difficult to efficiently fill up the first V-shaped pit 3a; when the thickness is more than 100nm, the electron concentration in the second multi-quantum well layer 6 is too low, the radiation recombination efficiency is low, and the luminous efficiency is reduced. Preferably, the thickness of the V-shaped pit art layer 51 is 10nm to 50nm.
The second V-shaped pit opening layer 52 has a periodic structure, and the period is 2-10, and each period includes an AlGaN layer 521 and a second InGaN layer 522 stacked in order. The second V-shaped pit opening layer 52 of this structure forms a second V-shaped pit 52a having a smaller opening, thereby reducing the leakage path and reducing the surface roughness of the light emitting diode epitaxial wafer. Specifically, the opening size of the second V-shaped pit 52a is 10nm to 200nm, and exemplary is 30nm, 50nm, 90nm, 120nm, 150nm, 170nm or 190nm, but is not limited thereto. Preferably 10nm to 150nm. Here, the opening size of the second V-shaped pit 52a refers to the width of the top surface of the second V-shaped pit 52a when it extends to the top of the second multi-quantum well layer 6 (the V-shaped pit is hexagonal-like, and the width refers to the width of the top surface at the two most vertices thereof, i.e., d in fig. 1).
The thickness of each AlGaN layer 521 is 2nm to 20nm, and is exemplified by 3nm, 7nm, 11nm, 15nm, or 19nm, but is not limited thereto. Preferably 2nm to 6nm. The thickness of each second InGaN layer 522 is 1nm to 5nm, and exemplary are 2nm, 3nm, and 4nm, but not limited thereto. Preferably 1nm to 3nm.
The Al composition ratio (i.e., the molar ratio of Al composition AlN) in AlGaN layer 521 is 0.05 to 0.2, and is exemplified by, but not limited to, 0.08, 0.1, 0.13, 0.15, or 0.18. Preferably 0.05-0.15.
The In composition ratio (i.e., the molar ratio of the In composition InN) In the second InGaN layer 522 is 0.02 to 0.15, and exemplary is 0.04, 0.06, 0.1, 0.11, or 0.13, but is not limited thereto. Preferably 0.02 to 0.1.
The structures of the first V-shaped pit opening layer 3 and the V-shaped pit adjustment layer 5 described above are applicable to, but not limited to, gaN-based light emitting diode epitaxial wafers, alGaN-based light emitting diode epitaxial wafers, and GaAs-based light emitting diode epitaxial wafers. Correspondingly, the multi-quantum well structure, the N-type semiconductor layer and the P-type semiconductor layer can be selected according to the specific type of the light-emitting diode epitaxial wafer.
Among them, the substrate 1 may be a sapphire substrate, a silicon carbide substrate, a gallium oxide substrate, a zinc oxide substrate, but is not limited thereto.
The N-type semiconductor layer 2 is an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer, but is not limited thereto. The N-type GaN layer is preferable, and the V-shaped pit has the strongest effect on improving the luminous efficiency of the GaN-based light emitting diode. The doping element of the N-type semiconductor layer 2 is Si, and the doping concentration is 5×10 18 cm -3 -1×10 19 cm -3 Thickness of 1 mum-3μm。
The first multiple quantum well layer 4 and the second multiple quantum well layer 6 are made of the same material or different materials, preferably the same material, and may be an AlGaN/AlGaN type multiple quantum well layer, an InGaN/GaN type multiple quantum well layer or an InGaAs/GaAs type multiple quantum well layer, but not limited thereto. Preferably, in one embodiment of the present invention, the first multi-quantum well layer 4 and the second multi-quantum well layer 6 are both InGaN/GaN multi-quantum well layers. I.e., it is composed of a periodically stacked InGaN well layer and GaN barrier layer. Wherein the thickness of the single InGaN well layer is 3nm-7nm, and the thickness of the single GaN barrier layer is 6nm-15nm.
The number of cycles of the first multi-quantum well layer 4 is greater than or equal to the number of cycles of the second multi-quantum well layer 6, and based on the arrangement, the electron concentration and the hole concentration in the first multi-quantum well layer 4 and the second multi-quantum well layer 6 can be balanced better, the radiation recombination efficiency is improved, and the luminous efficiency is improved. Specifically, in one embodiment of the present invention, the number of cycles of the first multiple quantum well layer 4 is 2-10, the number of cycles of the second multiple quantum well layer 6 is 2-8, and the number of cycles of the first multiple quantum well layer 4 is 1-3 more than the number of cycles of the second multiple quantum well layer 6.
The P-type semiconductor layer 7 is, but not limited to, a P-type GaN layer, a P-type AlGaN layer, or a P-type GaAs layer. A P-type GaN layer is preferred. The P-type doping element of the P-type semiconductor layer 7 is Mg, and the doping concentration is 5×10 17 cm -3 -1×10 20 cm -3 . The thickness of the P-type semiconductor layer 7 is 200nm to 300nm.
In addition, the light emitting diode epitaxial wafer of the invention further comprises a plurality of common additional structural layers, such as a nucleation layer, an intrinsic semiconductor layer, an electron blocking layer, an ohmic contact layer and the like, but is not limited thereto. Preferably, in one embodiment of the present invention, the light emitting diode epitaxial wafer further comprises a nucleation layer 8, an intrinsic semiconductor layer 9 and an electron blocking layer 10.
Wherein a nucleation layer 8 and an intrinsic semiconductor layer 9 are sequentially laminated between the substrate 1 and the N-type semiconductor layer 2. The nucleation layer 8 may be an AlN layer or an AlGaN layer, but is not limited thereto. The nucleation layer 8 has a thickness of 20nm to 100nm. The intrinsic semiconductor layer 9 is, but not limited to, an undoped GaN layer, an undoped AlGaN layer, and an undoped GaAs layer. Preferably, in one embodiment of the present invention, the intrinsic semiconductor layer 9 is an undoped GaN layer having a thickness of 300nm to 800nm.
The electron blocking layer 10 is disposed between the second multiple quantum well layer 6 and the P-type semiconductor layer 7. Which is an AlGaN layer or InAlGaN layer, but is not limited thereto. Preferably, in one embodiment of the present invention, the electron blocking layer 10 is Al a Ga 1-a N layer and In b Ga 1-b The periodic structure of the N layers alternately grows, and the period number is 3-15; wherein a is 0.05-0.2, and b is 0.1-0.5. Single Al a Ga 1-a The thickness of the N layer is 3nm-10nm, and single In b Ga 1-b The thickness of the N layer is 3nm-10nm. The thickness of the electron blocking layer 10 is 20nm to 100nm.
Correspondingly, referring to fig. 4, the invention also discloses a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps:
s1 the method comprises the following steps: providing a substrate;
preferably, in one embodiment of the present invention, the substrate is loaded into MOCVD and annealed at 1000-1200 deg.C, 200-600 torr, hydrogen atmosphere for 5-8 min to remove impurities such as particles, oxides, etc. on the substrate surface.
S2: sequentially growing an N-type semiconductor layer, a first V-shaped pit opening layer, a first multi-quantum well layer, a V-shaped pit adjusting layer, a second multi-quantum well layer and a P-type semiconductor layer on a substrate;
in one embodiment of the present invention, step S2 includes sequentially growing a nucleation layer, an intrinsic semiconductor layer, an N-type semiconductor layer, a first V-type pit opening layer, a first multiple quantum well layer, a V-type pit adjustment layer, a second multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer on a substrate. Specifically, in this embodiment, step S2 includes:
s21: growing a nucleation layer on the substrate;
specifically, S21 includes:
among them, the AlN layer may be grown by PVD, or may be grown by MOCVD, but is not limited thereto.
S22: growing an intrinsic semiconductor layer on the nucleation layer;
among them, an undoped GaN layer, an undoped AlGaN layer or an undoped GaAs layer may be grown by MBE, MOCVD, but is not limited thereto. Preferably, in one embodiment of the present invention, the undoped GaN layer is grown by MOCVD at a growth temperature of 1100-1150 ℃ and a growth pressure of 100-500 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As an N source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
S23: growing an N-type semiconductor layer on the intrinsic semiconductor layer;
among them, an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer may be grown by MBE, MOCVD, but is not limited thereto. Preferably, in one embodiment of the present invention, the N-type GaN layer is grown by MOCVD at a growth temperature of 1100-1150 ℃ and a growth pressure of 100-500 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, siH is introduced 4 As an N-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
S24: growing a first V-shaped pit opening layer on the N-type semiconductor layer;
wherein, in one embodiment of the present invention, a plurality of first InGaN layers and GaN layers are periodically grown by MOCVD as the first V-pit opening layer. Wherein the growth temperature of the GaN layer is 700-900 ℃, the growth pressure is 100-500 torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As carrier gas, or in N 2 As carrier gas, TEGa was introduced as a Ga source. Wherein the growth temperature of the first InGaN layer is 700-900 ℃, the growth pressure is 100-500 torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As carrier gas, or in N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source.
Preferably, in one embodiment of the present invention, the first InGaN layer is grown using N 2 As a carrier gas, the regulation effect on the size of the first V-shaped pit 3a can be enhanced.
S25: growing a first multiple quantum well layer on the first V-shaped pit opening layer;
among them, an AlGaN/AlGaN type multiple quantum well layer, an InGaN/GaN type multiple quantum well layer, or an InGaAs/GaAs type multiple quantum well layer may be grown by MBE, MOCVD, but is not limited thereto. Preferably, in one embodiment of the present invention, the InGaN well layer and the GaN barrier layer are periodically grown in MOCVD to form the first multi-quantum well layer. Wherein the growth temperature of the InGaN well layer is 700-800 ℃, the growth pressure is 100-500 torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source. Wherein the growth temperature of the GaN barrier layer is 800-900 ℃, the growth pressure is 100-500 torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As carrier gas, TEGa was introduced as a Ga source.
S25: growing a V-shaped pit adjusting layer on the first multi-quantum well layer;
wherein, in one embodiment of the present invention, S25 includes:
s251: growing a V-shaped pit filling layer on the first multi-quantum well layer;
wherein the GaN layer, alGaN layer or P-In layer can be grown by MOCVD, MBE x Al y Ga 1-x-y The N layer is not limited to this, and may be a V-shaped pit filling layer. Preferably, in one embodiment of the present invention, the P-In is grown by MOCVD x Al y Ga 1-x-y And N layer as V-shaped pit filling layer. The growth temperature is 900-1000 deg.c and the growth pressure is 100-300 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 And H 2 As carrier gas, TEGa as Ga source, TMIn as In source, TMAL as Al source, and CP 2 Mg is used as a P-type dopant source.
S252: growing a second V-shaped pit opening layer on the V-shaped pit filling layer to obtain a V-shaped pit adjusting layer;
wherein, in one embodiment of the present invention, the plurality of AlGaN layers and the second In are grown periodically by MOCVDAnd a GaN layer as a second V-shaped pit opening layer. Wherein the growth temperature of the AlGaN layer is 850-950 ℃, the growth pressure is 100-300 torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As carrier gas, or in N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMAl was introduced as an Al source. Wherein the growth temperature of the second InGaN layer is 850-950 ℃, the growth pressure is 100-300 torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As carrier gas, or in N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source.
Preferably, in one embodiment of the present invention, the second InGaN layer is grown using N 2 As a carrier gas, the regulation effect on the size of the second V-shaped pit 52a can be enhanced.
S26: growing a second multi-quantum well layer on the V-shaped pit adjusting layer;
specifically, the growth conditions of the second multiple quantum well layer are the same as those of the first multiple quantum well layer, and will not be described herein.
S27: growing an electron blocking layer on the second multi-quantum well layer;
wherein, an AlGaN layer or an InAlGaN layer is grown by MOCVD or MBE and is used as an electron blocking layer. Preferably, in one embodiment of the present invention, al is grown periodically by MOCVD a Ga 1-a N layer and In b Ga 1-b And an N layer serving as an electron blocking layer. Wherein Al is a Ga 1-a The growth temperature of the N layer is 900-1000 ℃, and the growth pressure is 100-500 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 And H 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas. In (In) b Ga 1-b The growth temperature of the N layer is 900-1000 ℃, and the growth pressure is 100-500 torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 And H 2 As a carrier gas, TMIn was introduced as an In source, and TMGa was introduced as a Ga source.
S28: growing a P-type semiconductor layer on the electron blocking layer;
among them, a P-type GaN layer, a P-type AlGaN layer, or a P-type GaAs layer may be grown by MBE, MOCVD, but is not limited thereto. Preferably, in one embodiment of the present invention, the P-type GaN layer is grown by MOCVD at a growth temperature of 800 ℃ to 1000 ℃ and a growth pressure of 100torr to 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, let in CP 2 Mg is used as a P-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
The invention is further illustrated by the following examples:
example 1
Referring to fig. 1 to 3, the present embodiment provides a light emitting diode epitaxial wafer, which includes a substrate 1, a nucleation layer 8, an intrinsic semiconductor layer 9, an N-type semiconductor layer 2, a first V-type pit opening layer 3, a first multiple quantum well layer 4, a V-type pit adjustment layer 5, a second multiple quantum well layer 6, an electron blocking layer 10, and a P-type semiconductor layer 7.
Wherein the substrate 1 is a sapphire substrate. The nucleation layer 8 is an AlN layer having a thickness of 30nm. The intrinsic semiconductor layer 9 is an intrinsic GaN layer having a thickness of 750nm. The N-type semiconductor layer is an N-type GaN layer with a thickness of 2 μm, a doping element of Si, and a doping concentration of 8X10 18 cm -3 。
The first V-shaped pit opening layer 3 is of a periodic structure, the period number is 6, and each period comprises a first InGaN layer and a GaN layer which are sequentially laminated; the thickness of each first InGaN layer was 3nm, and the thickness of each GaN layer was 10nm. The opening size of the first V-shaped pit 3a obtained by opening the first V-shaped pit opening layer 3 is 220nm to 240nm.
The first multi-quantum well layer 4 is of a periodic structure, the period number is 5, and each period comprises an InGaN well layer and a GaN barrier layer which are sequentially stacked; the thickness of the InGaN well layer was 4nm, and the thickness of the GaN barrier layer was 11nm.
Wherein the V-shaped pit adjustment layer 5 comprises a V-shaped pit filling layer 51 and a second V-shaped pit opening layer 52, and the V-shaped pit filling layer 51 is P-In x Al y Ga 1-x-y N layers (x=0.03, y=0.18) with a thickness of 40nm.
The second V-shaped pit opening layer 52 has a periodic structure with a period number of 5, and each period includes an AlGaN layer 521 and a second InGaN layer 522 stacked in this order; each AlGaN layer 521 has a thickness of 13nm and each second InGaN layer 522 has a thickness of 2nm. The Al composition ratio In the AlGaN layer 521 is 0.11, and the In composition ratio In the second InGaN layer 522 is 0.08. The opening size of the second V-shaped pit 52a obtained by opening the second V-shaped pit opening layer 52 is 90nm to 115nm.
The second multi-quantum well layer 6 is of a periodic structure, the period number is 5, and each period comprises an InGaN well layer and a GaN barrier layer which are sequentially stacked; the thickness of the InGaN well layer was 4nm, and the thickness of the GaN barrier layer was 11nm.
Wherein the electron blocking layer 10 is Al a Ga 1-a N layers (a=0.12) and In b Ga 1-b Periodic structure with N layers (b=0.3) alternately grown, with a period of 8, single Al a Ga 1-a The thickness of the N layer is 6nm, single In b Ga 1-b The thickness of the N layer was 6nm.
Wherein the P-type semiconductor layer is a P-type GaN layer, the doping element is Mg, and the doping concentration is 5×10 19 cm -3 The thickness was 250nm.
The preparation method of the light-emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) Providing a substrate; the substrate was loaded into MOCVD and annealed at 1120℃under a 400torr atmosphere of hydrogen for 6min.
(2) Growing a nucleation layer on the substrate;
specifically, PVD is used to grow an AlN layer.
(3) Growing an intrinsic semiconductor layer on the nucleation layer;
specifically, an intrinsic GaN layer is grown as an intrinsic semiconductor layer using MOCVD. The growth temperature is 1120 ℃, the growth pressure is 250torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As an N source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
(4) Growing an N-type semiconductor layer on the intrinsic semiconductor layer;
specifically, an N-type GaN layer is grown as an N-type semiconductor layer using MOCVD. The growth temperature is 1140 ℃, and the growth pressure is 200torr; during growthIntroducing NH into MOCVD reaction chamber 3 As N source, siH is introduced 4 As an N-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
(5) Growing a first V-shaped pit opening layer on the N-type semiconductor layer;
specifically, a plurality of first InGaN layers and GaN layers were periodically grown by MOCVD as first V-pit opening layers. Wherein the growth temperature of the GaN layer is 850 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As carrier gas, TEGa was introduced as a Ga source. Wherein the growth temperature of the first InGaN layer is 770 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source.
(6) Growing a first multiple quantum well layer on the first V-shaped pit opening layer;
wherein the InGaN well layer and the GaN barrier layer are periodically grown in MOCVD to form a first multi-quantum well layer. Wherein the growth temperature of InGaN well layer is 750 ℃, the growth pressure is 300torr, and NH is introduced into MOCVD reaction chamber during growth 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source. Wherein, the growth temperature of the GaN barrier layer is 850 ℃, the growth pressure is 300torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As carrier gas, TEGa was introduced as a Ga source.
(7) Growing a V-shaped pit filling layer on the first multi-quantum well layer;
wherein P-In is grown by MOCVD x Al y Ga 1-x-y And N layer as V-shaped pit filling layer. The growth temperature is 920 ℃, and the growth pressure is 250torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 And H 2 As carrier gas, TEGa as Ga source, TMIn as In source, TMAL as Al source, and CP 2 Mg is used as a P-type dopant source.
(8) Growing a second V-shaped pit opening layer on the V-shaped pit filling layer;
specifically, a plurality of AlGaN layers and a second InGaN layer are periodically grown by MOCVD as a second V-shaped pit opening layer. Wherein, the growth temperature of AlGaN layer is 920 ℃, the growth pressure is 200torr, and NH is introduced into MOCVD reaction chamber during growth 3 As N source, with H 2 And N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMAl was introduced as an Al source. Wherein the growth temperature of the second InGaN layer is 860 ℃, the growth pressure is 200torr, and NH is introduced into the MOCVD reaction chamber during growth 3 As N source, with N 2 As a carrier gas, TEGa was introduced as a Ga source, and TMIn was introduced as an In source.
(9) Growing a second multiple quantum well layer on the second V-shaped pit opening layer;
the specific growth conditions are the same as those of the first multiple quantum well layer.
(10) Growing an electron blocking layer on the second multi-quantum well layer;
specifically, periodically growing Al in MOCVD a Ga 1-a N layer and In b Ga 1-b And an N layer serving as an electron blocking layer. Wherein Al is a Ga 1-a The growth temperature of the N layer is 950 ℃ and the growth pressure is 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 And H 2 TMAl was introduced as an Al source and TMGa was introduced as a Ga source as a carrier gas. In (In) b Ga 1-b The growth temperature of the N layer is 950 ℃ and the growth pressure is 300torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, with N 2 And H 2 As a carrier gas, TMIn was introduced as an In source, and TMGa was introduced as a Ga source.
(11) Growing a P-type semiconductor layer on the electron blocking layer;
specifically, a P-GaN layer is grown in MOCVD as a P-type semiconductor layer. The growth temperature is 900 ℃ and the growth pressure is 200torr. During growth, NH is introduced into the MOCVD reaction chamber 3 As N source, let in CP 2 Mg is used as a P-type doping source; by H 2 And N 2 As a carrier gas, TMGa was introduced as a Ga source.
Example 2
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that:
the number of cycles of the first multi-quantum well layer 4 is 6, and the number of cycles of the second multi-quantum well layer 6 is 4.
The remainder was the same as in example 1.
Example 3
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 2 in that:
the number of cycles of the first V-shaped pit opening layer 3 was 8, and the opening size of the first V-shaped pit 3a obtained by opening was 260nm to 285nm.
The V-shaped pit filling layer 51 is P-In x Al y Ga 1-x-y N layers (x=0.07, y=0.22).
The remainder was the same as in example 2.
Comparative example 1
This comparative example provides a light emitting diode epitaxial wafer which is different from example 1 in that V-shaped pit adjustment layer 5 is not included, and accordingly, the step of preparing this layer is not included in the manufacturing method, and the remainder is the same as example 1.
Comparative example 2
This comparative example provides a light emitting diode epitaxial wafer which is different from that of example 1 in that the V-shaped pit filling layer 51 is not included, and accordingly, the step of preparing the layer is not included in the manufacturing method, and the remainder is the same as that of example 1.
Comparative example 3
This comparative example provides a light emitting diode epitaxial wafer which is different from example 1 in that the second V-shaped pit opening layer 52 is not included, and accordingly, the step of preparing the layer is not included in the manufacturing method, and the remainder is the same as example 1.
Comparative example 4
This comparative example provides a light emitting diode epitaxial wafer which is different from example 1 in that the first V-shaped pit opening layer 3 is not included, and accordingly, the step of preparing the layer is not included in the manufacturing method, and the remainder is the same as example 1.
Comparative example 5
The present comparative example provides a light emitting diode epitaxial wafer, which is different from example 1 in that the first V-shaped pit opening layer has the same structure as the second V-shaped pit opening layer, and accordingly, the preparation method of the first V-shaped pit opening layer and the preparation method of the second V-shaped pit opening layer are also the same in the present comparative example.
In this comparative example, the opening size of the first V-shaped pit obtained by opening the first V-shaped pit opening layer is 100nm to 120nm.
Comparative example 6
The present comparative example provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that the number of cycles of the first multiple quantum well layer 4 is 4 and the number of cycles of the second multiple quantum well layer 6 is 6. The remainder was the same as in example 1.
The light emitting diode epitaxial wafers of examples 1 to 3 and comparative examples 1 to 6 were measured as follows:
(1) Measuring the surface roughness of the light-emitting diode epitaxial wafer by adopting AFM equipment;
(2) Processing a light-emitting diode epitaxial wafer into a 10×24mil LED chip with a vertical structure, and testing the luminous intensity of the obtained chip when current of 120mA is introduced;
(3) The LED epitaxial wafer is processed into an LED chip with a vertical structure of 10 multiplied by 24mil, the antistatic performance of the chip is tested by using an electrostatic instrument under an HBM (human body discharge model) model, and the tested chip can bear the passing proportion of reverse 8000V static electricity.
The specific test results are shown in the following table:
as can be seen from the table, after the V-shaped pit (comparative example 1) in the conventional light-emitting diode epitaxial wafer is changed to the composite V-shaped pit of the present application, the surface roughness of the light-emitting diode epitaxial wafer is reduced from 0.265nm to 0.214nm, the brightness is increased from 190.3mW to 195.8mW, and the antistatic capability is increased from 86.3% to 95.1%, which indicates that the composite V-shaped pit of the present invention can increase the brightness and the antistatic capability.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.
Claims (10)
1. The light-emitting diode epitaxial wafer is characterized by comprising a substrate, an N-type semiconductor layer, a first V-shaped pit opening layer, a first multi-quantum well layer, a V-shaped pit adjusting layer, a second multi-quantum well layer and a P-type semiconductor layer which are sequentially laminated on the substrate;
the cycle number of the first multi-quantum well layer is more than or equal to the cycle number of the second multi-quantum well layer;
the V-shaped pit adjusting layer comprises a V-shaped pit filling layer and a second V-shaped pit opening layer; the first V-shaped pit opening layer is opened to obtain a first V-shaped pit, the V-shaped pit filling layer is used for filling the first V-shaped pit, and the second V-shaped pit opening layer is opened to obtain a second V-shaped pit;
the opening size of the second V-shaped pit is smaller than the opening size of the first V-shaped pit.
2. The light-emitting diode epitaxial wafer of claim 1, wherein the number of cycles of the first multi-quantum well layer is 1-3 more than the number of cycles of the second multi-quantum well layer;
the opening size of the first V-shaped pit is 150nm-300nm, and the opening size of the second V-shaped pit is 10nm-150nm.
3. The light-emitting diode epitaxial wafer of claim 1, wherein the first V-shaped pit opening layer has a periodic structure with a period number of 2-10, and each period comprises a first InGaN layer and a GaN layer which are sequentially stacked; the thickness of each first InGaN layer is 2nm-6nm, and the thickness of each GaN layer is 8nm-15nm.
4. The light-emitting diode epitaxial wafer of claim 1, wherein the V-shaped pit filling layer is P-In x Al y Ga 1-x-y An N layer of the silicon nitride film,x is 0.01-0.1, y is 0.1-0.3, and the thickness is 10nm-50nm.
5. The light-emitting diode epitaxial wafer of claim 1, wherein the V-shaped pit filling layer is P-In x Al y Ga 1-x-y An N layer, wherein x is 0.05-0.1, and y is 0.2-0.3;
the opening size of the first V-shaped pit is 250nm-350nm.
6. The light-emitting diode epitaxial wafer of claim 1, wherein the second V-shaped pit opening layer has a periodic structure, the period number is 2-10, and each period comprises an AlGaN layer and a second InGaN layer which are sequentially stacked; the thickness of each AlGaN layer is 5nm-15nm, and the thickness of each second InGaN layer is 1nm-3nm;
the Al component In the AlGaN layer accounts for 0.05-0.15, and the In component In the second InGaN layer accounts for 0.02-0.1.
7. The light-emitting diode epitaxial wafer of any one of claims 1-6, further comprising a nucleation layer, an intrinsic semiconductor layer, and an electron blocking layer;
the nucleation layer and the intrinsic semiconductor layer are sequentially laminated between the substrate and the N-type semiconductor layer, and the electron blocking layer is arranged between the second multi-quantum well layer and the P-type semiconductor layer;
the intrinsic semiconductor layer is an intrinsic GaN layer, the N-type semiconductor layer is an N-type GaN layer, and the P-type semiconductor layer is a P-type GaN layer;
the first multi-quantum well layer and the second multi-quantum well layer are periodic structures formed by alternately stacking InGaN well layers and GaN barrier layers.
8. A method for preparing a light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer according to any one of claims 1 to 7, and is characterized by comprising:
providing a substrate, and sequentially forming an N-type semiconductor layer, a first V-shaped pit opening layer, a first multi-quantum well layer, a V-shaped pit adjusting layer, a second multi-quantum well layer and a P-type semiconductor layer on the substrate;
the cycle number of the first multi-quantum well layer is more than or equal to the cycle number of the second multi-quantum well layer;
the V-shaped pit adjusting layer comprises a V-shaped pit filling layer and a second V-shaped pit opening layer; the first V-shaped pit opening layer is opened to obtain a first V-shaped pit, the V-shaped pit filling layer is used for filling the first V-shaped pit, and the second V-shaped pit opening layer is opened to obtain a second V-shaped pit;
the opening size of the second V-shaped pit is smaller than the opening size of the first V-shaped pit.
9. The method for manufacturing a light-emitting diode epitaxial wafer according to claim 8, wherein,
the growth temperature of the first V-shaped pit opening layer is 700-900 ℃, and the growth pressure is 100-500 torr;
the growth temperature of the V-shaped pit filling layer is 900-1000 ℃ and the growth pressure is 100-300 torr;
the growth temperature of the second V-shaped pit opening layer is 850-950 ℃ and the growth pressure is 100-300 torr.
10. A light emitting diode comprising the light emitting diode epitaxial wafer according to any one of claims 1 to 7.
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| CN116799118B (en) * | 2023-08-22 | 2023-11-03 | 江西兆驰半导体有限公司 | LED epitaxial wafer, preparation method thereof and LED |
| CN116825918A (en) * | 2023-08-31 | 2023-09-29 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer and preparation method thereof |
| CN116825918B (en) * | 2023-08-31 | 2023-11-17 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer and preparation method thereof |
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