CN116825918A - Light-emitting diode epitaxial wafer and preparation method thereof - Google Patents
Light-emitting diode epitaxial wafer and preparation method thereof Download PDFInfo
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Abstract
The application discloses a light-emitting diode epitaxial wafer and a preparation method thereof, and relates to the field of semiconductor photoelectric devices. The light-emitting diode epitaxial wafer sequentially comprises a substrate, a buffer layer, an undoped GaN layer, an N-type GaN layer, a first stress buffer layer, a second stress buffer layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer; the first stress buffer layer is a periodic structure formed by alternately stacking first potential well layers and first barrier layers; the first potential well layer is In x Ga 1‑x An N layer, a first barrier layer of B y Ga 1‑y A periodic structure formed by alternately stacking N layers and GaN layers; the second stress buffer layer is a periodic structure formed by alternately stacking a second potential well layer and a second barrier layer; the second potential well layer is In z Ga 1‑z An N layer, a second barrier layer of B w Ga 1‑w N layer and Si dopingThe GaN layers are alternately laminated to form a periodic structure. By implementing the application, the luminous efficiency and antistatic performance of the light-emitting diode can be improved.
Description
Technical Field
The application relates to the field of semiconductor photoelectric devices, in particular to a light-emitting diode epitaxial wafer and a preparation method thereof.
Background
The V-shaped pit technology is a novel technology in the field of light emitting diodes, and mainly comprises the steps of introducing a stress buffer layer (InGaN-GaN superlattice) between an N-type layer and a multiple quantum well layer, forming a V-shaped pit through a defect area of the stress buffer layer, enabling holes in a P-type layer to enter a deeper multiple quantum well region through the side wall of the V-shaped pit, optimizing the distribution density of electrons and holes in the whole multiple quantum well region, and improving the luminous efficiency.
However, such conventional stress buffers have several problems: (1) In order to increase the density of V-pits, a method of reducing the growth temperature of the stress buffer layer is generally employed. However, too low a growth temperature results in poor lattice quality of the stress buffer layer, and many defects are generated, which may extend to the multiple quantum well region, so that the crystal quality of the multiple quantum well layer is deteriorated, non-radiative recombination is increased, and instead, light emission efficiency is reduced. (2) The V-shaped pits (especially small-size V-shaped pits) can increase leakage channels, form concentrated release channels when static electricity is loaded on the LED chip, further form local large current, break down devices and reduce antistatic performance. (3) The V-shaped pit allows holes to enter a deeper multiple quantum well region through the side wall of the V-shaped pit, which means that holes may be injected into the stress buffer layer through the side wall of the V-shaped pit to form non-radiative recombination, thereby reducing the luminous efficiency, especially the luminous efficiency under high current density, i.e. the quantum efficiency attenuation effect is high.
Disclosure of Invention
The application aims to solve the technical problem of providing a light-emitting diode epitaxial wafer and a preparation method thereof, which can improve the light-emitting efficiency and antistatic performance of a light-emitting diode.
In order to solve the problems, the application discloses a light-emitting diode epitaxial wafer, which comprises a substrate, a buffer layer, an undoped GaN layer, an N-type GaN layer, a first stress buffer layer, a second stress buffer layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer, wherein the buffer layer, the undoped GaN layer, the N-type GaN layer, the first stress buffer layer, the second stress buffer layer, the multiple quantum well layer, the electron blocking layer and the P-type GaN layer are sequentially laminated on the substrate;
the first stress buffer layer is of a periodic structure, and each period comprises a first potential well layer and a first potential barrier layer which are sequentially stacked; the first potential well layer is In x Ga 1-x An N layer, the first barrier layer is B y Ga 1-y A periodic structure formed by alternately stacking N layers and GaN layers;
the second stress buffer layer is of a periodic structure, and each period comprises a second potential well layer and a second barrier layer which are sequentially stacked; the second potential well layer is In z Ga 1-z An N layer, the second barrier layer is B w Ga 1-w And the N layer and the Si doped GaN layer are alternately laminated to form a periodic structure.
As an improvement of the technical scheme, the cycle number of the first stress buffer layer is 5-20, and the cycle number of the second stress buffer layer is 1-5.
As an improvement of the technical scheme, x is 0.01-0.1, z is 0.05-0.2, and x is less than z;
the thickness of the first potential well layer is 1.5-3 nm, the thickness of the second potential well layer is 2-5 nm, and the thickness of the first potential well layer is smaller than the thickness of the second potential well layer.
As an improvement of the technical scheme, y is 0.03-0.1, w is 0-0.05, and y is more than w.
As an improvement of the technical scheme, the period number of the first barrier layer is 2-5, each B y Ga 1-y The thickness of the N layer is 0.5-2 nm, and the thickness of each GaN layer is 1-2 nm.
As an improvement of the technical scheme, the period number of the second barrier layer is 1-3, each B w Ga 1-w The thickness of the N layer is 0.3 nm-3.5 nm, and each Si is doped with GaThe thickness of the N layer is 4 nm-8 nm;
the doping concentration of Si in the Si-doped GaN layer is 5×10 16 cm -3 ~5×10 17 cm -3 。
As an improvement of the above technical scheme, the thickness of the Si-doped GaN layer exhibits increasing variation with increasing cycle number of the second stress buffer layer, the B w Ga 1-w The thickness of the N layers is progressively varied.
As an improvement of the above technical scheme, the Si doping concentration in the Si-doped GaN layer presents increasing variation with increasing cycle number of the second stress buffer layer, the B w Ga 1-w The B component duty ratio in the N layer is changed in a decreasing way.
Correspondingly, the application also discloses a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps:
providing a substrate, and sequentially growing a buffer layer, an undoped GaN layer, an N-type GaN layer, a first stress buffer layer, a second stress buffer layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer on the substrate;
the first stress buffer layer is of a periodic structure, and each period comprises a first potential well layer and a first potential barrier layer which are sequentially stacked; the first potential well layer is In x Ga 1-x An N layer, the first barrier layer is B y Ga 1-y A periodic structure formed by alternately stacking N layers and GaN layers;
the second stress buffer layer is of a periodic structure, and each period comprises a second potential well layer and a second barrier layer which are sequentially stacked; the second potential well layer is In z Ga 1-z An N layer, the second barrier layer is B w Ga 1-w A periodic structure formed by alternately stacking N layers and Si-doped GaN layers;
the growth temperature of the first stress buffer layer is less than the growth temperature of the second stress buffer layer.
As an improvement of the technical scheme, the growth temperature of the first potential well layer is 700-760 ℃, and the growth pressure is 100-500 torr;
the growth temperature of the first barrier layer is 750-820 ℃, and the growth pressure is 100-500 torr;
the growth temperature of the second potential well layer is 750-840 ℃, and the growth pressure is 100-500 torr;
the growth temperature of the second barrier layer is 780-900 ℃, and the growth pressure is 100-500 torr.
The implementation of the application has the following beneficial effects:
1. in the light-emitting diode epitaxial wafer, a first stress buffer layer and a second stress buffer layer are sequentially arranged between an N-type GaN layer and a multiple quantum well layer. The first stress buffer layer is a periodic structure formed by the first potential well layer and the first barrier layer, and the second stress buffer layer is a periodic structure formed by the second potential well layer and the second barrier layer. The first barrier layer is B y Ga 1-y The N layer and the GaN layer are alternately laminated to form a periodic structure, and the second barrier layer is B w Ga 1-w And the N layer and the Si doped GaN layer are alternately laminated to form a periodic structure. One, B is formed by the first barrier layer and the second barrier layer y Ga 1-y The N layer forms compressive stress on the GaN layer, B w Ga 1-w The N layer forms compressive stress on the Si doped GaN layer, so that the surface energy of the GaN layer and the surface energy of the Si doped GaN layer are reduced, the diffusion rate of Ga atoms is increased, the size of the V-shaped pit is effectively improved, the duty ratio of the small-size V-shaped pit is reduced, the channels for concentrated current release are reduced, and the antistatic performance is improved. And meanwhile, the larger size is beneficial to promoting the uniform distribution of holes, and the luminous efficiency is improved. Both of which are introduced with a first barrier layer B y Ga 1-y B introduced by N layer and second barrier layer w Ga 1-w The N layer has a small lattice constant and is equal to In x Ga 1-x N layer (first potential well layer), in z Ga 1-z The lattice difference of the N layer (the second potential well layer) is large, and a plurality of dislocation are formed, so that the V-shaped pit size is further enlarged. At the same time B y Ga 1-y N layer, B w Ga 1-w The barrier of the N layer is high, so that holes can be effectively blocked from entering the stress buffer layer through the V-shaped pit, electrons are more prone to be injected into the multi-quantum well layer through the platform instead of the side wall of the V-shaped pit, and the antistatic performance is improvedAnd the density of carriers in the multi-quantum well layer is improved, the energy band filling effect under large current is enhanced, and the Efficiency droop effect is weakened. The third layer adopts a Si doped GaN layer and B at a second barrier layer of a second stress buffer layer close to the multi-quantum well layer w Ga 1-w The N layer can jointly block the holes overflowing to the second buffer layer through the holes, so that non-radiative recombination is prevented, and the luminous efficiency of the light-emitting diode epitaxial wafer is improved; in addition, the forward voltage of the light-emitting diode epitaxial wafer is not obviously increased when Si is doped at the position.
2. In the light-emitting diode epitaxial wafer, the Si doped GaN layer with high temperature growth and large thickness is adopted in the second stress buffer layer of the adjacent multiple quantum well layer, so that the combination of small-size V-shaped pits can be promoted, only the V-shaped pits with larger size are left, and the antistatic performance and the luminous efficiency are further optimized.
3. In the light-emitting diode epitaxial wafer, in with relatively high In component is adopted In the second stress buffer layer of the adjacent multiple quantum well layer z Ga 1-z The N layer can effectively improve the quality of the subsequent multiple quantum well layers, weaken the intensity of a polarized electric field in the multiple quantum well layers, improve the superposition of electron hole wave functions and improve the luminous efficiency.
Drawings
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a first barrier layer according to an embodiment of the application;
FIG. 3 is a schematic diagram of a second barrier layer according to an embodiment of the application;
fig. 4 is a flowchart of a method for manufacturing an led epitaxial wafer according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail below in order to make the objects, technical solutions and advantages of the present application more apparent.
Referring to fig. 1-3, the application discloses a light emitting diode epitaxial wafer, which comprises a substrate 100, a buffer layer 200, an undoped GaN layer 300 and an N-type GaN layer sequentially stacked on the substrate 100400. A first stress buffer layer 500, a second stress buffer layer 600, a multiple quantum well layer 700, an electron blocking layer 800, and a P-type GaN layer 900. The first stress buffer layer 500 is a periodic structure, and each period includes a first potential well layer 510 and a first barrier layer 520 that are sequentially stacked; the first potential well layer 510 is In x Ga 1-x N layers, the first barrier layer 520 being B y Ga 1-y A periodic structure in which N layers 521 and GaN layers 522 are alternately stacked; the second stress buffer layer 600 is a periodic structure, and each period includes a second potential well layer 610 and a second barrier layer 620 stacked in sequence; the second well layer 610 is In z Ga 1-z N layer, second barrier layer 620 is B w Ga 1-w The N layer 621 and the Si-doped GaN layer 622 are alternately stacked to form a periodic structure.
The number of cycles of the first stress buffer layer 500 is 5-30, and when the number of cycles is less than 5, the density of the V-shaped pits is too low, the size of the opening is too small, so that it is difficult to effectively improve the light emitting efficiency, and the working voltage is also higher. When the cycle number is more than 30, the duty ratio of the small-size V-shaped pit is too high, which is unfavorable for improving the antistatic performance. The number of cycles of the first stress buffer 500 is, but not limited to, 8, 12, 16, 20, 24, or 28. Preferably 5 to 20.
The thickness of the first well layer 510 is 1 nm-3 nm, and the first well layer with the thickness range is favorable for maintaining the working voltage of the light emitting diode in a reasonable range. The thickness of the first well layer 510 is, but not limited to, 1.4nm, 1.8nm, 2.2nm, or 2.6nm, for example. Preferably 1.5nm to 3nm.
First potential well layer 510 (In x Ga 1-x N layer) is 0.01 to 0.12 (i.e., x), the first well layer 510 with a lower In composition can better buffer stress. Illustratively, x is 0.02, 0.04, 0.06, 0.08, or 0.1, but is not limited thereto. Preferably 0.01 to 0.1, more preferably 0.01 to 0.06.
The number of cycles of the first barrier layer 520 is 2-10, and when the number of cycles is less than 2, it is difficult to effectively increase the size of the V-shaped pit; when the cycle number is more than 10, the potential barrier is too high, even electrons enter the multi-quantum well layer, and the luminous efficiency is reduced. The number of periods of the first barrier layer 520 is, but not limited to, 3, 5, 7, or 9, for example. Preferably 2 to 5.
Wherein B is y Ga 1-y The B component in the N layer 521 has a duty ratio (i.e., y) of 0.02 to 0.12, and when y is less than 0.02, the lattice difference between the B component and the GaN layer or the first well layer is small, so that it is difficult to effectively increase the size of the V-shaped pit. When y is more than 0.12, the surface roughness is high, so that the lattice quality of the multi-quantum well layer is deteriorated, and the luminous efficiency is reduced. Illustratively, y is 0.04, 0.06, 0.08, or 0.1, but is not so limited. Preferably, y is 0.03 to 0.1.
B y Ga 1-y The thickness of the N layer 521 is 0.5nm to 3nm, and exemplary is 0.8nm, 1.2nm, 1.6nm, 2nm, 2.4nm, or 2.8nm, but is not limited thereto. Preferably 0.5nm to 2nm.
The thickness of the GaN layer 522 is 1nm to 2.5nm, and when the thickness is more than 2.5nm, the stress is relaxed, so that the size of the V-shaped pit is difficult to be increased. The GaN layer 522 is illustratively, but not limited to, 1.3nm, 1.6nm, 1.9nm, or 2.2nm thick. Preferably, the thickness of the GaN layer 522 is 1nm to 2nm.
The number of cycles of the second stress buffer layer 600 is 1-8, and when the number of cycles is greater than 8, the working voltage is greatly increased. Specifically, since the second stress buffer layer 600 has a high In composition ratio, the second barrier layer has a larger thickness, which makes it difficult for electrons to enter the multi-quantum well layer through the second stress buffer layer In a tunneling diffusion manner, thereby increasing the operating voltage. The number of cycles of the second stress buffer 600 is, but not limited to, 2, 3, 4, 5, or 6. Preferably 1 to 5.
The second well layer 610 has a thickness of 2nm to 6nm, and is exemplified by, but not limited to, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm, 5nm, or 5.5 nm. Preferably 2nm to 5nm.
Preferably, in one embodiment of the present application, the thickness of the second well layer 610 > the thickness of the first well layer 510.
A second potential well layer 610 (In z Ga 1-z N layer) is 0.05-0.22 (i.e., z), the higher In component can not only effectively improve the size of the V-shaped pit, but also improve the crystal quality of the multi-quantum well layer. Showing theIllustratively, z is 0.06, 0.09, 0.12, 0.15, or 0.18, but is not limited thereto. Preferably 0.05 to 0.2.
Preferably, in one embodiment of the application, x < z.
The number of periods of the second barrier layer 620 is 1 to 4, and is exemplified by 2, 3 or 4, but not limited thereto. Preferably 1 to 3.
Wherein B is w Ga 1-w The B component in the N layer 621 has a ratio (i.e., w) of 0to 0.07, and when w > 0.07, it is unfavorable for the Si-doped GaN layer 622 to fill up small-sized V-shaped pits. Illustratively, w is 0.01, 0.02, 0.03, or 0.04. Preferably 0to 0.05, more preferably 0.01 to 0.03.
B w Ga 1-w The thickness of the N layer 621 is 0.1nm to 4nm, and exemplary is 0.3nm, 0.7nm, 1.2nm, 1.6nm, 2nm, 2.4nm, 2.8nm, 3.2nm, or 3.7nm, but is not limited thereto. Preferably 0.3nm to 3.5nm.
Wherein the Si doping concentration in the Si-doped GaN layer 622 is 1×10 16 cm -3 ~1×10 18 cm -3 By introducing Si doping, one can enhance the blocking effect on holes injected via the V-shaped pits, preventing them from entering the first stress buffer layer, the second stress buffer layer; and the Si is doped at the position close to the multi-quantum well layer, so that a conduction band close to the multi-quantum well is bent downwards, a barrier to electrons is weakened, and the working voltage is reduced. Exemplary, the Si doping concentration in the Si-doped GaN layer 622 is 3×10 16 cm -3 、6×10 16 cm -3 、9×10 16 cm -3 、2×10 17 cm -3 、5×10 17 cm -3 Or 8X 10 17 cm -3 But is not limited thereto. Preferably 5X 10 16 cm -3 ~5×10 17 cm -3 。
The thickness of the Si doped GaN layer 622 is 3nm to 10nm, and is exemplified by, but not limited to, 4nm, 6nm, 8nm, or 9 nm. Preferably 4nm to 8nm.
Preferably, in one embodiment of the present application, the thickness of the Si-doped GaN layer 622 exhibits an increasing variation, B, with increasing number of 600 cycles of the second stress buffer layer w Ga 1-w The thickness of the N layer 621 is progressively reduced。
Preferably, in another embodiment of the present application, the Si doping concentration of the Si-doped GaN layer 622 exhibits an increasing change, B, with increasing number of 600 cycles of the second stress buffer layer w Ga 1-w The thickness of the N layer 621 is changed in a decreasing manner.
Based on the structure of the application, the average size of the V-shaped pits can be controlled to be 120-170 nm, and the density of the large V-shaped pits (more than 160 nm) can be controlled to be 4 multiplied by 10 8 cm -2 ~4.5×10 8 cm -2 The density of the small V-shaped pit (< 80 nm) is controlled to be 2.8X10 8 cm -2 ~3.2×10 8 cm -2 (conventionally at 5X 10) 8 cm -2 Above), thereby effectively improving the luminous efficiency and antistatic performance and weakening the efficiency-droop effect.
Among them, the substrate 100 is a sapphire substrate, a gallium oxide substrate, a zinc oxide substrate, or a carbonized substrate, but is not limited thereto.
The buffer layer 200 is an AlN layer or an AlGaN layer, but is not limited thereto. An AlN layer is preferred. The thickness of the buffer layer 200 is 20nm to 80nm. The thickness of the undoped GaN layer 300 is 1 μm to 3 μm.
The N-type doping element of the N-type GaN layer 400 is Si or Ge, but is not limited thereto. The N-type doping concentration of the N-type GaN layer 400 is 5×10 18 cm -3 ~5×10 19 cm -3 The thickness is 1 μm to 3 μm.
The multiple quantum well layer 700 is an InGaN quantum well layer and a GaN quantum barrier layer stacked alternately, and the stacking period is 3-15. The thickness of the single InGaN quantum well layer is 3 nm-5 nm, and the in component ratio is 0.15-0.25. The thickness of the single GaN quantum barrier layer is 5 nm-15 nm.
The electron blocking layer 800 is an AlGaN layer or an InAlGaN layer, but is not limited thereto. Preferably, the Mg-doped AlGaN layer has an Al component ratio of 0.2-0.3. Mg doping concentration of 1×10 17 cm -3 ~1×10 19 cm -3 The thickness is 30 nm-100 nm.
The P-type doping element in the P-type GaN layer 900 is Mg, be, or Zn, but is not limited thereto. Mg is preferred. The P-type doping concentration in the P-type GaN layer 900 is 1×10 19 cm -3 ~1×10 21 cm -3 . The thickness of the P-type GaN layer 900 is 20 nm-50 nm.
Correspondingly, referring to fig. 4, the application also provides a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and specifically comprises the following steps:
s1: providing a substrate;
s2: growing a buffer layer on a substrate;
wherein the buffer layer may be grown by PVD, MOCVD, MBE or VPE, but is not limited thereto.
Preferably, in one embodiment of the present application, the AlN layer is grown by PVD as a buffer layer.
S3: growing an undoped GaN layer on the buffer layer;
wherein the undoped GaN layer may be grown through PVD, MOCVD, MBE or VPE, but is not limited thereto.
Preferably, in one embodiment of the present application, the undoped GaN layer is grown by MOCVD. The growth temperature is 1100-1150 ℃ and the growth pressure is 100-500 torr.
S4: growing an N-type GaN layer on the undoped GaN layer;
among them, the N-type GaN layer may be grown by MOCVD, MBE, or VPE, but is not limited thereto.
Preferably, in one embodiment of the present application, the N-type GaN layer is grown by MOCVD at a growth temperature of 1100 ℃ to 1150 ℃ and a growth pressure of 100torr to 500torr.
S5: growing a first stress buffer layer on the N-type GaN layer;
specifically, a first potential well layer and a first barrier layer are periodically grown on the N-type GaN layer until a first stress buffer layer is obtained.
Wherein, in one embodiment of the application, in is grown by MOCVD x Ga 1-x And an N layer serving as a first potential well layer. The growth temperature of the first potential well layer is 700-760 ℃, and the growth pressure is 100-500 torr;
wherein, in one embodiment of the application, B is grown periodically by MOCVD y Ga 1-y An N layer and a GaN layer untilTo the first barrier layer. The growth temperature of the first barrier layer is 750-820 ℃, and the growth pressure is 100-500 torr.
S6: growing a second stress buffer layer on the first stress buffer layer;
specifically, a second potential well layer and a second barrier layer are periodically grown on the first stress buffer layer until the second stress buffer layer is obtained.
Wherein, in one embodiment of the application, in is grown by MOCVD z Ga 1-z And an N layer serving as a second potential well layer. The growth temperature of the second potential well layer is 750-840 ℃, and the growth pressure is 100-500 torr.
Wherein, in one embodiment of the application, B is grown periodically by MOCVD w Ga 1-w And doping the N layer and the Si layer with the GaN layer until a second barrier layer is obtained. The growth temperature of the second barrier layer is 780-900 ℃, and the growth pressure is 100-500 torr.
And controlling the growth temperature of the first stress buffer layer to be less than the growth temperature of the second stress buffer layer. The crystal quality of the second stress buffer layer can be effectively improved.
S7: growing a multi-quantum well layer on the second stress buffer layer;
wherein, in one embodiment of the application, the InGaN quantum well layer and the GaN quantum barrier layer are periodically grown on the second stress buffer layer by MOCVD until a multi-quantum well layer is obtained. The growth temperature of the InGaN quantum well layer is 700-800 ℃, and the growth pressure is 100-300 torr. The growth temperature of the GaN quantum barrier layer is 850-900 ℃, and the growth pressure is 100-300 torr.
S8: growing an electron blocking layer on the multiple quantum well layer;
among them, the electron blocking layer may be grown by MOCVD, MBE, or VPE, but is not limited thereto.
Preferably, in one embodiment of the present application, the Mg doped AlGaN layer is grown by MOCVD, and the growth temperature is 1000 ℃ to 1100 ℃ and the growth pressure is 100torr to 300torr as the electron blocking layer.
S9: growing a P-type GaN layer on the electron blocking layer;
among them, the P-type GaN layer may be grown by MOCVD, MBE, or VPE, but is not limited thereto.
Preferably, in one embodiment of the present application, the P-type GaN layer is grown by MOCVD at a growth temperature of 900 ℃ to 1000 ℃ and a growth pressure of 100torr to 300torr.
The application is further illustrated by the following examples:
example 1
Referring to fig. 1 to 3, the present embodiment provides a light emitting diode epitaxial wafer, which includes a substrate 100, a buffer layer 200, an undoped GaN layer 300, an N-type GaN layer 400, a first stress buffer layer 500, a second stress buffer layer 600, a multiple quantum well layer 700, an electron blocking layer 800 and a P-type GaN layer 900 sequentially stacked on the substrate 100.
The substrate 100 is a sapphire substrate, and the buffer layer 200 is an AlN layer with a thickness of 40nm. The thickness of the undoped GaN layer 300 was 1.6 μm. The doping element of the N-type GaN layer 400 is Si, and the doping concentration is 3×10 19 cm -3 The thickness thereof was 2.5. Mu.m.
The first stress buffer layer 500 has a periodic structure, and the number of periods is 15. Each cycle includes a first potential well layer 510 and a first barrier layer 520 stacked in order; the first potential well layer 510 is In x Ga 1-x N layers (x=0.11) with a thickness of 1.2nm; the first barrier layer 520 is B y Ga 1-y A periodic structure in which N layers 521 (y=0.06) and GaN layers 522 are alternately stacked, the number of periods being 4; b (B) y Ga 1-y The thickness of the N layer 521 was 2.5nm, and the thickness of the GaN layer was 2.5nm.
The second stress buffer layer 600 has a periodic structure, and the period number is 4, and each period includes a second potential well layer 610 and a second barrier layer 620 stacked in sequence; the second well layer 610 is In z Ga 1-z N layer (z=0.17) with a thickness of 3nm and a second barrier layer 620 of B w Ga 1-w N layer 621 (w=0.06) and Si-doped GaN layer 622 are alternately laminated to form a periodic structure with a period of 2, b w Ga 1-w The thickness of the N layer 621 was 4nm and was maintained constant, the thickness of the Si-doped GaN layer 622 was 3.5nm and was maintained constant, and the Si doping concentration in the Si-doped GaN layer 622 was 8×10 17 cm -3 And remain constant.
The multiple quantum well layer 700 is of a periodic structure, the period number is 10, each period comprises an InGaN quantum well layer and a GaN quantum barrier layer which are sequentially stacked, the In component In the InGaN quantum well layer is 0.22, the thickness is 3nm, and the thickness of the GaN quantum barrier layer is 10nm.
Wherein the electron blocking layer 800 is an Mg-doped AlGaN layer with an Al component ratio of 0.2 and an Mg doping concentration of 4X10 17 cm -3 The thickness was 50nm. The doping element of the P-type GaN layer 900 is Mg, and the doping concentration is 3×10 20 cm -3 The thickness thereof was 30nm.
The preparation method of the light-emitting diode epitaxial wafer in the embodiment comprises the following steps:
(1) A substrate is provided.
(2) Growing a buffer layer on a substrate;
wherein, growing an AlN layer by PVD as a buffer layer;
(3) Growing an undoped GaN layer on the buffer layer;
wherein the undoped GaN layer is grown by MOCVD. The growth temperature is 1120 ℃, and the growth pressure is 200torr.
(4) Growing an N-type GaN layer on the undoped GaN layer;
wherein, the growth temperature of the N-type GaN layer is 1130 ℃ and the growth pressure is 300torr by MOCVD.
(5) Growing a first stress buffer layer on the N-type GaN layer;
specifically, a first potential well layer and a first barrier layer are periodically grown on the N-type GaN layer through MOCVD until a first stress buffer layer is obtained. Wherein the growth temperature of the first potential well layer is 730 ℃ and the growth pressure is 300torr.
The preparation method of each first barrier layer comprises the following steps: periodic growth of B by MOCVD y Ga 1-y And an N layer and a GaN layer until a first barrier layer is obtained. The growth temperature of the first barrier layer was 810 deg.c and the growth pressure was 300torr.
(6) Growing a second stress buffer layer on the first stress buffer layer;
specifically, the second potential well layer and the second barrier layer are periodically grown on the first stress buffer layer through MOCVD until the second stress buffer layer is obtained. Wherein the growth temperature of the second well layer is 760 ℃ and the growth pressure is 300torr.
The preparation method of each second barrier layer comprises the following steps: periodic growth of B by MOCVD w Ga 1-w And doping the N layer and the Si layer with the GaN layer until a second barrier layer is obtained. The second barrier layer was grown at 860 c and at 300torr.
(7) Growing a multi-quantum well layer on the second stress buffer layer;
and periodically growing an InGaN quantum well layer and a GaN quantum barrier layer on the second stress buffer layer through MOCVD until the multi-quantum well layer is obtained. The growth temperature of the InGaN quantum well layer is 760 ℃, and the growth pressure is 200torr. The growth temperature of the GaN quantum barrier layer is 880 ℃, and the growth pressure is 200torr.
(8) Growing an electron blocking layer on the multiple quantum well layer;
wherein, the Mg doped AlGaN layer is grown by MOCVD and used as an electron blocking layer, the growth temperature is 1050 ℃, and the growth pressure is 220torr.
(9) Growing a P-type GaN layer on the electron blocking layer;
wherein, the P-type GaN layer is grown by MOCVD, the growth temperature is 960 ℃, and the growth pressure is 200torr.
Example 2
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 1 in that:
the first potential well layer 510 is In x Ga 1-x N layers (x=0.05) with a thickness of 2nm; b (B) y Ga 1-y The thickness of the N layer 521 was 1.6nm, and the thickness of the GaN layer was 1.4nm. B (B) w Ga 1-w In the N layer 621, the B component was 0.03 (i.e., w) in a thickness of 2.5nm. The Si doping concentration in the Si-doped GaN layer 622 is 3×10 17 cm -3 And maintained constant, its thickness was 5nm and maintained constant.
The remainder was the same as in example 1.
Example 3
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 2 in that:
the thickness of the Si-doped GaN layer 622 is incrementally changed, specifically linearly from 4nm to 7nm, as the number of second stress buffer layer 600 cycles increases, but the thickness of the Si-doped GaN layer 622 remains constant in each of the second barrier layers 620.
B with the increase of 600 cycles of the second stress buffer layer w Ga 1-w The thickness of the N layer 621 decreases progressively, in particular linearly from 3.5nm to 0.5nm, but in each second barrier layer 620B w Ga 1-w The thickness of the N layer 621 remains constant.
The remainder was the same as in example 2.
Example 4
The present embodiment provides a light emitting diode epitaxial wafer, which is different from embodiment 3 in that:
the Si doping concentration in the Si-doped GaN layer 622 is changed incrementally, specifically from 1×10, with increasing number of 600 cycles of the second stress buffer layer 17 cm -3 Linearly increasing to 4X 10 17 cm -3 In each of the second barrier layers 620, however, the Si doping concentration in the Si-doped GaN layer 622 remains constant.
B with the increase of 600 cycles of the second stress buffer layer w Ga 1-w The B-component duty cycle in the N layer 621 is progressively varied, specifically linearly progressively from 0.04 to 0.01, but in each second barrier layer 620, B w Ga 1-w The B component in the N layer 621 remains constant.
The remainder was the same as in example 3.
Comparative example 1
This comparative example provides a light emitting diode epitaxial wafer, which differs from example 1 in that:
comprises only a first stress buffer layer with a cycle number of 20, each cycle comprising In α Ga 1-α N layer (α=0.08) and Si doped GaN layer (Si doping concentration 5×10) 17 cm -3 ），In α Ga 1-α The thickness of the N layer was 3nm and the thickness of the Si-doped GaN layer was 8nm.
The first stress buffer layer is prepared by MOCVD periodic growth of In α Ga 1-α And the N layer and the Si doped GaN layer are doped until the first stress buffer layer is obtained. Wherein In α Ga 1-α The growth temperature of the N layer was 730 ℃, and the growth pressure was 300torr. The growth temperature of the Si doped GaN layer is 810 ℃ and the growth pressure is 300torr.
The remainder was the same as in example 1.
Comparative example 2
This comparative example provides a light emitting diode epitaxial wafer, which differs from example 1 in that:
the first stress buffer layer is not included. Correspondingly, the preparation step of the layer is not included.
The remainder was the same as in example 1.
Comparative example 3
This comparative example provides a light emitting diode epitaxial wafer, which differs from example 1 in that:
the second stress buffer layer is not included. Correspondingly, the preparation step of the layer is not included.
The remainder was the same as in example 1.
Comparative example 4
This comparative example provides a light emitting diode epitaxial wafer, which differs from example 1 in that:
and (3) replacing the first stress buffer layer and the second stress buffer layer, and correspondingly, replacing the preparation steps of the first stress buffer layer and the second stress buffer layer in the preparation method.
The remainder was the same as in the examples.
The light emitting diode epitaxial wafers obtained in examples 1 to 4 and comparative examples 1 to 4 were tested by the following specific methods:
(1) Manufacturing epitaxial wafer into chip with horizontal structure of 5mil×7mil, and testing luminous power at 3 mA; and calculating the luminous power increasing rate, wherein the specific calculation method comprises the following steps:
wherein eta is the luminous power increasing rate and delta i Luminescence at 3mA for the chips of the i-th group example or comparative examplePower, delta 0 For the chip of comparative example 1 at a luminous power of 3mA,
(2) Testing the working voltage of the chip at 3 mA;
(3) Antistatic properties: the antistatic performance of the chip is tested by using an electrostatic instrument under an HBM (human body discharge model) model, and the test chip can bear the passing proportion of reverse 8000V static electricity.
The specific results are shown in the following table:
as can be seen from the table, when the conventional stress buffer layer (comparative example 1) is replaced with the stress buffer layer (example 1) of the present application, the light emitting efficiency and antistatic performance of the light emitting diode epitaxial wafer are improved, and the operating voltage thereof is not significantly improved.
While the foregoing is directed to the preferred embodiments of the present application, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the application, such changes and modifications are also intended to be within the scope of the application.
Claims (10)
1. The light-emitting diode epitaxial wafer is characterized by comprising a substrate, and a buffer layer, an undoped GaN layer, an N-type GaN layer, a first stress buffer layer, a second stress buffer layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer which are sequentially laminated on the substrate;
the first stress buffer layer is of a periodic structure, and each period comprises a first potential well layer and a first potential barrier layer which are sequentially stacked; the first potential well layer is In x Ga 1-x An N layer, the first barrier layer is B y Ga 1-y A periodic structure formed by alternately stacking N layers and GaN layers;
the second stress buffer layer is of a periodic structure, and each period comprises a second potential well layer and a second barrier layer which are sequentially stacked; the second potential well layer is In z Ga 1-z An N layer, the second barrier layer is B w Ga 1-w And the N layer and the Si doped GaN layer are alternately laminated to form a periodic structure.
2. The led epitaxial wafer of claim 1, wherein the number of cycles of the first stress buffer layer is 5-20 and the number of cycles of the second stress buffer layer is 1-5.
3. The led epitaxial wafer of claim 1, wherein x is 0.01 to 0.1, z is 0.05 to 0.2, and x < z;
the thickness of the first potential well layer is 1.5-3 nm, the thickness of the second potential well layer is 2-5 nm, and the thickness of the first potential well layer is smaller than the thickness of the second potential well layer.
4. The led epitaxial wafer of claim 1, wherein y is 0.03-0.1, w is 0-0.05, and y > w.
5. The light-emitting diode epitaxial wafer of claim 1, wherein the number of cycles of the first barrier layer is 2-5, each B y Ga 1-y The thickness of the N layer is 0.5-2 nm, and the thickness of each GaN layer is 1-2 nm.
6. The light-emitting diode epitaxial wafer of claim 1, wherein the number of cycles of the second barrier layer is 1-3, each B w Ga 1-w The thickness of the N layer is 0.3-3.5 nm, and the thickness of each Si doped GaN layer is 4-8 nm;
the doping concentration of Si in the Si-doped GaN layer is 5×10 16 cm -3 ~5×10 17 cm -3 。
7. The led epitaxial wafer of any one of claims 1-6, wherein the thickness of the Si-doped GaN layer exhibits increasing variation with increasing number of cycles of the second stress buffer layer, the B w Ga 1-w The thickness of the N layers is progressively varied.
8. The led epitaxial wafer of any one of claims 1-6, wherein the Si doping concentration in the Si-doped GaN layer exhibits increasing variation with increasing number of cycles of the second stress buffer layer, the B w Ga 1-w The B component duty ratio in the N layer is changed in a decreasing way.
9. A method for preparing a light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer according to any one of claims 1 to 8, and is characterized by comprising the following steps:
providing a substrate, and sequentially growing a buffer layer, an undoped GaN layer, an N-type GaN layer, a first stress buffer layer, a second stress buffer layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer on the substrate;
the first stress buffer layer is of a periodic structure, and each period comprises a first potential well layer and a first potential barrier layer which are sequentially stacked; the first potential well layer is In x Ga 1-x An N layer, the first barrier layer is B y Ga 1-y A periodic structure formed by alternately stacking N layers and GaN layers;
the second stress buffer layer is of a periodic structure, and each period comprises a second potential well layer and a second barrier layer which are sequentially stacked; the second potential well layer is In z Ga 1-z An N layer, the second barrier layer is B w Ga 1-w A periodic structure formed by alternately stacking N layers and Si-doped GaN layers;
the growth temperature of the first stress buffer layer is less than the growth temperature of the second stress buffer layer.
10. The method for manufacturing a light-emitting diode epitaxial wafer according to claim 9, wherein the growth temperature of the first potential well layer is 700 ℃ to 760 ℃ and the growth pressure is 100torr to 500torr;
the growth temperature of the first barrier layer is 750-820 ℃, and the growth pressure is 100-500 torr;
the growth temperature of the second potential well layer is 750-840 ℃, and the growth pressure is 100-500 torr;
the growth temperature of the second barrier layer is 780-900 ℃, and the growth pressure is 100-500 torr.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117253948A (en) * | 2023-11-20 | 2023-12-19 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode |
| CN117476829A (en) * | 2023-12-28 | 2024-01-30 | 江西兆驰半导体有限公司 | Ultraviolet light-emitting diode epitaxial wafer, preparation method thereof and ultraviolet light-emitting diode |
| CN117525230A (en) * | 2024-01-08 | 2024-02-06 | 江西兆驰半导体有限公司 | Micro-LED epitaxial structure and preparation method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107170865A (en) * | 2017-05-27 | 2017-09-15 | 安徽三安光电有限公司 | A kind of semiconductor light-emitting elements and preparation method thereof |
| CN113675303A (en) * | 2021-08-20 | 2021-11-19 | 江西兆驰半导体有限公司 | Nitride light-emitting diode epitaxial wafer and preparation method thereof |
| US20230011795A1 (en) * | 2021-06-30 | 2023-01-12 | Seoul Viosys Co., Ltd. | Light emitting diode |
| CN116454186A (en) * | 2023-06-15 | 2023-07-18 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode |
| CN116581214A (en) * | 2023-06-02 | 2023-08-11 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode |
| CN116581216A (en) * | 2023-07-12 | 2023-08-11 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode |
-
2023
- 2023-08-31 CN CN202311108429.8A patent/CN116825918B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107170865A (en) * | 2017-05-27 | 2017-09-15 | 安徽三安光电有限公司 | A kind of semiconductor light-emitting elements and preparation method thereof |
| US20230011795A1 (en) * | 2021-06-30 | 2023-01-12 | Seoul Viosys Co., Ltd. | Light emitting diode |
| CN113675303A (en) * | 2021-08-20 | 2021-11-19 | 江西兆驰半导体有限公司 | Nitride light-emitting diode epitaxial wafer and preparation method thereof |
| CN116581214A (en) * | 2023-06-02 | 2023-08-11 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode |
| CN116454186A (en) * | 2023-06-15 | 2023-07-18 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode |
| CN116581216A (en) * | 2023-07-12 | 2023-08-11 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117253948A (en) * | 2023-11-20 | 2023-12-19 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode |
| CN117253948B (en) * | 2023-11-20 | 2024-03-08 | 江西兆驰半导体有限公司 | Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode |
| CN117476829A (en) * | 2023-12-28 | 2024-01-30 | 江西兆驰半导体有限公司 | Ultraviolet light-emitting diode epitaxial wafer, preparation method thereof and ultraviolet light-emitting diode |
| CN117476829B (en) * | 2023-12-28 | 2024-03-29 | 江西兆驰半导体有限公司 | Ultraviolet light-emitting diode epitaxial wafer, preparation method thereof and ultraviolet light-emitting diode |
| CN117525230A (en) * | 2024-01-08 | 2024-02-06 | 江西兆驰半导体有限公司 | Micro-LED epitaxial structure and preparation method thereof |
| CN117525230B (en) * | 2024-01-08 | 2024-03-29 | 江西兆驰半导体有限公司 | Micro-LED epitaxial structure and preparation method thereof |
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