CN116960247A - LED epitaxial wafer with high light extraction efficiency and preparation method thereof - Google Patents
LED epitaxial wafer with high light extraction efficiency and preparation method thereof Download PDFInfo
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Abstract
The invention discloses an LED epitaxial wafer with high light extraction efficiency, a preparation method thereof and an LED, and relates to the field of semiconductor photoelectric devices. The LED epitaxial wafer comprises a substrate, a buffer layer, an N-type GaN layer, a stress buffer layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer which are sequentially arranged; the stress buffer layer comprises a first stress buffer layer, a metal reflecting layer and a second stress buffer layer which are sequentially laminated on the N-type GaN layer; the first stress buffer layer is Si doped with Al a In b Ga 1‑a‑b An N layer, wherein a is more than or equal to 0 and less than or equal to 0.6,0 and b is more than or equal to 0.2; the metal reflecting layer is a laminated structure formed by one or more of an Al metal layer, a Ga metal layer, an In metal layer and an Mg metal layer; the second stress buffer layer is Si doped with Al c In d Ga 1‑c‑d And N layers, wherein c is more than or equal to 0 and less than or equal to 0.6,0, d is more than or equal to 0.3. By implementing the invention, the luminous efficiency can be improved.
Description
Technical Field
The invention relates to the field of semiconductor photoelectric devices, in particular to an LED epitaxial wafer with high light extraction efficiency and a preparation method thereof.
Background
In order to obtain a high-brightness LED, it is critical to increase the internal and external quantum efficiency of the device. At present, the internal quantum efficiency of the blue light GaN-based LED can reach more than 80%, but the external quantum efficiency of a high-power LED chip is only about 40%. The main factor that restricts the improvement of external quantum efficiency is that the light extraction efficiency of the chip is low because the refractive index of the GaN material (n=2.5) differs greatly from the refractive index of air (n=1) and the refractive index of the sapphire substrate (n=1.75), resulting in that the critical angles at which the total reflection occurs at the air-GaN interface and the sapphire-GaN interface are only 23.6 ° and 44.4 °, respectively, and only a small number of light generated in the active region can escape from the bulk material. In order to improve the light extraction efficiency of the chip, the main technical schemes adopted at home and abroad at present include a growth Distributed Bragg Reflector (DBR) structure, a patterned substrate (PSS) technology, a surface roughening technology, a photonic crystal technology and the like. The PSS has high requirement on the regularity of the pattern, and the sapphire substrate is harder, so that the consistency and uniformity of the whole pattern are difficult to achieve in both dry etching and wet etching processes, and the manufacturing process has high requirements on equipment and processes, so that the cost is high. DBR and photonic crystal fabrication processes are relatively complex and costly, and surface roughening techniques that employ dry etching or wet etching processes also present significant challenges.
Disclosure of Invention
The invention aims to solve the technical problem of providing an LED epitaxial wafer with high light extraction efficiency and a preparation method thereof, which can improve the external quantum efficiency of the LED epitaxial wafer and have simple manufacturing process.
In order to solve the problems, the invention discloses an LED epitaxial wafer with high light extraction efficiency, which comprises a substrate, and a buffer layer, an N-type GaN layer, a stress buffer layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer which are sequentially laminated on the substrate; the stress buffer layer comprises a first stress buffer layer, a metal reflecting layer and a second stress buffer layer which are sequentially laminated on the N-type GaN layer;
the first stress buffer layer is Si doped with Al a In b Ga 1-a-b An N layer, wherein a is more than or equal to 0 and less than or equal to 0.6,0 and b is more than or equal to 0.2;
the metal reflecting layer is a laminated structure formed by one or more of an Al metal layer, a Ga metal layer, an In metal layer and an Mg metal layer;
the second stress buffer layer is Si doped with Al c In d Ga 1-c-d And N layers, wherein c is more than or equal to 0 and less than or equal to 0.6,0, d is more than or equal to 0.3.
As an improvement of the technical proposal, the thickness of the first stress buffer layer is 50 nm-500 nm, and the doping concentration of Si is 2 multiplied by 10 17 cm -3 ～2×10 19 cm -3 ；
The thickness of the metal reflecting layer is 2 nm-20 nm;
the thickness of the second stress buffer layer is 30 nm-300 nm, and the doping concentration of Si is 2 multiplied by 10 16 cm -3 ～2×10 18 cm -3 。
As improvement of the technical scheme, a is more than or equal to 0.2 and less than or equal to 0.5,0.05, c is more than or equal to 0.4, and a is more than c;
b is more than or equal to 0.04 and less than or equal to 0.1,0.1, d is more than or equal to 0.23, and b is less than d.
As an improvement of the technical scheme, the multiple quantum well layer is of a periodic structure, the period number is 4-16, and each period comprises a quantum well layer and a quantum barrier layer;
each quantum well layer comprises a pre-well protective layer, a light-emitting well layer and a post-well protective layer which are sequentially stacked; the pre-well protective layer is In with In composition changing with increasing thickness y Ga 1-y An N layer, the light-emitting well layer is In x Ga 1-x N layer, the protective layer is In whose In component is decreasingly changed along with the thickness increase z Ga 1-z An N layer; wherein x is more than or equal to 0.12 and less than or equal to 0.4, y is more than or equal to 0 and less than or equal to 0.4, and z is more than or equal to 0 and less than or equal to 0.4;
the quantum barrier layer is a GaN layer.
As an improvement of the technical scheme, the thickness of the protective layer before the well is 0.5-2 nm, and the In component increases from 0to the In component proportion In the light-emitting well layer along with the thickness;
the thickness of the light-emitting well layer is 2.5 nm-5 nm;
the thickness of the protective layer after the well is 0.5-2 nm, and the In component of the protective layer is decreased to 0 from the In component duty ratio In the luminescent well layer along with the thickness;
the thickness of the quantum barrier layer is 8 nm-15 nm.
As an improvement of the technical proposal, H is adopted after the growth of the protective layer after the trap is completed 2 And NH 3 Treating the mixed gas of the post-trap protection layer to coarsen the surface of the post-trap protection layer;
wherein the treatment temperature is 800-950 ℃, the treatment pressure is 100-300 torr, and the treatment time is 20-120 s; h 2 And NH 3 The volume ratio of (2) is 1:3-1:5.
Correspondingly, the invention also discloses a preparation method of the LED epitaxial wafer with high light extraction efficiency, which is used for preparing the LED epitaxial wafer with high light extraction efficiency and comprises the following steps:
providing a substrate, and sequentially growing a buffer layer, an N-type GaN layer, a stress buffer layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer on the substrate; the stress buffer layer comprises a first stress buffer layer, a metal reflecting layer and a second stress buffer layer which are sequentially laminated on the N-type GaN layer;
the first stress buffer layer is Si doped with Al a In b Ga 1-a-b An N layer, wherein a is more than or equal to 0 and less than or equal to 0.6,0 and b is more than or equal to 0.2;
the metal reflecting layer is a laminated structure formed by one or more of an Al metal layer, a Ga metal layer, an In metal layer and an Mg metal layer;
the second stress buffer layer is Si doped with Al c In d Ga 1-c-d And N layers, wherein c is more than or equal to 0 and less than or equal to 0.6,0, d is more than or equal to 0.3.
As an improvement of the technical scheme, the growth temperature of the first stress buffer layer is 800-950 ℃ and the growth pressure is 100-300 torr;
the growth temperature of the metal reflecting layer is 750-1050 ℃, and the growth pressure is 30-500 torr;
the growth temperature of the second stress buffer layer is 780-900 ℃, and the growth pressure is 100-300 torr.
As an improvement of the above technical solution, the multiple quantum well layer includes a quantum well layer and a quantum barrier layer; the quantum well layer comprises a pre-well protective layer, a light-emitting well layer and a post-well protective layer;
the growth temperature of the protective layer before the trap is 700-900 ℃ and the growth pressure is 100-300 torr;
the growth temperature of the light-emitting well layer is 700-850 ℃, and the growth pressure is 100-300 torr;
the growth temperature of the protective layer after the trap is 700-900 ℃ and the growth pressure is 100-300 torr.
As an improvement of the technical scheme, in the growth process of the protective layer before the trap, the growth temperature is decreased from 900 ℃ to 700 ℃;
in the growth process of the post-trap protection layer, the growth temperature is increased from 700 ℃ to 900 ℃.
The implementation of the invention has the following beneficial effects:
in the LED epitaxial wafer, a stress buffer layer is introduced between an N-type GaN layer and a multiple quantum well layer, and the LED epitaxial wafer comprises a first stress buffer layer sequentially laminated on the N-type GaN layerA layer, a metal reflective layer, and a second stress buffer layer; the first stress buffer layer is Si doped with Al a In b Ga 1-a-b The metal reflection layer is a laminated structure formed by one or more of an Al metal layer, a Ga metal layer, an In metal layer and an Mg metal layer; the second stress buffer layer is Si doped with Al c In d Ga 1-c-d And N layers. Through the design of the metal reflecting layer, the number of photons penetrating through the metal reflecting layer and immersing into the first stress releasing layer and the N-type semiconductor layer can be greatly reduced, the light absorption loss of a bottom layer material is avoided, the external quantum efficiency is effectively improved, and the luminous efficiency is improved.
Further, each quantum well of the multi-quantum well layer comprises a pre-well protection layer, a light-emitting well layer and a post-well protection layer; the protective layer before the trap is In with In component changing with increasing thickness y Ga 1-y An N layer, the light-emitting well layer is In x Ga 1-x N layer, protective layer behind trap is In whose In component is decreasing with thickness z Ga 1-z An N layer; through the structure, the crystal quality of the light-emitting well layer can be greatly improved, the internal quantum efficiency is improved, and the light-emitting efficiency is further improved. Furthermore, the invention adopts H after the growth of the protective layer after the trap is finished 2 、NH 3 After the treatment, the crystalline quality difference material and cluster In clusters on the surface of the protective layer are decomposed, so that the quality of the multi-quantum well luminescent layer material can be obviously improved; in addition, the roughened surface formed after the strength can reduce in-plane total reflection, improve the light-emitting efficiency of the multi-quantum well layer, improve the external quantum efficiency and improve the luminous efficiency of the LED epitaxial wafer.
In view of the above, the LED epitaxial wafer of the present invention can provide the ratio of photon overflowed material in the multi-quantum well layer, improve the light extraction efficiency, remarkably improve the crystal quality of the multi-quantum well layer, and improve the internal quantum efficiency; the two are combined, and the luminous efficiency is effectively improved.
Drawings
Fig. 1 is a schematic structural diagram of an LED epitaxial wafer with high light extraction efficiency according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a quantum well layer according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for manufacturing an LED epitaxial wafer with high light extraction efficiency according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below in order to make the objects, technical solutions and advantages of the present invention more apparent.
Referring to fig. 1, the invention discloses an LED epitaxial wafer with high light extraction efficiency, which comprises a substrate 1, and a buffer layer 2, an N-type GaN layer 3, a stress buffer layer 4, a multiple quantum well layer 5, an electron blocking layer 6 and a P-type GaN layer 7 which are sequentially arranged on the substrate 1. The stress buffer layer 4 includes a first stress buffer layer 41, a metal reflective layer 42, and a second stress buffer layer 43 sequentially stacked on the N-type GaN layer 3.
Wherein the first stress buffer layer 41 is Si-doped Al a In b Ga 1-a-b The N layer has a thickness of 50nm to 500nm, and exemplary is 80nm, 120nm, 160nm, 220nm, 300nm, 350nm, 400nm or 430nm, but is not limited thereto. Preferably 100nm to 300nm. Si doped with Al a In b Ga 1-a-b The doping concentration of Si in the N layer is 2×10 17 cm -3 ～2×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the Exemplary is 4X 10 17 cm -3 、8×10 17 cm -3 、2×10 18 cm -3 、6×10 18 cm -3 、9×10 18 cm -3 Or 1X 10 19 cm -3 But is not limited thereto; preferably 5X 10 17 cm -3 ～5×10 18 cm -3 。
Si doped with Al a In b Ga 1-a-b The Al component of the N layer has a ratio (i.e., a) of 0to 0.6, and exemplary values are 0.08, 0.14, 0.2, 0.28, 0.33, 0.45, or 0.57, but are not limited thereto. Preferably 0.2 to 0.5.Si doped with Al a In b Ga 1-a-b The In component of the N layer has a ratio (i.e., b) of 0to 0.2, and exemplary values are 0.02, 0.04, 0.06, 0.12, 0.15, or 0.18, but are not limited thereto. Preferably 0.04 to 0.1.
The metal reflective layer 42 is a stacked structure formed of one or more of an Al metal layer, a Ga metal layer, an In metal layer, and an Mg metal layer, but is not limited thereto. Preferably an Al metal layer.
The thickness of the metal reflective layer 42 is 2nm to 25nm, and the thickness range satisfies the condition of total reflection of light, thereby greatly improving the light extraction efficiency. The thickness of the metal reflective layer 42 is, but not limited to, 3.5nm, 5.4nm, 8.2nm, 12.5nm, 15.8nm, 20nm, or 24.3nm, for example. Preferably 2nm to 20nm.
Wherein the second stress buffer layer 43 is Si doped with Al c In d Ga 1-c-d The N layer has a thickness of 30nm to 300nm, and is exemplified by, but not limited to, 50nm, 80nm, 120nm, 160nm, 220nm, or 260 nm. Preferably 50nm to 200nm. Si doped with Al c In d Ga 1-c-d The doping concentration of Si in the N layer is 2×10 16 cm -3 ～2×10 18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the Exemplary is 3X 10 16 cm -3 、7×10 16 cm -3 、1×10 17 cm -3 、6×10 17 cm -3 Or 8X 10 17 cm -3 But is not limited thereto; preferably 5X 10 16 cm -3 ～3×10 17 cm -3 。
Si doped with Al c In d Ga 1-c-d The Al component of the N layer has a ratio (i.e., molar content of AlN, c) of 0to 0.6, and exemplary is 0.08, 0.14, 0.2, 0.28, 0.33, 0.45, or 0.57, but is not limited thereto. Preferably 0.05 to 0.3.Si doped with Al c In d Ga 1-c-d The In component In the N layer has a ratio (i.e., the molar content of InN, d) of 0to 0.3, and exemplary is 0.04, 0.08, 0.12, 0.16, 0.2, 0.24, or 0.28, but is not limited thereto. Preferably 0.1 to 0.23.
Preferably, in one embodiment of the present invention, a > c and b < d, based on the above control, not only the external quantum efficiency but also the crystal quality of the multiple quantum well layer and the internal quantum efficiency can be improved, thereby further improving the light emitting efficiency.
The multiple quantum well layer 5 has a periodic structure with a period of 4 to 16, and each period includes a quantum well layer 51 and a quantum barrier layer 52 laminated in this order. The quantum well layer 51 may be an InGaN quantum well layer having a thickness of 3nm to 8nm and an in composition ratio of 0.12 to 0.4; the quantum barrier layer 52 may be a GaN quantum barrier layer, but is not limited thereto.
Preferably, referring to fig. 2, in one embodiment of the present invention, the quantum well layer 51 includes a pre-well protective layer 511, a light emitting well layer 512, and a post-well protective layer 513, which are sequentially stacked. Wherein the pre-well protective layer 511 is In whose In composition varies with the thickness y Ga 1-y N layer, light emitting well layer 512 is In x Ga 1-x N layer, the post-well protective layer 513 is In whose In composition is decreasing with increasing thickness z Ga 1-z And N layers.
Among them, the thickness of the pre-well protective layer 511 is 0.5nm to 2nm, and exemplary is 0.8nm, 1nm, 1.4nm, or 1.8nm, but is not limited thereto. Preferably 0.5nm to 1.5nm. The In composition ratio (i.e., y) In the pre-well protective layer 511 is 0to 0.4, and is exemplified by 0.05, 0.13, 0.21, 0.29, or 0.37, but is not limited thereto. Preferably, in one embodiment of the present invention, the In composition In the pre-well protective layer 511 is gradually increased from 0to the In composition In the light emitting well layer 512 (i.e., x) as the thickness of the pre-well protective layer 511 increases.
The thickness of the light emitting well layer 512 is 2nm to 5nm, and is exemplified by, but not limited to, 2.2nm, 2.6nm, 3nm, 3.4nm, 3.8nm, 4.2nm, or 4.6 nm. Preferably 2.5nm to 5nm. The In composition ratio (i.e., x) In the light emitting well layer 512 is 0.12 to 0.4, and exemplary is 0.15, 0.18, 0.21, 0.28, 0.3, or 0.35, but is not limited thereto. Preferably 0.12 to 0.3; more preferably 0.2 to 0.3.
The thickness of the post-well protective layer 513 is, but not limited to, 0.5nm to 2nm, and is exemplified by 0.8nm, 1nm, 1.4nm, or 1.8nm. Preferably 0.5nm to 1.5nm. The In composition ratio (i.e., z) In the post-well protective layer 513 is 0to 0.4, and is exemplified by, but not limited to, 0.05, 0.13, 0.21, 0.29, or 0.37. Preferably, in one embodiment of the present invention, the In composition In the post-well protective layer 513 is gradually decreased from the In composition In the light emitting well layer 512 to 0 (i.e., x) as the thickness of the post-well protective layer 513 increases.
In the present embodiment, the quantum barrier layer 52 is a GaN layer, and the thickness thereof is 8nm to 15nm.
Preferably, H is adopted after the growth of the protective layer after the well is completed 2 And NH 3 Treating the mixed gas of the post-trap protection layer to coarsen the surface of the post-trap protection layer; wherein the treatment temperature is 800-950 ℃, the treatment pressure is 100-300 torr, and the treatment time is 20-120 s; h 2 And NH 3 The volume ratio of (2) is 1:3-1:5.
Among them, the substrate 1 is a sapphire substrate, a silicon carbide substrate, a zinc oxide substrate, or a gallium oxide substrate, but is not limited thereto. A sapphire substrate is preferred.
Among them, the buffer layer 2 is an AlN layer, a low-temperature GaN layer, or a low-temperature AlGaN layer, but is not limited thereto. An AlN layer is preferred. The thickness of the buffer layer 2 is 20nm to 100nm.
Among them, the doping element of the N-type GaN layer 3 is Si or Ge, but is not limited thereto, and Si is preferable. The doping concentration of the N-type GaN layer 3 was 5×10 18 cm -3 ～5×10 19 cm -3 The thickness of the N-type GaN layer 3 is 1 μm to 3 μm.
Preferably, in one embodiment of the present invention, an undoped GaN layer 8 having a thickness of 1 μm to 4 μm is further provided between the buffer layer 2 and the N-type GaN layer 3.
The electron blocking layer 6 is an AlInGaN layer or an AlGaN layer, but is not limited thereto. The thickness of the electron blocking layer 6 is 10nm to 80nm.
The P-type doping element in the P-type GaN layer 7 is Mg, be or Zn, but is not limited thereto. Mg is preferred. The P-type doping concentration in the P-type GaN layer 7 is 1×10 19 cm -3 ～1×10 21 cm -3 Exemplary is 3×10 19 cm -3 、7×10 19 cm -3 、1×10 20 cm -3 、4×10 20 cm -3 Or 8X 10 20 cm -3 But is not limited thereto. The thickness of the P-type GaN layer 7 is 10nm to 50nm, and is exemplified by 12nm, 18nm, 25nm, 30nm, 42nm, or 45nm, but not limited thereto.
Correspondingly, referring to fig. 3, the invention also discloses a preparation method of the LED epitaxial wafer with high light extraction efficiency, which is used for preparing the LED epitaxial wafer with high light extraction efficiency, and comprises the following steps:
s1: providing a substrate;
s2: sequentially growing a buffer layer, an N-type GaN layer, a stress buffer layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer on a substrate;
specifically, step S2 includes:
s21: growing a buffer layer on a substrate;
wherein in one embodiment of the present invention, an AlN layer is grown by PVD as a buffer layer, but is not limited thereto.
S22: growing an undoped GaN layer on the buffer layer;
in one embodiment of the invention, the undoped GaN layer is grown in MOCVD at 1050-1200 deg.C and at 100-500 torr.
S23: growing an N-type GaN layer on the undoped GaN layer;
in one embodiment of the invention, the N-type GaN layer is grown in MOCVD at 1050-1200 deg.C and at 100-500 torr.
S24: growing a stress buffer layer on the N-type GaN layer;
wherein, step S24 includes:
s241: growing a first stress buffer layer on the N-type GaN layer;
wherein Si doped with Al can be grown by MOCVD, MBE or VPE a In b Ga 1-a-b And N layer as the first stress buffer layer, but not limited thereto.
Preferably, in one embodiment of the invention, si-doped Al is grown by MOCVD a In b Ga 1-a-b And N layers serving as first stress buffer layers. The growth temperature is 800-950 ℃ and the growth pressure is 100-300 torr.
S242: growing a metal reflecting layer on the first stress buffer layer;
among them, the metal reflective layer may be grown by PVD, MOCVD, evaporation, etc., but is not limited thereto.
Preferably, in one embodiment of the present invention, the metal reflective layer is grown by MOCVD. The growth temperature is 750-1050 deg.c and the growth pressure is 30-500 torr.
S243: growing a second stress buffer layer on the metal reflecting layer to obtain a stress buffer layer;
wherein Si doped with Al can be grown by MOCVD, MBE or VPE c In d Ga 1-c-d And an N layer as a second stress buffer layer, but not limited thereto.
Preferably, in one embodiment of the invention, si-doped Al is grown by MOCVD c In d Ga 1-c-d And N layers serving as second stress buffer layers. The growth temperature is 780-900 deg.c and the growth pressure is 100-300 torr.
S25: growing a multi-quantum well layer on the stress buffer layer;
and periodically growing a quantum well layer and a quantum barrier layer on the stress buffer layer until a multi-quantum well layer is obtained.
In one embodiment of the present invention, an InGaN quantum well layer is grown by MOCVD, and the growth temperature is 750-850 ℃ and the growth pressure is 50-300 torr. And growing a GaN quantum barrier layer by MOCVD, wherein the growth temperature is 750-900 ℃ and the growth pressure is 50-300 torr.
Preferably, in one embodiment of the present invention, the preparation method of each quantum well layer includes the steps of:
(I) Growing a protective layer before a trap;
wherein In whose In composition is incrementally varied with thickness can be grown by MOCVD, MBE or VPE y Ga 1-y And an N layer as a pre-well protection layer, but is not limited thereto.
Preferably, in one embodiment of the present invention, in is grown by MOCVD In which In composition is incrementally varied with thickness y Ga 1-y And N layer as well front protective layer. The growth temperature is 700-900 deg.c and the growth pressure is 100-300 torr.
Preferably, in another embodiment of the present invention, the growth temperature of the pre-well protection layer is decreased from 900 ℃ to 700 ℃.
(II) growing a light emitting well layer on the pre-well protective layer;
wherein In can be grown by MOCVD, MBE or VPE x Ga 1-x N layer, which is not limited to this, is a light emitting well layer.
Preferably, in one embodiment of the present invention, in is grown by MOCVD x Ga 1-x And an N layer serving as a light emitting well layer. The growth temperature is 700-850 deg.c and the growth pressure is 100-300 torr.
(III) growing a post-well protection layer on the light-emitting well layer;
wherein In whose In composition is progressively changed with increasing thickness can be grown by MOCVD, MBE or VPE z Ga 1-z And an N layer as a post-well protection layer, but is not limited thereto.
Preferably, in one embodiment of the present invention, in is grown by MOCVD In which In composition is progressively varying with increasing thickness z Ga 1-z And N layer as well back protective layer. The growth temperature is 700-900 deg.c and the growth pressure is 100-300 torr.
Preferably, in another embodiment of the present invention, the growth temperature of the post-well protection layer is decreased from 700 ℃ to 900 ℃.
(IV) roughening the post-well protection layer;
specifically, H is adopted 2 And NH 3 Treating the mixed gas of the post-trap protective layer to coarsen the surface of the post-trap protective layer; wherein the treatment temperature is 800-950 ℃, the treatment pressure is 100-300 torr, and the treatment time is 20-120 s; h 2 And NH 3 The volume ratio of (2) is 1:3-1:5.
S26: growing an electron blocking layer on the multiple quantum well layer;
wherein in one embodiment of the invention, an AlInGaN layer is grown by MOCVD as an electron blocking layer. The growth temperature is 800-900 deg.c and the growth pressure is 50-300 torr.
S27: growing a P-type GaN layer on the electron blocking layer;
in one embodiment of the invention, the P-type GaN layer is grown by MOCVD at 900-1050 ℃ and at 100-500 torr.
The invention is further illustrated by the following examples:
example 1
Referring to fig. 1, the present embodiment provides an LED epitaxial wafer with high light extraction efficiency, which includes a substrate 1, and a buffer layer 2, an undoped GaN layer 8, an N-type GaN layer 3, a stress buffer layer 4, a multiple quantum well layer 5, an electron blocking layer 6, and a P-type GaN layer 7 sequentially disposed on the substrate 1.
Wherein the substrate 1 is a sapphire substrate. The buffer layer 2 is an AlN layer having a thickness of 33nm. The thickness of the undoped GaN layer 8 was 1.5 μm. The thickness of the N-type GaN layer 3 was 2.5 μm, the doping element was Si, and the doping concentration of Si was 7X10 19 cm -3 。
Wherein the stress buffer layer 4 includes a first stress buffer layer 41, a metal reflective layer 42, and a second stress buffer layer 43 sequentially stacked on the N-type GaN layer 3; the first stress buffer layer 41 is Si doped with Al a In b Ga 1-a-b N layers (a=0.15, b=0.15) with Si doping concentration of 1×10 19 cm -3 The thickness was 450nm. The metal reflection 42 is an Al metal layer with a thickness of 15nm. The second stress buffer layer 43 is Si doped with Al c In d Ga 1-c-d N layer (c=0.15, d=0.15) with a thickness of 220nm and Si doping concentration of 5×10 17 cm -3 。
The multiple quantum well layer 5 has a periodic structure, and the number of periods is 10, and each period includes a quantum well layer 51 and a quantum barrier layer 52 stacked in this order. The quantum well layer 51 is an InGaN quantum well layer, the In component of which is 0.23 and the thickness of which is 4nm; the quantum barrier layer 52 is a GaN quantum barrier layer having a thickness of 12nm.
The electron blocking layer 5 is an AlInGaN layer, and the thickness thereof is 50nm. The thickness of the P-type GaN layer 7 is 20nm, the doping element is Mg, and the doping concentration is 5 multiplied by 10 20 cm -3 。
The preparation method of the LED epitaxial wafer for high light extraction efficiency in the embodiment comprises the following steps:
(1) A substrate is provided.
(2) Growing a buffer layer on a substrate;
wherein an AlN layer is grown by PVD as a buffer layer.
(3) Growing an undoped GaN layer on the buffer layer;
wherein, the undoped GaN layer is grown by MOCVD, the growth temperature is 1020 ℃, and the growth pressure is 300torr.
(4) Growing an N-type GaN layer on the undoped GaN layer;
wherein, the N-type GaN layer is grown by MOCVD, the growth temperature is 1150 ℃, and the growth pressure is 300torr.
(5) Growing a first stress buffer layer on the N-type GaN layer;
wherein, si is doped with Al by MOCVD a In b Ga 1-a-b And N layers serving as first stress buffer layers. The growth temperature is 820 ℃, and the growth pressure is 200torr.
(6) Growing a metal reflecting layer on the first stress buffer layer;
wherein an Al layer is grown by MOCVD as a metal reflective layer. The growth temperature is 800 ℃ and the growth pressure is 100torr.
(7) Growing a second stress buffer layer on the metal reflecting layer;
wherein, si is doped with Al by MOCVD c In d Ga 1-c-d And N layers serving as second stress buffer layers. The growth temperature is 800 ℃, and the growth pressure is 200torr.
(8) Growing a multi-quantum well layer on the second stress buffer layer;
wherein the quantum well layer and the quantum barrier layer are periodically grown in MOCVD to form a multi-quantum well layer. Wherein the growth temperature of the quantum well layer is 780 ℃ and the growth pressure is 200torr. The growth temperature of the quantum barrier layer is 860 ℃ and the growth pressure is 200torr.
(9) Growing an electron blocking layer on the multiple quantum well layer;
wherein an AlInGaN layer is grown by MOCVD as an electron blocking layer. The growth temperature was 880℃and the growth pressure was 200torr.
(10) Growing a P-type GaN layer on the electron blocking layer;
wherein the P-type GaN layer is grown by MOCVD. The growth temperature is 1000 ℃ and the growth pressure is 200torr.
Example 2
The present embodiment provides an LED epitaxial wafer with high light extraction efficiency, which is different from embodiment 1 in that:
the first stress buffer layer 41 is Si doped with Al a In b Ga 1-a-b N layers (a=0.28, b=0.06) with Si doping concentration of 1×10 18 cm -3 The thickness was 250nm. The second stress buffer layer 43 is Si doped with Al c In d Ga 1-c-d N layer (c=0.15, d=0.18) with a thickness of 140nm and Si doping concentration of 1×10 17 cm -3 。
The remainder was the same as in example 1.
Example 3
The present embodiment provides an LED epitaxial wafer with high light extraction efficiency, which is different from embodiment 2 in that:
each quantum well layer 51 includes a pre-well protective layer 511, a light emitting well layer 512, and a post-well protective layer 513. Wherein the pre-well protective layer 511 is In whose In composition varies with the thickness y Ga 1-y And an N layer whose In composition is increased from 0to 0.23 and whose thickness is 1.2nm. The light-emitting well layer 512 is In x Ga 1-x N layers (x=0.23) with a thickness of 3nm. The post-well protective layer 513 is In whose In composition changes In decreasing fashion with increasing thickness z Ga 1-z And an N layer, the In component of which is reduced from 0.23 to 0, and the thickness of which is 1.8nm.
The quantum barrier layer is a GaN layer, and the thickness of the quantum barrier layer is 12nm.
The preparation method of each quantum well layer comprises the following steps:
(I) Growing a protective layer before a trap;
wherein In whose In composition is incrementally changed with thickness is grown by MOCVD y Ga 1-y And N layer as well front protective layer. The growth temperature is decreased from 900 ℃ to 700 ℃ and the growth pressure is 200torr.
(II) growing a light emitting well layer on the pre-well protective layer;
wherein In is grown by MOCVD x Ga 1-x And an N layer serving as a light emitting well layer. The growth temperature is 760 ℃, and the growth pressure is 200 DEGtorr。
(III) growing a post-well protection layer on the light-emitting well layer;
wherein In whose In composition is progressively changed with thickness increase is grown by MOCVD z Ga 1-z And N layer as well back protective layer. The growth temperature is increased from 700 ℃ to 900 ℃ and the growth pressure is 200torr.
The remainder was the same as in example 2.
Example 4
The present embodiment provides an LED epitaxial wafer with high light extraction efficiency, which is different from embodiment 3 in that:
and coarsening the protective layer after the well is grown. Namely, the preparation method of each quantum well layer further comprises the following steps:
preferably, in another embodiment of the present invention, the growth temperature of the post-well protection layer is decreased from 700 ℃ to 900 ℃.
(IV) roughening the post-well protection layer;
specifically, H is adopted 2 And NH 3 Treating the mixed gas of the post-trap protective layer to coarsen the surface of the post-trap protective layer; wherein the treatment temperature is 820 ℃, the treatment pressure is 200torr, and the treatment time is 80s; h 2 And NH 3 The volume ratio of (2) is 1:4.5.
The remainder was the same as in example 3.
Comparative example 1
This comparative example provides an LED epitaxial wafer, which differs from example 1 in that:
the stress buffering layer is not included, and correspondingly the preparation step of the layer is not included.
The remainder was the same as in example 1.
Comparative example 2
This comparative example provides an LED epitaxial wafer, which differs from example 1 in that:
the first stress buffer layer is not included, and correspondingly, the preparation step of the layer is not included.
The remainder was the same as in example 1.
Comparative example 3
This comparative example provides an LED epitaxial wafer, which differs from example 1 in that:
no metal reflective layer is included, and correspondingly no step is included in the preparation of the layer.
The remainder was the same as in example 1.
Comparative example 4
This comparative example provides an LED epitaxial wafer, which differs from example 1 in that:
the second stress buffer layer is not included, and correspondingly, the preparation step of the layer is not included.
The remainder was the same as in example 1.
The LED epitaxial wafers obtained in examples 1 to 4 and comparative examples 1 to 4 were processed into LED chips having a vertical structure of 10×24mil, and the brightness at 120mA was measured, 10 for each of the examples and comparative examples, and the average value was obtained. And the luminance improvement ratio was calculated based on comparative example 1.
The specific results are as follows:
| luminance enhancement rate/% | |
| Example 1 | 3.52 |
| Example 2 | 4.18 |
| Example 3 | 6.72 |
| Example 4 | 7.14 |
| Comparative example 1 | - |
| Comparative example 2 | 1.15 |
| Comparative example 3 | 0.82 |
| Comparative example 4 | 1.08 |
As can be seen from the table, when the stress buffer layer (example 1) of the present invention was added to the conventional light emitting diode structure (comparative example 1), the light emitting efficiency was effectively improved.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.
Claims (10)
1. The LED epitaxial wafer with high light extraction efficiency is characterized by comprising a substrate, and a buffer layer, an N-type GaN layer, a stress buffer layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer which are sequentially laminated on the substrate; the stress buffer layer comprises a first stress buffer layer, a metal reflecting layer and a second stress buffer layer which are sequentially laminated on the N-type GaN layer;
the first stress buffer layer is Si doped with Al a In b Ga 1-a-b An N layer, wherein a is more than or equal to 0 and less than or equal to 0.6,0 and b is more than or equal to 0.2;
the metal reflecting layer is a laminated structure formed by one or more of an Al metal layer, a Ga metal layer, an In metal layer and an Mg metal layer;
the second stress buffer layer is Si doped with Al c In d Ga 1-c-d And N layers, wherein c is more than or equal to 0 and less than or equal to 0.6,0, d is more than or equal to 0.3.
2. The high light extraction efficiency LED epitaxial wafer of claim 1 wherein said first stress buffer layer has a thickness of 50nm to 500nm and a si doping concentration of 2 x 10 17 cm -3 ～2×10 19 cm -3 ；
The thickness of the metal reflecting layer is 2 nm-20 nm;
the thickness of the second stress buffer layer is 30 nm-300 nm, and the doping concentration of Si is 2 multiplied by 10 16 cm -3 ～2×10 18 cm -3 。
3. The LED epitaxial wafer of claim 1, wherein a is greater than or equal to 0.2 and less than or equal to 0.5,0.05 and c is greater than or equal to 0.4, and a > c;
b is more than or equal to 0.04 and less than or equal to 0.1,0.1, d is more than or equal to 0.23, and b is less than d.
4. The LED epitaxial wafer of any one of claims 1 to 3, wherein the multiple quantum well layers have a periodic structure with a period number of 4 to 16, each period including a quantum well layer and a quantum barrier layer;
each quantum well layer comprises a pre-well protective layer, a light-emitting well layer and a post-well protective layer which are sequentially stacked; the pre-well protective layer is In with In composition changing with increasing thickness y Ga 1-y An N layer, the light-emitting well layer is In x Ga 1-x N layer, the protective layer is In whose In component is decreasingly changed along with the thickness increase z Ga 1-z An N layer; wherein x is more than or equal to 0.12 and less than or equal to 0.4, y is more than or equal to 0 and less than or equal to 0.4, and z is more than or equal to 0 and less than or equal to 0.4;
the quantum barrier layer is a GaN layer.
5. The high light extraction efficiency LED epitaxial wafer of claim 4, wherein the pre-well protective layer has a thickness of 0.5nm to 2nm, and an In composition increases from 0to an In composition ratio In the light emitting well layer with the thickness;
the thickness of the light-emitting well layer is 2.5 nm-5 nm;
the thickness of the protective layer after the well is 0.5-2 nm, and the In component of the protective layer is decreased to 0 from the In component duty ratio In the luminescent well layer along with the thickness;
the thickness of the quantum barrier layer is 8 nm-15 nm.
6. The high light extraction efficiency LED epitaxial wafer of claim 4, wherein after the growth of said post-well protection layer is completed, H is used 2 And NH 3 Treating the mixed gas of the post-trap protection layer to coarsen the surface of the post-trap protection layer;
wherein the treatment temperature is 800-950 ℃, the treatment pressure is 100-300 torr, and the treatment time is 20-120 s; h 2 And NH 3 The volume ratio of (2) is 1:3-1:5.
7. A method for producing the LED epitaxial wafer with high light extraction efficiency, which is used for producing the LED epitaxial wafer with high light extraction efficiency according to any one of claims 1 to 6, comprising:
providing a substrate, and sequentially growing a buffer layer, an N-type GaN layer, a stress buffer layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer on the substrate; the stress buffer layer comprises a first stress buffer layer, a metal reflecting layer and a second stress buffer layer which are sequentially laminated on the N-type GaN layer;
the first stress buffer layer is Si doped with Al a In b Ga 1-a-b An N layer, wherein a is more than or equal to 0 and less than or equal to 0.6,0 and b is more than or equal to 0.2;
the metal reflecting layer is a laminated structure formed by one or more of an Al metal layer, a Ga metal layer, an In metal layer and an Mg metal layer;
the second stress buffer layer is Si doped with Al c In d Ga 1-c-d And N layers, wherein c is more than or equal to 0 and less than or equal to 0.6,0, d is more than or equal to 0.3.
8. The method for preparing an LED epitaxial wafer with high light extraction efficiency according to claim 7, wherein the growth temperature of the first stress buffer layer is 800-950 ℃ and the growth pressure is 100-300 torr;
the growth temperature of the metal reflecting layer is 750-1050 ℃, and the growth pressure is 30-500 torr;
the growth temperature of the second stress buffer layer is 780-900 ℃, and the growth pressure is 100-300 torr.
9. The method of manufacturing a high light extraction efficiency LED epitaxial wafer of claim 7 wherein said multiple quantum well layer comprises a quantum well layer and a quantum barrier layer; the quantum well layer comprises a pre-well protective layer, a light-emitting well layer and a post-well protective layer;
the growth temperature of the protective layer before the trap is 700-900 ℃ and the growth pressure is 100-300 torr;
the growth temperature of the light-emitting well layer is 700-850 ℃, and the growth pressure is 100-300 torr;
the growth temperature of the protective layer after the trap is 700-900 ℃ and the growth pressure is 100-300 torr.
10. The method for preparing an LED epitaxial wafer with high light extraction efficiency according to claim 9, wherein the growth temperature is decreased from 900 ℃ to 700 ℃ during the growth of the pre-well protective layer;
in the growth process of the post-trap protection layer, the growth temperature is increased from 700 ℃ to 900 ℃.
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