CN116314176A - Preparation method of low-capacitance low-residual voltage TVS device and TVS device - Google Patents

Preparation method of low-capacitance low-residual voltage TVS device and TVS device Download PDF

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CN116314176A
CN116314176A CN202310055077.8A CN202310055077A CN116314176A CN 116314176 A CN116314176 A CN 116314176A CN 202310055077 A CN202310055077 A CN 202310055077A CN 116314176 A CN116314176 A CN 116314176A
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layer
type
low
tvs device
epitaxial
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张啸
李佳豪
蒋骞苑
赵德益
吕海凤
王允
郝壮壮
胡亚莉
张彩霞
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Shanghai Wei'an Semiconductor Co ltd
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Shanghai Wei'an Semiconductor Co ltd
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Abstract

The invention provides a preparation method of a low-capacitance low-residual voltage TVS device and the TVS device, comprising the following steps: step S1, forming a P-type buried layer in a preset area of an N-type substrate; s2, forming an epitaxial transition layer on the surface, and growing an N-type epitaxial layer on the epitaxial transition layer; s3, forming an SN layer and an SP layer in the N-type epitaxial layer; step S4, etching to form a deep groove in the N-type epitaxial layer, wherein the deep groove is filled with polysilicon in situ and comprises two first deep grooves and two second deep grooves; and S5, depositing a dielectric layer on the surface, etching the contact hole and depositing a metal layer. The beneficial effects are that: the invention creatively adopts an NPN structure, ensures the current capacity of the device by accurately controlling the depth of the isolation deep groove, reduces the clamping voltage and can be widely applied to the protection of various high-speed data transmission ports; and the near-intrinsic high-resistance epitaxy is obtained on the substrate on which the high-concentration P-type buried layer is grown, so that the low capacitance characteristic of the device is ensured.

Description

Preparation method of low-capacitance low-residual voltage TVS device and TVS device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a low-capacitance low-residual voltage TVS device and the TVS device.
Background
Low capacitance low residual voltage transient diode (TVS) devices are widely used for voltage transient and surge protection of high frequency circuits, consisting of low breakdown voltage avalanche diodes and low capacitance switching tubes, where the low capacitance switching tubes require the growth of an approximately intrinsic ultra-high resistivity N-type epitaxial layer on a high concentration P-buried layer and substrate. The chip capacitance and residual voltage are key parameters which must be considered, the capacitance is too large, high-frequency signals are distorted under capacitive load, and the residual voltage has negative influence on the back-end circuit. How to manufacture chips that meet both low capacitance and low residual voltage requirements is a challenge to TVS product development.
As shown in fig. 1, a TVS device with a conventional PNP structure is shown in fig. 2, which is an equivalent circuit schematic diagram of a TVS device with a conventional PNP structure. The breakdown voltage diode Z1 is formed by an SP layer-N type epitaxial layer (Nepi) -N type buried layer-P type substrate (Psub), the residual voltage is higher, the low capacitance switching tube D1 is formed by an SP layer and an N type epitaxial layer, the capacitance is greatly affected by the depth and the side area of the SP junction, and if the process control is not good, the capacitance is larger. Because the DTI deep groove penetrates into the substrate (Psub), a through-flow junction formed by the N-type buried layer and the P-type substrate can only utilize the bottom area of the N-type buried layer, and the through-flow capacity of the TVS device can be limited to a certain extent; besides the DTI deep groove with isolation function, a contact groove is further arranged to be filled at the bottom of the epitaxial layer by a doped polysilicon layer, which inevitably greatly increases the transverse area of the device, is very unfavorable for miniaturized packaging, has higher cost, and is difficult to obtain extremely low device capacitance, so that the application of the device in a high-speed data port is greatly limited. In summary, the TVS device with the conventional PNP structure has the disadvantages of poor current capability, high residual voltage, unstable capacitance, and the like, and is difficult to meet the application requirements of the high-speed data port.
Disclosure of Invention
In order to solve the technical problems, the invention provides a preparation method of a low-capacitance low-residual voltage TVS device and the TVS device.
The technical problems solved by the invention can be realized by adopting the following technical scheme:
a preparation method of a low-capacitance low-residual voltage TVS device comprises the following steps:
step S1, forming a P-type buried layer in a preset area of an N-type substrate;
s2, forming an epitaxial transition layer on the upper surfaces of the N-type substrate and the P-type buried layer, and growing an N-type epitaxial layer on the upper surface of the epitaxial transition layer; wherein, in the growing process of the N-type epitaxial layer, the P-type buried layer is upwards reversed to the N-type epitaxial layer;
s3, forming an SN layer and an SP layer in the N-type epitaxial layer, wherein the SN layer corresponds to the P-type buried layer in the longitudinal direction, and then carrying out high-temperature annealing on the SN layer and the SP layer at the same time;
s4, etching to form a deep groove in the N-type epitaxial layer, and filling polycrystalline silicon in situ in the deep groove, wherein the deep groove comprises two first deep grooves which extend downwards from the upper surface of the N-type epitaxial layer into the P-type buried layer respectively; two second deep grooves extending downwards from the upper surface of the SP layer through the SP layer;
and S5, depositing a dielectric layer on the surface, etching contact holes corresponding to the SN layer and the SP layer, and depositing metal layers in the contact holes respectively.
Preferably, in the step S1, the ion implantation element of the P-type buried layer is B or BF2, the implantation dose is 5E15-1.5E16, and the implantation energy is 60kev-80kev.
Preferably, before the step S2, the method further includes:
and forming a silicon dioxide dielectric layer on the upper surface of the N-type substrate.
Preferably, in the step S2, the resistivity of the N-type epitaxial layer is 200-300 ohm.
Preferably, in the step S2, the thickness of the epitaxial transition layer is 0.3um-2um;
the resistivity of the epitaxial transition layer was 0.5ohm.
Preferably, in the step S3, the ion implantation elements of the SN layer are P and AS, the implantation dose is 1E15-8E15, and the implantation energy is 50kev-80kev;
the ion implantation element of the SP layer is B, the implantation dosage is 1E15-8E15, and the implantation energy is 50kev-80kev;
the annealing temperature is 1100-1150 deg. and the annealing time is 60-90min.
Preferably, in the step S4, a distance between two first deep grooves is 0.3 to 0.5 times a width of the P-type buried layer.
Preferably, in the step S4, the depth of the deep groove is 5um-8um, and the width of the deep groove is 1.2um.
Preferably, the area of the P-type buried layer is larger than the area enclosed by the two first deep grooves.
The invention also provides a low-capacitance low-residual voltage TVS device, which is prepared by the preparation method of the low-capacitance low-residual voltage TVS device, and comprises the following steps:
a P-type buried layer formed in a predetermined region of an N-type substrate;
the epitaxial transition layer is formed on the upper surfaces of the N-type substrate and the P-type buried layer;
the N-type epitaxial layer is formed on the upper surface of the epitaxial transition layer;
an SN layer formed in the N-type epitaxial layer, and corresponding to the P-type buried layer in the longitudinal direction;
an SP layer formed in the N-type epitaxial layer,
the deep grooves are filled with polysilicon in situ, and comprise first deep grooves which extend downwards from the upper surface of the epitaxial layer to the P-type buried layer respectively; the second deep grooves respectively penetrate through the SP layer from the upper surface of the SP layer and extend downwards;
and the dielectric layer is formed on the upper surface of the epitaxial layer, contact holes corresponding to the SN layer and the SP layer are etched, and a metal layer is deposited in the contact holes.
The technical scheme of the invention has the advantages that:
the TVS device creatively forms a unique NPN structure through the SN layer-N epitaxial layer-P buried layer-N substrate, has lower residual voltage and larger through-current capacity compared with the conventional PNP structure formed by the N buried layer, reduces clamping voltage, and can be widely applied to the protection of various high-speed data transmission ports; and obtaining near-intrinsic high-resistance epitaxy on the substrate on which the high-concentration P-type buried layer is grown, thereby ensuring the low capacitance characteristic of the device.
Drawings
Fig. 1 is a schematic diagram of a TVS device of a conventional PNP structure in the prior art;
fig. 2 is an equivalent circuit schematic diagram of a TVS device with a conventional PNP structure in the prior art;
FIGS. 3a-3h are schematic diagrams illustrating steps in a method for fabricating a low capacitance low residual voltage TVS device according to a preferred embodiment of the invention;
fig. 4 is an equivalent schematic diagram of a low-capacitance low-residual voltage TVS device according to a preferred embodiment of the present invention;
fig. 5 is an equivalent circuit schematic diagram of a low-capacitance low-residual voltage TVS device according to a preferred embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.
In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a method for manufacturing a low-capacitance low-residual voltage TVS device is now provided, which belongs to the technical field of semiconductors, as shown in fig. 3a-3h, and includes:
step S1, as shown in FIGS. 3a and 3b, forming a P-type buried layer 2 in a predetermined region of an N-type substrate 1;
firstly, providing an N-type substrate 1, wherein the resistivity of the N-type substrate 1 is smaller than 0.08ohm.cm, and then carrying out photoetching definition and ion implantation of a P-type buried layer 2 in a partial area of the N-type substrate 1.
In a preferred embodiment, in the step S1, the ion implantation element of the P-type buried layer 2 is B or BF2, the implantation dose is 5E15-1.5E16, and the implantation energy is 60kev-80kev.
Furthermore, the width of the P-type buried layer 2 should be set larger, which is favorable for obtaining a diode with larger junction area, and the specific width can be set according to actual devices.
Step S2, as shown in FIG. 3c, an epitaxial transition layer is formed on the upper surfaces of the N-type substrate 1 and the P-type buried layer 2, and an N-type epitaxial layer 3 is grown on the upper surface of the epitaxial transition layer; wherein, in the growth process of the N-type epitaxial layer 3, the P-type buried layer 2 is upwards reflected into the N-type epitaxial layer 3;
specifically, the N-type epitaxial layer 3 is grown on the surface of the N-type substrate 1, and the P-type buried layer 2 is doped with high concentration, and the growth temperature of the high-resistance epitaxy is higher and is generally 1130-1180 ℃, so that the N-type epitaxial transition layer is required to be adopted in the process of growing the high-resistance epitaxy to effectively inhibit the reverse expansion of boron in the P-type buried layer. Meanwhile, in the process of growing the high-resistance epitaxy, the P-type buried layer 2 has a certain upward reflection and can be upward reflected into the N-type epitaxial layer 3.
As a preferred embodiment, before step S2, the method further includes:
and forming a silicon dioxide dielectric layer on the upper surface of the N-type substrate 1.
It is important to note how to grow a high quality almost intrinsic epitaxy on the substrate of the high concentration P-type buried layer 2, which directly affects the capacitance of the device. According to the embodiment of the invention, silicon dioxide and a silicon nitride medium are required to be deposited before the epitaxy is grown to carry out back sealing, so that phosphorus element in the N-type substrate 1 is prevented from diffusing into the substrate in the process of growing the high-resistance epitaxy. And a layer of high-concentration N-type epitaxial transition layer is also grown before the high-resistance epitaxy is grown, so that the back diffusion of boron in the P-type buried layer is effectively inhibited.
As a preferred embodiment, in the step S2, the resistivity of the N-type epitaxial layer 3 is 200-300 ohm.
As a preferred embodiment, in step S2, the thickness of the epitaxial transition layer is 0.3um to 2um;
the resistivity of the epitaxial transition layer was 0.5ohm.
Specifically, how to select the thickness of the proper epitaxial transition layer is also important, the thickness is too thin to press the overflow of boron element in the P-type buried layer, the thickness is too thick, the upper reflection of the P-type buried layer 2 cannot penetrate through the high-concentration N-type epitaxial transition layer, the junction of the low-capacitance switching tube is formed by the P-type buried layer 2 and the N-type transition layer, and compared with the junction formed by the P-type buried layer 2 and the N-type epitaxial layer 3, the junction capacitance is larger, so that a low-capacitance TVS device cannot be formed.
Step S3, as shown in FIGS. 3d, 3e and 3f, forming an SN layer 4 and an SP layer 5 in the N-type epitaxial layer 3, wherein the SN layer 4 corresponds to the P-type buried layer 2 in the longitudinal direction, and then carrying out high-temperature annealing on the SN layer 4 and the SP layer 5 at the same time;
specifically, after photoetching definition is carried out in the N-type epitaxial layer 3, an SN layer 4 is formed through ion implantation, the ion implantation elements of the SN layer 4 are P and AS, the implantation dosage is 1E15-8E15, and the implantation energy is 50kev-80kev;
after photoetching definition is carried out in the N-type epitaxial layer 3, an SP layer 5 is formed through ion implantation, the ion implantation element of the SP layer 5 is B, the implantation dosage is 1E15-8E15, and the implantation energy is 50kev-80kev;
then, the device is sent into a furnace tube, the SP layer 5 and the SN layer 4 are annealed at high temperature, the injected elements are activated, the annealing temperature is 1100-1150 degrees, and the annealing time is 60-90min.
Step S4, as shown in FIG. 3g, etching to form a deep trench in the N-type epitaxial layer 3, and filling polysilicon in situ in the deep trench, wherein the deep trench comprises two first deep trenches 61 respectively extending downwards from the upper surface of the N-type epitaxial layer 3 into the P-type buried layer 2; two second deep grooves 62 extending downward from the upper surface of the SP layer 5 through the SP layer 5, respectively;
specifically, a DTI deep groove is formed in the N-type epitaxial layer 3 through a dry etching process, and after etching, the deep groove is filled with in-situ poly to achieve an isolation effect, compared with SiO 2 The filling stress of in-situ poly is smaller, and the filling effect is better.
As a preferred embodiment, wherein the depth of the deep groove is 5um-8um, the width of the deep groove is 1.2um,
specifically, in order to meet the high requirements of the residual voltage and the current capacity of the TVS device, the embodiment of the present invention needs to specifically control the effective area of the breakdown voltage diode Z1, and after the N-type high-resistance epitaxy is grown, the depth of the DTI isolation deep trench is determined by confirming the degree of upward reverse of the P-type buried layer through slice SEM dyeing, and the requirement is that the depth of the isolation deep trench only needs to be carved through the P-type buried layer 2 just to isolate the P-type buried layer 2, but must not be carved through the P-type buried layer to extend into the N-type substrate.
Further, if the depth of the first deep trench 61 extends into the N-type substrate 1, when current flows from IO2 to IO1, the effective area of the diode Z1 formed by the N-type substrate 1 and the P-type buried layer 2 will be greatly reduced, which not only weakens the current-carrying capability of the device, but also brings about the negative effect of high residual voltage. If the depth of the first deep trench is too shallow, the P-type buried layer 2 cannot be enclosed, the device capacitance becomes large, and the breakdown voltage and leakage of the device are also affected.
As a preferred embodiment, the space between the first deep grooves 61 on two sides of the SN layer 4 is 0.3-0.5 times of the width of the P-type buried layer 2, which is beneficial to obtaining a switching tube with smaller PN junction area.
Specifically, the smaller interval between the first deep grooves 61 on two sides of the SN layer 4 is used for controlling the contact area between the P-type buried layer 2 and the N-type epitaxial layer 3, so that the capacitance of the diode D1 is reduced to the greatest extent, and a TVS device with low capacitance is obtained.
As a preferred embodiment, the area of the P-type buried layer 2 is larger than the area surrounded by the two first deep grooves.
Specifically, the P-type buried layer 2 is reversely more after the N-type epitaxial layer 3 is grown, and the area of the P-type buried layer 2 must be much larger than the area enclosed by DTI deep grooves on two sides of the isolation SN layer 4, so that the effective area of the diode Z1 with breakdown voltage is greatly increased, and the current passing capability of the device is enhanced.
In step S5, as shown in FIG. 3h, a dielectric layer 7 is deposited on the surface, contact holes corresponding to the SN layer 4 and the SP layer 5 are etched, and metal layers 8 are deposited in the contact holes, respectively.
Specifically, a layer of SiO is deposited 2 The thickness of the dielectric layer 7 is 0.6um-0.8um as the dielectric of the contact hole; the contact holes are defined by photoetching and etched by a dry method, metal is deposited to be led out as the electrodes IO1 and IO2, and the metal layer 8 can be ALSiCu, and the thickness is 4um-5um.
The invention also provides a low-capacitance low-residual voltage TVS device, which is prepared by the preparation method of the low-capacitance low-residual voltage TVS device, as shown in FIG. 4, and comprises the following steps:
a P-type buried layer 2 formed in a predetermined region of an N-type substrate 1;
the epitaxial transition layer is formed on the upper surfaces of the N-type substrate 1 and the P-type buried layer 2;
an N-type epitaxial layer 3 formed on the upper surface of the epitaxial transition layer;
an SN layer 4 formed in the N-type epitaxial layer 3, the SN layer 4 corresponding to the P-type buried layer 2 in the longitudinal direction;
an SP layer 5 formed in the N-type epitaxial layer 3,
the deep grooves are filled with polysilicon in situ, and comprise first deep grooves 61 which extend downwards from the upper surface of the N-type epitaxial layer 3 into the P-type buried layer 2 respectively; second deep grooves 62 extending downward from the upper surface of the SP layer 5 through the SP layer 5, respectively;
and a dielectric layer 7 formed on the upper surface of the N-type epitaxial layer 3 and etched with contact holes corresponding to the SN layer 4 and the SP layer 5, and a metal layer 8 is deposited in the contact holes.
In the above preferred embodiment, as shown in fig. 4, an equivalent schematic diagram of the low-capacitance low-residual voltage TVS device manufactured by the embodiment of the present invention is shown; fig. 5 shows a corresponding equivalent circuit schematic diagram. The device consists of a low-capacitance switching tube D1, a low-breakdown-voltage diode Z1 and a low-capacitance switching tube D2, and forms a unique NPN structure through an SN layer 4-N epitaxial layer 3-P buried layer 2-N substrate 1.
The diode Z1 with low breakdown voltage is formed by the bottom and the side surfaces of the N-type substrate 1 and the P-type buried layer 2, the switching tube D1 with low capacitance is formed by the N-type epitaxial layer 3 and the area of the top of the P-type buried layer 2 limited by the two first deep grooves 61, and the switching tube D2 with low capacitance is formed by the SP layer 5 and the N-type epitaxial layer 3; since the width of the P-type buried layer 2 is far greater than the distance between the two first deep grooves 61, the diode Z1 has a larger PN junction area, the PN junction area of the switching tube D1 is smaller, and the junction area of the diode Z1 is more than 3 times of the junction area of the switching tube D1, so that the device is compatible with the dual characteristics of large surge capacity and small parasitic capacitance.
When the first port IO1 applies high potential and the second port IO2 applies low potential, current passes through the N-type epitaxial layer 3 from the SP layer 5 to the N-type substrate 1 and then directly passes through the switching tube D2 to reach the second port IO2; when the second port IO2 applies high potential and the first port IO1 applies low potential, current flows from the N-type substrate 1 to the SN layer 4 through the P-type buried layer 2 and the N-type epitaxial layer 3, and reaches the first port IO1.
The technical scheme has the following advantages or beneficial effects: the TVS device creatively forms a unique NPN structure through the SN layer-N epitaxial layer-P buried layer-N substrate, has lower residual voltage and larger through-current capacity compared with the conventional PNP structure formed by the N buried layer, reduces clamping voltage, and can be widely applied to the protection of various high-speed data transmission ports; and obtaining near-intrinsic high-resistance epitaxy on the substrate on which the high-concentration P-type buried layer is grown, thereby ensuring the low capacitance characteristic of the device.
The foregoing description is only illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the scope of the invention, and it will be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and drawings, and are intended to be included within the scope of the present invention.

Claims (10)

1. The preparation method of the low-capacitance low-residual voltage TVS device is characterized by comprising the following steps:
step S1, forming a P-type buried layer in a preset area of an N-type substrate;
s2, forming an epitaxial transition layer on the upper surfaces of the N-type substrate and the P-type buried layer, and growing an N-type epitaxial layer on the upper surface of the epitaxial transition layer; wherein, in the growing process of the N-type epitaxial layer, the P-type buried layer is upwards reversed to the N-type epitaxial layer;
s3, forming an SN layer and an SP layer in the N-type epitaxial layer, wherein the SN layer corresponds to the P-type buried layer in the longitudinal direction, and then carrying out high-temperature annealing on the SN layer and the SP layer at the same time;
s4, etching to form a deep groove in the N-type epitaxial layer, and filling polycrystalline silicon in situ in the deep groove, wherein the deep groove comprises two first deep grooves which extend downwards from the upper surface of the N-type epitaxial layer into the P-type buried layer respectively; two second deep grooves extending downwards from the upper surface of the SP layer through the SP layer;
and S5, depositing a dielectric layer on the surface, etching contact holes corresponding to the SN layer and the SP layer, and depositing metal layers in the contact holes respectively.
2. The method for manufacturing a TVS device according to claim 1, wherein in step S1, the ion implantation element of the P-type buried layer is B or BF2, the implantation dose is 5E15-1.5E16, and the implantation energy is 60kev-80kev.
3. The method for manufacturing a low-capacitance low-residual voltage TVS device according to claim 1, further comprising, prior to said step S2:
and forming a silicon dioxide dielectric layer on the upper surface of the N-type substrate.
4. The method for manufacturing a TVS device according to claim 1, wherein in said step S2, the resistivity of said N-type epitaxial layer is 200-300 ohm.
5. The method for manufacturing a low-capacitance low-residual voltage TVS device according to claim 1, wherein in said step S2, a thickness of said epitaxial transition layer is 0.3um to 2um;
the resistivity of the epitaxial transition layer was 0.5ohm.
6. The method for manufacturing a low-capacitance low-residual voltage TVS device according to claim 1, wherein in said step S3, the ion implantation elements of the SN layer are P and AS, the implantation dose is 1E15-8E15, and the implantation energy is 50kev-80kev;
the ion implantation element of the SP layer is B, the implantation dosage is 1E15-8E15, and the implantation energy is 50kev-80kev;
the annealing temperature is 1100-1150 deg. and the annealing time is 60-90min.
7. The method for manufacturing a low-capacitance low-residual voltage TVS device according to claim 1, wherein in said step S4, a distance between two of said first deep grooves is 0.3 to 0.5 times a width of said P-type buried layer.
8. The method for manufacturing a low-capacitance low-residual voltage TVS device according to claim 1, wherein in said step S4, the depth of said deep trench is 5um-8um, and the width of said deep trench is 1.2um.
9. The method for manufacturing a low-capacitance low-residual voltage TVS device of claim 1, wherein an area of said P-type buried layer is larger than an area enclosed by two of said first deep trenches.
10. A low-capacitance low-residual voltage TVS device, prepared by the method of any one of claims 1 to 9, comprising:
a P-type buried layer formed in a predetermined region of an N-type substrate;
the epitaxial transition layer is formed on the upper surfaces of the N-type substrate and the P-type buried layer;
the N-type epitaxial layer is formed on the upper surface of the epitaxial transition layer;
an SN layer formed in the N-type epitaxial layer, and corresponding to the P-type buried layer in the longitudinal direction;
an SP layer formed in the N-type epitaxial layer,
the deep grooves are filled with polysilicon in situ, and comprise first deep grooves which extend downwards from the upper surface of the N-type epitaxial layer into the P-type buried layer respectively; the second deep grooves respectively penetrate through the SP layer from the upper surface of the SP layer and extend downwards;
and the dielectric layer is formed on the upper surface of the N-type epitaxial layer, contact holes corresponding to the SN layer and the SP layer are etched, and a metal layer is deposited in the contact holes.
CN202310055077.8A 2023-02-03 2023-02-03 Preparation method of low-capacitance low-residual voltage TVS device and TVS device Pending CN116314176A (en)

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