CN116301181A - Overshoot suppression circuit for load jump of low-dropout linear voltage regulator - Google Patents
Overshoot suppression circuit for load jump of low-dropout linear voltage regulator Download PDFInfo
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F1/63—Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is ac or dc using variable impedances in series with the load as final control devices
Abstract
The application relates to the technical field of integrated circuits and discloses an overshoot suppression circuit for load jump of a low-dropout linear voltage regulator, which comprises the following components: a main load module and a dummy load module. The dummy load module includes: the heavy load-to-light load processing module receives the heavy load-to-light load signal and outputs a narrow pulse signal; the source electrode of the first PMOS transistor is connected with the output end of the low-dropout linear voltage regulator, and the grid electrode of the first PMOS transistor receives a narrow pulse signal; the drain electrode of the first NMOS transistor is connected with the output end of the low-dropout linear voltage regulator, the grid electrode of the first NMOS transistor is connected with the drain electrode of the first PMOS transistor, and the source electrode of the first NMOS transistor is grounded; one end of the first current source is connected with the drain electrode of the first PMOS transistor and the grid electrode of the first NMOS transistor, and the other end of the first current source is grounded; one end of the first capacitor is connected with the grid electrode of the first NMOS transistor, and the other end of the first capacitor is grounded; and a dummy load ending module coupled to the gate of the first NMOS transistor and outputting a dummy load ending signal. When the main load module is changed from heavy load to light load, the pseudo load module enables the load of the low dropout linear voltage regulator not to change drastically.
Description
Technical Field
The present disclosure relates to integrated circuit technology, and more particularly to an overshoot suppression circuit for load jump of a low dropout linear voltage regulator.
Background
The low dropout linear voltage regulator (LDO) in the market at present is mainly divided into an off-chip capacitor and an off-chip capacitor. LDO with off-chip load capacitor has good transient response due to the off-chip capacitor, but the cost of the system is increased by a part due to the off-chip capacitor, and the area of the PCB is enlarged. Because the load capacitance in the LDO without the off-chip capacitor is smaller, the transient response characteristic is poorer, and particularly when the mode is switched, the heavy load mode is switched to the light load mode, and the output of the LDO has high overshoot.
Disclosure of Invention
The purpose of the application is to provide an overshoot suppression circuit for load jump of a low dropout linear voltage regulator, which can prevent overshoot caused by severe load change during load jump of the low dropout linear voltage regulator.
The application discloses overshoot suppression circuit of low dropout linear voltage regulator load jump includes:
the main load module and the pseudo load module are respectively coupled to the output end of the low-dropout linear voltage regulator, when the main load module is changed from heavy load to light load, the pseudo load module receives a heavy load to light load signal, and the load of the pseudo load module is changed from high to low, so that the load of the low-dropout linear voltage regulator does not change drastically;
wherein the dummy load module comprises:
the heavy load-to-light load processing module is used for receiving the heavy load-to-light load signal and outputting a narrow pulse signal;
a source electrode of the first PMOS transistor is connected with the output end of the low-dropout linear voltage regulator, and a grid electrode of the first PMOS transistor receives the narrow pulse signal;
the drain electrode of the first NMOS transistor is connected with the output end of the low-dropout linear voltage regulator, the grid electrode of the first NMOS transistor is connected with the drain electrode of the first PMOS transistor, and the source electrode of the first NMOS transistor is connected with the ground end;
one end of the first current source is connected with the drain electrode of the first PMOS transistor and the grid electrode of the first NMOS transistor, and the other end of the first current source is connected with the ground end;
one end of the first capacitor is connected with the grid electrode of the first NMOS transistor, and the other end of the first capacitor is connected with the ground end; and
and a dummy load ending module coupled to the gate of the first NMOS transistor and outputting a dummy load ending signal to the low dropout linear regulator.
In a preferred embodiment, when the heavy-to-light-load signal is enabled, the heavy-to-light-load processing module generates the narrow pulse signal to the first PMOS transistor, so that the first PMOS transistor is turned on instantaneously, and the drain voltage of the first PMOS transistor and the gate voltage of the first NMOS transistor rise to the output voltage of the low dropout linear regulator.
In a preferred embodiment, the first capacitor is charged to the output voltage of the low dropout linear voltage regulator, the gate voltage of the first NMOS transistor rises to enable the first NMOS transistor to be fully turned on, after the first PMOS transistor is turned off, the first capacitor is discharged through the first current source, after the first capacitor is fully discharged, the gate voltage of the first NMOS transistor drops to zero, and the dummy load ending module outputs the dummy load ending signal to the low dropout linear voltage regulator to complete switching from heavy load to light load.
In a preferred embodiment, the heavy load-to-light load processing module includes: the second PMOS transistor, the second NMOS transistor, the first inverter, the second capacitor, the second current source and the NAND gate;
the gates of the second PMOS transistor and the second NMOS transistor are connected with heavy load-to-light load signals, the drains of the second PMOS transistor and the second NMOS transistor are connected with one end of the second capacitor and the input end of the first inverter, the source of the second PMOS transistor is connected with the second current source, and the source of the second NMOS transistor is connected with the ground end and the other end of the second capacitor;
the input end of the second inverter is connected with the heavy load-light load signal, the output ends of the first inverter and the second inverter are respectively connected with the two input ends of the NAND gate, and the output end of the NAND gate outputs the narrow pulse signal.
In a preferred embodiment, the output end of the first inverter outputs a delayed heavy-to-light load signal, the output end of the second inverter outputs an inverted heavy-to-light load signal, and the nand gate performs nand logic operation on the delayed heavy-to-light load signal and the inverted heavy-to-light load signal and outputs the narrow pulse signal.
In a preferred embodiment, the first inverter is a schmitt inverter.
In a preferred embodiment, the dummy load ending module includes: a third current source, a third NMOS transistor, a third inverter, and a fourth inverter, wherein a drain of the third NMOS transistor is coupled to the third current source and an input terminal of the third inverter, a gate is coupled to a gate of the first NMOS transistor, a source is coupled to the ground, an output terminal of the third inverter is connected to an input terminal of the fourth inverter, and an output terminal of the fourth inverter outputs the dummy load end signal.
In the embodiment of the application, the main load module and the dummy load module are respectively coupled to the output end of the low-dropout linear voltage regulator, when the main load module is changed from heavy load to light load, the dummy load module receives a heavy load-to-light load signal, and the load of the dummy load module is changed from high to low, so that the load of the low-dropout linear voltage regulator does not change drastically, and overshoot caused by the severe load change during load jump of the low-dropout linear voltage regulator is prevented.
In the present application, a number of technical features are described in the specification, and are distributed in each technical solution, which makes the specification too lengthy if all possible combinations of technical features (i.e. technical solutions) of the present application are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the present application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.
Drawings
Fig. 1 is a block diagram of an overshoot suppression circuit for load hops of a low dropout linear regulator according to one embodiment of the present application.
Fig. 2 is a schematic diagram of a pseudo-load module according to one embodiment of the present application.
Fig. 3 is a schematic structural diagram of a heavy load-to-light load processing module according to an embodiment of the present application.
Fig. 4 is a schematic waveform diagram of a heavy-to-light-load processing module according to an embodiment of the present application.
Fig. 5 is a schematic diagram of a pseudo load ending module according to one embodiment of the present application.
FIG. 6 is a waveform diagram of a low dropout linear regulator with a dummy load handling during a load jump according to one embodiment of the present application.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be understood by those skilled in the art that the claimed invention may be practiced without these specific details and with various changes and modifications from the embodiments that follow.
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
One embodiment of the present application relates to an overshoot suppression circuit for load jump of a low dropout linear regulator, the structure of which is shown in fig. 1, and the structure includes: a low dropout linear regulator (LDO) 101, a dummy load module (pre_load) 102, and a Main load module (main_load) 103. The dummy load module (pre_load) 102 and the Main load module (main_load) 103 are coupled to the output terminal Out of the low dropout linear regulator 103, respectively. When the main load module 103 is changed from heavy load to light load, the dummy load module 102 receives the heavy load to light load signal h_l_load and the load of the dummy load module 103 is changed from high to low, so that the load of the low dropout linear regulator 101 does not change drastically. And, the dummy load module 103 outputs a dummy load end signal pre_load end signal to the low dropout linear regulator 101.
Referring to fig. 2, the dummy load module 102 includes a heavy-to-light load processing module (h_l_load_signal_dead-end module) 201, a first PMOS transistor PM1, a first NMOS transistor NM1, a first current source I1, a first capacitor C1, and a dummy load ending module (pre_load_end module) 202. The heavy-to-light-load processing module 201 is configured to receive the heavy-to-light-load signal h_l_load and output a narrow pulse signal Vy. The source of the first PMOS transistor PM1 is connected to the output terminal Out of the low dropout linear regulator 101, and the gate receives the narrow pulse signal Vy. The drain of the first NMOS transistor NM1 is connected to the output terminal Out of the low dropout linear regulator 101, the gate is connected to the drain of the first PMOS transistor PM1, and the source is connected to the ground terminal. One end of the source of the first current I1 is connected with the drain of the first PMOS transistor PM1 and the gate of the first NMOS transistor NM1, and the other end is connected with the ground. One end of the first capacitor C1 is connected to the gate of the first NMOS transistor NM1, and the other end is connected to the ground. The dummy load ending block 202 is coupled to the gate of the first NMOS transistor NM1 and outputs a dummy load ending signal pre_load end signal to the low dropout linear regulator 101.
In one embodiment, when the heavy-to-light load signal h_l_load is enabled, the heavy-to-light load processing module 201 generates the narrow pulse signal Vy to the first PMOS transistor PM1, so that the first PMOS transistor PM1 is turned on instantaneously, the drain voltage of the first PMOS transistor PM1 and the gate voltage of the first NMOS transistor NM1 rise to the output voltage Vout of the low dropout linear regulator 101, and the first capacitor C1 is charged to the output voltage Vout of the low dropout linear regulator 101 and the gate voltage of the first NMOS transistor NM1 rises to make the first NMOS transistor NM1 fully turned on, after the first PMOS transistor NM1 is turned off, the first capacitor C1 is discharged by the first current source I1, after the first capacitor C1 is fully discharged, the gate voltage of the first NMOS transistor NM1 drops to zero, and the dummy load ending module 202 outputs the dummy load ending signal pre_load end signal to the low dropout linear regulator 101 to complete the switching to light load.
The mode conversion signal (heavy load to light load) H_L_load signal is the start signal of the pre_load module, meanwhile, the Main load main_load module is changed from a large load to a light load, the load of the pre_load module is changed from high to low, and the load of the main_load module and the load of the pre_load module are added, so that the overall load of the LDO is not changed drastically at the moment of switching, and the output of the LDO is not subjected to serious overshoot phenomenon. When the load of the pre_load module becomes 0, the pre_load module gives an end signal pre_load end to the LDO to inform the LDO that the mode switching is ended.
The dummy load module Pre_load mainly comprises a heavy load-to-light load processing module, PM1, I1, C1, NM1 and a Pre_load end module. When the heavy load-to-light load signal h_l_load signal is changed from high to low, the gate signal Vy of PM1 is changed from high to low, the Vx point is rapidly increased to Vout, then the gate signal Vy of PM1 is changed to high, PM1 is turned off, vx point discharges through I1 until it becomes 0, in this process, NM1 is turned on from full to low to 0, the dummy load module pre_load is turned off, and at the same time, the pre_load end module gives a high level pre_load end signal to inform the LDO mode conversion end.
Fig. 3 is a schematic structural diagram of a heavy load to light load processing module 201 according to an embodiment of the present application. The heavy load-to-light load processing module includes a second PMOS transistor PM2, a second NMOS transistor NM2, a first inverter INV1, a second inverter INV2, a second capacitor C2, a second current source I2, and a Nand gate Nand. The gates of the second PMOS transistor PM2 and the second NMOS transistor NM2 are both connected to the heavy-to-light-load signal h_l_load, the drains of the second PMOS transistor PM2 and the second NMOS transistor NM2 are connected to one end of the second capacitor C2 and the input end of the first inverter INV1, the source of the second PMOS transistor PM2 is connected to the second current source I2, and the source of the second NMOS transistor NM2 is connected to the ground end and the other end of the second capacitor C2. The input end of the second inverter INV2 is connected with a heavy-to-light-load signal h_l_load, the output ends of the first inverter INV1 and the second inverter INV2 are respectively connected with two input ends of the Nand gate Nand, and the output end of the Nand gate Nand outputs a narrow pulse signal Vy.
In one embodiment, the output end of the first inverter INV1 outputs a delayed reload load signal h_l_load_delay, the output end of the second inverter INV2 outputs an inverted reload load signal h_l_load_signal_n, and the Nand gate Nand performs a Nand logic operation on the delayed reload load signal h_l_load_delay and the inverted reload load signal h_l_load_signal_n and outputs the narrow pulse signal Vy. In one embodiment, the first inverter INV1 is a schmitt inverter.
Referring to fig. 4, when the heavy-to-light-load signal h_l_load signal is changed from high to low, a delay effect is performed on the falling edge signal of the heavy-to-light-load signal h_l_load signal, and a low-level narrow pulse is generated by the Vy signal through logic operation of the falling edge signal, so that the turn-on time of the PM1 tube is very short, the C1 capacitor voltage is flushed to an out voltage value through instant turn-on of the PM1 tube, and then the PM1 tube is turned off rapidly, so that the PM1 tube is not turned on any more. Specifically, when the heavy load-to-light load signal h_l_load signal is changed from high to low, an h_l_load_line signal, which is linearly changed from low to high, is obtained through the second PMOS transistor PM2, the second NMOS transistor NM2, and the second capacitor C2, and the h_l_load_line signal is passed through the first inverter INV1 to obtain a delayed heavy load-to-light load signal h_l_load_delay. The heavy load-to-light load signal H_L_load signal passes through the second inverter INV2 to obtain an inverted heavy load-to-light load signal H_L_load_signal_n, and the Nand logic operation is performed on the delayed heavy load-to-light load signal H_L_load_delay and the inverted heavy load-to-light load signal H_L_load_signal_n to obtain the narrow pulse signal Vy.
Fig. 5 is a schematic diagram of the structure of the dummy load ending module 202 according to one embodiment of the present application. The dummy load ending block includes a third current source I3, a third NMOS transistor NM3, a third inverter INV3, and a fourth inverter INV4. The drain electrode of the third NMOS transistor NM3 is coupled to the third current source I3 and the input terminal of the third inverter INV3, the gate electrode is coupled to the gate electrode of the first NMOS transistor NM1, the source electrode is coupled to the ground terminal, the output terminal of the third inverter INV3 is connected to the input terminal of the fourth inverter INV4, and the output terminal of the fourth inverter INV4 outputs the dummy load end signal pre_load end signal.
When the Vx point in the pseudo-load module is slowly discharged through the first capacitor C1 and the voltage is discharged to 0, the pre_load_end module detects that the Vx signal is changed to 0, namely, the grid voltage of the third NMOS transistor NM3 is changed from high to low, the third NMOS transistor NM3 is closed, a high-level pre_load end signal is generated through the third current source I3 and the inverters INV3 and INV4, the pre_load end signal is output to the LDO module, the LDO module is informed of the end of the conversion from the heavy load mode to the light load mode, the heavy load to light load processing module is completely closed, and the conversion of the pre_load_end module is ended.
Fig. 6 is a waveform diagram of a low dropout linear regulator without spurious load suppression overshoot at load transitions in accordance with one embodiment of the present application. As can be seen from fig. 6, there is a large overshoot in the voltage at the output terminal out without dummy load processing. When the pseudo load processing is adopted, the load of the pre_load module is changed from high to low, the main_load module load and the pre_load module load are added, so that the overall load whole_load of the LDO is gradually reduced, no severe change occurs at the switching moment, and the voltage fluctuation of the output end out is small.
It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.
The term "coupled to" and its derivatives may be used herein. "coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between elements that are referred to as being coupled to each other.
This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated as mutually exclusive or as would be apparent to one of skill in the art, the embodiments are not mutually exclusive. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly indicates otherwise or requires otherwise.
All documents mentioned in the present specification are considered to be included in the disclosure of the present application as a whole, so that they may be regarded as a basis for modification if necessary. Furthermore, it should be understood that the foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.
Claims (7)
1. An overshoot suppression circuit for a load jump of a low dropout linear voltage regulator, comprising:
the main load module and the pseudo load module are respectively coupled to the output end of the low-dropout linear voltage regulator, when the main load module is changed from heavy load to light load, the pseudo load module receives a heavy load to light load signal, and the load of the pseudo load module is changed from high to low, so that the load of the low-dropout linear voltage regulator does not change drastically;
wherein the dummy load module comprises:
the heavy load-to-light load processing module is used for receiving the heavy load-to-light load signal and outputting a narrow pulse signal;
a source electrode of the first PMOS transistor is connected with the output end of the low-dropout linear voltage regulator, and a grid electrode of the first PMOS transistor receives the narrow pulse signal;
the drain electrode of the first NMOS transistor is connected with the output end of the low-dropout linear voltage regulator, the grid electrode of the first NMOS transistor is connected with the drain electrode of the first PMOS transistor, and the source electrode of the first NMOS transistor is connected with the ground end;
one end of the first current source is connected with the drain electrode of the first PMOS transistor and the grid electrode of the first NMOS transistor, and the other end of the first current source is connected with the ground end;
one end of the first capacitor is connected with the grid electrode of the first NMOS transistor, and the other end of the first capacitor is connected with the ground end; and
and a dummy load ending module coupled to the gate of the first NMOS transistor and outputting a dummy load ending signal to the low dropout linear regulator.
2. The overshoot suppression circuit of claim 1, wherein when the heavy-to-light load signal is enabled, the heavy-to-light load processing module generates the narrow pulse signal to the first PMOS transistor such that the first PMOS transistor is turned on instantaneously, and the drain voltage of the first PMOS transistor and the gate voltage of the first NMOS transistor rise to the output voltage of the low dropout linear regulator.
3. The overshoot suppression circuit of claim 2, wherein the first capacitor is charged to an output voltage of the low dropout linear regulator and a gate voltage of the first NMOS transistor rises to fully turn on the first NMOS transistor, the first capacitor is discharged by the first current source after the first PMOS transistor is turned off, and a gate voltage of the first NMOS transistor drops to zero after the first capacitor is fully discharged, and the dummy load ending module outputs the dummy load ending signal to the low dropout linear regulator to complete a heavy load to light load switching.
4. The overshoot suppression circuit of claim 1, wherein the heavy-load-to-light-load processing module comprises: the second PMOS transistor, the second NMOS transistor, the first inverter, the second capacitor, the second current source and the NAND gate;
the gates of the second PMOS transistor and the second NMOS transistor are connected with heavy load-to-light load signals, the drains of the second PMOS transistor and the second NMOS transistor are connected with one end of the second capacitor and the input end of the first inverter, the source of the second PMOS transistor is connected with the second current source, and the source of the second NMOS transistor is connected with the ground end and the other end of the second capacitor;
the input end of the second inverter is connected with the heavy load-light load signal, the output ends of the first inverter and the second inverter are respectively connected with the two input ends of the NAND gate, and the output end of the NAND gate outputs the narrow pulse signal.
5. The overshoot suppression circuit of claim 4, wherein the output terminal of the first inverter outputs a delayed heavy-to-light load signal, the output terminal of the second inverter outputs an inverted heavy-to-light load signal, and the nand gate performs a nand logic operation on the delayed heavy-to-light load signal and the inverted heavy-to-light load signal and outputs the narrow pulse signal.
6. The overshoot suppression circuit of claim 4 wherein the first inverter is a schmitt inverter.
7. The overshoot suppression circuit of claim 1, wherein the dummy load ending module comprises: a third current source, a third NMOS transistor, a third inverter, and a fourth inverter, wherein a drain of the third NMOS transistor is coupled to the third current source and an input terminal of the third inverter, a gate is coupled to a gate of the first NMOS transistor, a source is coupled to the ground, an output terminal of the third inverter is connected to an input terminal of the fourth inverter, and an output terminal of the fourth inverter outputs the dummy load end signal.
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| JP2015018364A (en) * | 2013-07-10 | 2015-01-29 | スパンション エルエルシー | Power supply device and semiconductor device |
| US20150198960A1 (en) * | 2014-01-14 | 2015-07-16 | Broadcom Corporation | Low-power low-dropout voltage regulators with high power supply rejection and fast settling performance |
| CN104407662A (en) * | 2014-11-21 | 2015-03-11 | 电子科技大学 | Light-load transient enhanced circuit and low-voltage-difference linear voltage stabilizer integrated with circuit |
| CN105807831A (en) * | 2014-12-30 | 2016-07-27 | 展讯通信（上海）有限公司 | Linear voltage regulator and linear voltage stabilizing system preventing overshoot |
| US20180164843A1 (en) * | 2016-12-13 | 2018-06-14 | University Of Electronic Science And Technology Of China | Linear regulator with real-time frequency compensation function |
| CN108803764A (en) * | 2018-06-25 | 2018-11-13 | 电子科技大学 | A kind of LDO circuit of fast transient response |
| CN114008555A (en) * | 2020-03-18 | 2022-02-01 | 理光微电子株式会社 | Power supply device and electronic apparatus |
| CN114647271A (en) * | 2022-05-23 | 2022-06-21 | 芯海科技（深圳）股份有限公司 | LDO circuit, control method, chip and electronic equipment |
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Address after: Room 301, No. 54, Lane 565, Shengxia Road, China (Shanghai) Pilot Free Trade Zone, Pudong New Area, Shanghai, March 2012 Patentee after: SHANGHAI MINDMOTION MICROELECTRONICS CO.,LTD. Address before: Room 301, building 10, 399 Keyuan Road, Zhangjiang Town, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 201203 Patentee before: SHANGHAI MINDMOTION MICROELECTRONICS CO.,LTD. |
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