CN116298481A - Ultra-low power consumption overvoltage detection circuit - Google Patents
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- CN116298481A CN116298481A CN202310561207.5A CN202310561207A CN116298481A CN 116298481 A CN116298481 A CN 116298481A CN 202310561207 A CN202310561207 A CN 202310561207A CN 116298481 A CN116298481 A CN 116298481A
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Abstract
The invention relates to an ultra-low power consumption overvoltage detection circuit, and belongs to the technical field of integrated circuits. The low-power consumption overvoltage detection circuit comprises: the device comprises an OVP detection circuit, a VIN voltage division signal control circuit and an overvoltage comparator control circuit. The invention is mainly applied to an overvoltage detection circuit of an input signal VIN, and the purpose of reducing power consumption is realized by controlling the VIN voltage division signal circuit and the OVP comparator circuit to be started only near an overvoltage point and reducing the leakage current of the VIN signal and the static current of a power supply.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to the technical field of integrated circuits, and specifically relates to an ultra-low power consumption overvoltage detection circuit.
Background
With the development of radio technology, various portable, wirelessly chargeable mobile devices are becoming more and more popular. These portable intelligent devices are small in size and low in battery capacity. In order to prevent short-circuit surge caused by various hot plug in the use process of the chip, an OVP detection circuit (overvoltage detection circuit) is often required to be built in to detect whether an input VIN signal is overvoltage or not, and the circuit is turned off in time, so that the effect of protecting the circuit from damaging the chip is achieved. However, due to the objective reasons of small volume, limited battery capacity and the like, the service life of the chip is shortened after the OVP detection circuit is increased.
The US patent application of patent No. US005896324a discloses a conventional OVP overvoltage detection circuit, which is composed of circuit components shown in fig. 2. The module b comparator is a comparator with EN enabling, and when EN is high, the comparator works, and when EN is low and high, the comparator is turned off; when the EN signal is in a high level, the NMOS switch tube S11 is opened, the node a takes the voltage division value Va and the Vbg_cmp reference voltage to send into the comparator of the module b for comparison, and when the input signal VIN is larger than the OVP voltage, va is larger than the Vbg_cmp, so that overvoltage detection of the VIN input signal is completed. As is known from patent US005896324a, when the external signal is ready, the EN signal is immediately set high, the overvoltage detection sub-circuit starts to operate, at this time, a direct current path exists from the voltage dividing resistor at the left side of the circuit to GND, and a leakage current (leakage current) exists in the VIN input signal, so that energy is consumed; the comparator of the module b on the right side of the circuit is in a normally open state, and consumes the energy of the power supply VDD.
Therefore, how to provide an OVP overvoltage detection circuit with low power consumption, so that the circuit does not consume energy before an overvoltage point, thereby reducing the leakage current of the input signal VIN and the power consumption of the overall circuit power supply VDD, which is a problem to be solved in the art.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide an ultra-low power consumption overvoltage detection circuit so as to solve the problems that the existing overvoltage detection circuit is overlarge in power consumption and has input voltage leakage current.
In order to achieve the above object, an ultra-low power consumption overvoltage detection circuit of the present invention has the following constitution:
it comprises the following steps: an overvoltage detection sub-circuit, a voltage division control sub-circuit and an overvoltage comparator control sub-circuit.
The voltage division control sub-circuit controls the on and off of the voltage division circuit of the input voltage VIN, the overvoltage comparator control sub-circuit controls the on and off of the comparator in the overvoltage detection sub-circuit, and the operating states of the voltage division control sub-circuit and the overvoltage comparator control sub-circuit are controlled to further control the on of the overvoltage detection sub-circuit only near an overvoltage point.
In the ultra-low power consumption overvoltage detection circuit, the overvoltage detection sub-circuit comprises a first input signal Vbg_cmp; the circuit also comprises a first voltage dividing resistor R1; the upper end of the first voltage dividing resistor R1 is connected with the input voltage VIN signal; the lower end of the first divider resistor R1 is connected with the drain electrode of the high-voltage NLDMOS tube N1; the grid electrode of the high-voltage NLDMOS tube N1 is connected with the power supply voltage VDD, and the source electrode of the high-voltage NLDMOS tube N1 is respectively connected with the upper end of the second voltage dividing resistor R2 and the drain electrode of the fourth NMOS switch tube S4; the source electrode of the fourth NMOS switch tube S4 is connected with the positive input end of the comparator 10; the negative input end of the comparator 10 is connected with a first input signal Vbg_cmp; the output of the comparator 10 generates an output signal ovp_output.
In the ultra-low power consumption overvoltage detection circuit, the voltage division control sub-circuit comprises a second input signal Vbg_ OVP and a third input signal OVP_eH; the voltage division control sub-circuit (VIN voltage division control sub-circuit) comprises a high-voltage PLDMOS tube P1; the gate of the high-voltage PLDMOS transistor P1 is connected to the second input signal vbgp_ ovp, and the second input signal vbgp_ ovp is a reference voltage lower than the overvoltage point; the source electrode of the high-voltage PLDMOS tube P1 is connected with the lower end of the third resistor R3; the drain electrode of the high-voltage PLDMOS tube P1 is respectively connected with the upper end of the current limiting resistor R4, the upper end of the voltage margin module 11 and the drain electrode of the third NMOS switch tube S3; the upper end of the third resistor R3 is connected with the input voltage VIN; the lower end of the current limiting resistor R4 and the lower end of the voltage margin module 11 are grounded to GND, and the grid electrode of the third NMOS switch tube S3 is connected with the third input signal OVP_eH; the source electrode of the third NMOS switch tube S3 is grounded GND; when the third input signal ovp_eh is at low level and the input voltage VIN is greater than or equal to the overvoltage point VOVP or less than the overvoltage point VOVP within a range, the overvoltage detection sub-circuit is turned on.
In the ultra-low power consumption overvoltage detection circuit, the overvoltage comparator control sub-circuit comprises a first NMOS switching tube S1; the grid electrode of the first NMOS switch tube S1 is respectively connected with the grid electrode of the second NMOS switch tube S2 and the drain electrode of the third NMOS switch tube S3, and the drain electrode of the NMOS switch tube S1 is connected with the lower end of the second voltage-dividing resistor R2; the source electrode of the first NMOS switch tube S1 is grounded GND; the drain electrode of the second NMOS switch tube S2 is connected with the lower end of the fifth current limiting resistor R5 and the input end of the first reverse function digital logic unit 7; the output end of the first reverse function digital logic unit 7 is respectively connected with the input end of the second reverse function digital logic unit 8 and the grid electrode of the fourth NMOS switch tube S4; the output end of the second reverse function digital logic unit 8 is respectively connected with the grid electrode of the fifth NMOS switch tube S5 and the input end of the delay function module 9; the output end of the delay function module 9 is connected with the EN control end of the comparator 10; the drain electrode of the fifth NMOS switch tube S5 is connected with the source electrode of the fourth NMOS switch tube S4; the source electrode of the fifth NMOS switch transistor S5 is grounded GND.
By adopting the ultra-low power consumption overvoltage detection circuit, the VIN voltage division signal circuit and the OVP comparator circuit are controlled to be started only near an overvoltage point, so that the leakage current (leakage current) of the VIN signal and the quiescent current of a power supply are reduced, and the purpose of reducing power consumption is realized.
Drawings
FIG. 1 is a schematic block diagram of an ultra-low power consumption overvoltage detection circuit of the present invention;
FIG. 2 is a schematic circuit diagram of a conventional overvoltage detection sub-circuit;
FIG. 3 is a schematic diagram of an ultra-low power consumption overvoltage detection circuit according to the present invention;
FIG. 4 is a schematic diagram of simulation comparison of VDD voltage of the ultra-low power consumption overvoltage detection circuit according to the present invention in different operation intervals;
fig. 5 is a schematic diagram of simulation comparison of leakage current of an input signal of an ultra-low power consumption overvoltage detection circuit VIN according to the present invention in different operation regions.
Detailed Description
In order to make the technical contents of the present invention more clearly understood, the following examples are specifically described.
An embodiment of the present invention provides an ultra-low power consumption overvoltage detection circuit described with reference to fig. 1 and 3.
In one embodiment, the ultra-low power consumption overvoltage detection circuit includes as shown in fig. 1: an overvoltage detection sub-circuit (OVP detection circuit), a voltage division control sub-circuit (VIN voltage division signal control circuit), and an overvoltage comparator control sub-circuit (OVP comparator control circuit).
The voltage division control sub-circuit controls the on and off of the voltage division circuit of the input voltage VIN, the overvoltage comparator control sub-circuit controls the turn-off and on of the comparator in the overvoltage detection sub-circuit, and the operating states of the voltage division control sub-circuit and the overvoltage comparator control sub-circuit are controlled to further control the turn-on of the overvoltage detection sub-circuit only near an overvoltage point.
In a specific embodiment, the overvoltage detection subcircuit includes a first input signal vbgp_cmp; the circuit also comprises a first voltage dividing resistor R1; the upper end of the first voltage dividing resistor R1 is connected with the input voltage VIN signal; the lower end of the first divider resistor R1 is connected with the drain electrode of the high-voltage NLDMOS tube N1; the grid electrode of the high-voltage NLDMOS tube N1 is connected with the power supply voltage VDD, and the source electrode of the high-voltage NLDMOS tube N1 is respectively connected with the upper end of the second voltage dividing resistor R2 and the drain electrode of the fourth NMOS switch tube S4; the source electrode of the fourth NMOS switch tube S4 is connected with the positive input end of the comparator 10; the negative input end of the comparator 10 is connected with a first input signal Vbg_cmp; the output of the comparator 10 generates an output signal ovp_output.
The voltage division control sub-circuit comprises a second input signal Vbg_ OVP and a third input signal OVP_eH; the voltage division control sub-circuit comprises a high-voltage PLDMOS tube P1; the gate of the high-voltage PLDMOS transistor P1 is connected to the second input signal vbgp_ ovp, and the second input signal vbgp_ ovp is a reference voltage lower than the overvoltage point; the source electrode of the high-voltage PLDMOS tube P1 is connected with the lower end of the third resistor R3; the drain electrode of the high-voltage PLDMOS tube P1 is respectively connected with the upper end of the current limiting resistor R4, the upper end of the voltage margin module 11 and the drain electrode of the third NMOS switch tube S3; the upper end of the third resistor R3 is connected with the input voltage VIN; the lower end of the current limiting resistor R4 and the lower end of the voltage margin module 11 are grounded to GND, and the grid electrode of the third NMOS switch tube S3 is connected with the third input signal OVP_eH; the source electrode of the third NMOS switch tube S3 is grounded GND; when the third input signal ovp_eh is at low level and the input voltage VIN is greater than or equal to the overvoltage point VOVP or less than the overvoltage point VOVP within a range, the overvoltage detection sub-circuit is turned on.
The overvoltage comparator control sub-circuit comprises a first NMOS switching tube S1; the grid electrode of the first NMOS switch tube S1 is respectively connected with the grid electrode of the second NMOS switch tube S2 and the drain electrode of the third NMOS switch tube S3, and the drain electrode of the NMOS switch tube S1 is connected with the lower end of the second voltage-dividing resistor R2; the source electrode of the first NMOS switch tube S1 is grounded GND; the drain electrode of the second NMOS switch tube S2 is connected with the lower end of the fifth current limiting resistor R5 and the input end of the first reverse function digital logic unit 7; the output end of the first reverse function digital logic unit 7 is respectively connected with the input end of the second reverse function digital logic unit 8 and the grid electrode of the fourth NMOS switch tube S4; the output end of the second reverse function digital logic unit 8 is respectively connected with the grid electrode of the fifth NMOS switch tube S5 and the input end of the delay function module 9; the output end of the delay function module 9 is connected with the EN control end of the comparator 10; the drain electrode of the fifth NMOS switch tube S5 is connected with the source electrode of the fourth NMOS switch tube S4; the source electrode of the fifth NMOS switch transistor S5 is grounded GND.
In a specific application, as shown in fig. 3, the module 10 is a comparator with an enable control terminal, and the comparator is operated at a low level and is not operated at a high level when the EN control terminal is turned off. The PMOS transistor P1 is a high-voltage PLDMOS transistor, and the gate signal vbgp_ OVP is a reference voltage lower than the OVP overvoltage point 1V, that is, vbgp_ OVP =vovp-1; the turn-on threshold voltage VTHP of the PMOS tube is approximately equal to 0.7V. The N1 tube is a high-voltage-resistant NLDMOS tube, and the grid signal of the N1 tube is connected with a VDD power supply, so that the source output voltage of the N1 tube is lower than VDD, and the switching tubes S1 and S4 are low-voltage switching tubes and are not damaged.
In the use process of the ultra-low power consumption overvoltage detection circuit, when a third input signal OVP_eH is high level and VIN is smaller than VOVP-0.7, a P1 pipe is closed, a switching pipe S3 is opened, a node 2 is pulled down, V2 is low level, and switching pipes S1 and S2 are closed; the open-drain output structure formed by R5 and the switch tube S2 outputs a high level, namely the level V3 of the node 3 is a high level; v3 outputs a low level through the inverter 6 with the reverse function, namely the voltage V4 of the node 4 is a low level, and the switching tube S4 is closed at the moment; level V4 outputs a high level, i.e., node 5 level V5 is a high level, through inverter 7 having an inverting function, and S5 is turned on to pull node 6 low, i.e., node 6 level V6 is a low level; the level V5 outputs a high level through a delay (delay) module 9, namely the EN signal is high level, and the comparator is closed and does not work at the moment; the whole process has no direct current path, and the circuit does not consume energy.
When OVP_eH is high level and VIN is more than VOVP-0.7, the P1 pipe is opened, the switch pipe S3 is opened, the node 2 is pulled down, V2 is low level, the switch pipes S1 and S2 are closed, the resistance value of R4 is a resistance above 1 megaohm, and at the moment, the direct current path from VIN to GND through P1 and R4 consumes little energy; the open-drain output structure formed by R5 and the switch tube S2 outputs a high level, namely the level V3 of the node 3 is a high level; v3 outputs a low level through the inverter 6 with the reverse function, namely the voltage V4 of the node 4 is a low level, and the switching tube S4 is closed at the moment; level V4 outputs a high level, i.e., node 5 level V5 is a high level, through inverter 7 having an inverting function, and S5 is turned on to pull node 6 low, i.e., node 6 level V6 is a low level; the level V5 outputs a high level through a delay (delay) module 9, namely the EN signal is high level, and the comparator is closed and does not work at the moment; the whole process has no direct current path, and the circuit consumes little energy.
When OVP_eH is low level, the switch tube S3 is turned off; when VIN is less than VOVP-0.7, the P1 pipe is closed, the node 2 is at a low level, and therefore the switching pipes S1 and S2 are closed; the open-drain output structure formed by R5 and the switch tube S2 outputs a high level, namely the level V3 of the node 3 is a high level; v3 outputs a low level through the inverter 6 with the reverse function, namely the voltage V4 of the node 4 is a low level, and the switching tube S4 is closed at the moment; level V4 outputs a high level, i.e., node 5 level V5 is a high level, through inverter 7 having an inverting function, and S5 is turned on to pull node 6 low, i.e., node 6 level V6 is a low level; the level V5 outputs a high level through a delay (delay) module 9, namely the EN signal is high level, and the comparator is closed and does not work at the moment; the whole process has no direct current path, and the circuit does not consume energy.
When OVP_eH is low level, the switch tube S3 is turned off; when VIN is larger than VOVP-0.7, the P1 pipe is opened; because of the existence of the 11 voltage margin module, the voltage V2 of the node 2 is higher than the threshold voltage VTH of one MOS tube and is smaller than Vgsmax, so that the switching tubes S1 and S2 can be normally opened without being damaged; the voltage division network formed by R2 and R1 outputs a voltage division value V1, and the open drain output structure formed by R5 and the switch tube S2 outputs a low level, namely the level V3 of the node 3 is a low level; v3 outputs high level through the inverter 6 with reverse function, namely the voltage V4 of the node 4 is high level, and the switch tube S4 is opened at the moment; v1 is transmitted to the node 6 through the switching tube S4; level V4 is output low level through inverter 7 with inverting function, i.e. node 5 level V5 is low level, at which time S5 is turned off; the level V5 is fed through a delay block 9, outputting a low level,
i.e. EN signal is low, the comparator is turned on; the voltage division value V6 and the Vbg_cmp reference voltage are sent to the comparator module 10 for comparison, and the result Output is Output;
in summary, as shown in fig. 4 and 5, the low-power overvoltage detection circuit provided by the present invention only has the control signal ovp_eh at low level, and consumes larger VDD energy when VIN > VOVP-0.7, otherwise does not consume VDD energy, and can also effectively reduce the leakage current of VIN signal.
In fig. 3, the resistances R1, R2, R4, and R5 have resistance values of 1 mega ohm or more, and perform a current limiting function. The modules 7, 8 include, but are not limited to, digital logic cells such as inverters, nand gates, nor gates, etc. that can provide a reverse action. The module 9 includes, but is not limited to, a buffer, an RC delay circuit, and other circuit units that can provide a delay effect. Module 11 voltage margin module M includes, but is not limited to, diodes that can provide voltage margin, diode-connected BJTs or MOS transistors, and the like. Each switching tube S includes, but is not limited to, a MOS tube that can perform a switching function through voltage control, and may also be a BJT that performs a switching function through voltage control, or the like.
In this specification, the invention has been described with reference to specific embodiments thereof. It will be apparent, however, that various modifications and changes may be made without departing from the spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (4)
1. An ultra-low power consumption overvoltage detection circuit, comprising: an overvoltage detection sub-circuit, a voltage division control sub-circuit and an overvoltage comparator control sub-circuit;
the voltage division control sub-circuit controls the on and off of the voltage division circuit of the input Voltage (VIN),
the overvoltage comparator control sub-circuit controls the turn-off and turn-on of the comparator in the overvoltage detection sub-circuit,
the operating states of the voltage division control sub-circuit and the overvoltage comparator control sub-circuit are controlled, so that the overvoltage detection sub-circuit is controlled to be started only near an overvoltage point.
2. The ultra-low power consumption overvoltage detection circuit according to claim 1, wherein,
the overvoltage detection subcircuit includes a first input signal (vbgp_cmp);
the overvoltage detection subcircuit also comprises a first voltage dividing resistor (R1);
the upper end of the first voltage dividing resistor (R1) is connected with the input Voltage (VIN) signal; the lower end of the first voltage dividing resistor (R1) is connected with the drain electrode of the high-voltage NLDMOS tube (N1);
the grid electrode of the high-voltage NLDMOS tube (N1) is connected with the power supply Voltage (VDD), and the source electrode of the high-voltage NLDMOS tube (N1) is respectively connected with the upper end of the second voltage dividing resistor (R2) and the drain electrode of the fourth NMOS switch tube (S4);
the source electrode of the fourth NMOS switch tube (S4) is connected with the positive input end of the comparator (10);
the negative input end of the comparator (10) is connected with a first input signal (Vbg_cmp); the output of the comparator (10) generates an output signal (ovp_output).
3. The ultra-low power consumption overvoltage detection circuit according to claim 2, wherein,
the voltage division control sub-circuit comprises a second input signal (Vbg_ OVP) and a third input signal (OVP_eH);
the voltage division control sub-circuit comprises a high-voltage PLDMOS tube (P1); the grid electrode of the high-voltage PLDMOS tube (P1) is connected with the second input signal (Vbg_ ovp), and the second input signal (Vbg_ ovp) is a base reference voltage lower than an overvoltage point;
the source electrode of the high-voltage PLDMOS tube (P1) is connected with the lower end of the third resistor (R3); the drain electrode of the high-voltage PLDMOS tube (P1) is respectively connected with the upper end of the current limiting resistor (R4), the upper end of the voltage margin module (11) and the drain electrode of the third NMOS switch tube (S3);
the upper end of the third resistor (R3) is connected with an input Voltage (VIN);
the lower end of the current limiting resistor (R4) and the lower end of the voltage margin module (11) are Grounded (GND);
the grid electrode of the third NMOS switch tube (S3) is connected with the third input signal (OVP_eH); the source electrode of the third NMOS switch tube (S3) is Grounded (GND);
when the third input signal (ovp_eh) is at a low level and the input Voltage (VIN) is greater than or equal to the over-voltage point (VOVP) or less than the over-voltage point (VOVP) within a range, the over-voltage detection sub-circuit is turned on.
4. The ultra-low power consumption overvoltage detection circuit according to claim 3, wherein,
the overvoltage comparator control sub-circuit comprises a first NMOS switch tube (S1); the grid electrode of the first NMOS switch tube (S1) is respectively connected with the grid electrode of the second NMOS switch tube (S2) and the drain electrode of the third NMOS switch tube (S3), and the drain electrode of the NMOS switch tube (S1) is connected with the lower end of the second voltage-dividing resistor (R2); the source electrode of the first NMOS switch tube (S1) is Grounded (GND);
the drain electrode of the second NMOS switch tube (S2) is connected with the lower end of the fifth current limiting resistor (R5) and the input end of the first reverse function digital logic unit (7); the source electrode of the second NMOS switch tube (S2) is Grounded (GND);
the upper end of the fifth resistor (R5) is connected with a power supply Voltage (VDD);
the output end of the first reverse function digital logic unit (7) is respectively connected with the input end of the second reverse function digital logic unit (8) and the grid electrode of the fourth NMOS switch tube (S4);
the output end of the second reverse function digital logic unit (8) is respectively connected with the grid electrode of the fifth NMOS switch tube (S5) and the input end of the delay function module (9);
the output end of the delay function module (9) is connected with the EN control end of the comparator (10);
the drain electrode of the fifth NMOS switch tube (S5) is connected with the source electrode of the fourth NMOS switch tube (S4); the source electrode of the fifth NMOS switch tube (S5) is Grounded (GND).
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| CN117133211A (en) * | 2023-10-25 | 2023-11-28 | 无锡力芯微电子股份有限公司 | Low-cost test circuit and method for LCD lattice drive integrated circuit |
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| CN117133211A (en) * | 2023-10-25 | 2023-11-28 | 无锡力芯微电子股份有限公司 | Low-cost test circuit and method for LCD lattice drive integrated circuit |
| CN117133211B (en) * | 2023-10-25 | 2024-01-16 | 无锡力芯微电子股份有限公司 | Low-cost test circuit and method for LCD lattice drive integrated circuit |
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| CN116298481B (en) | 2023-08-15 |
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