CN116230625A

CN116230625A - Semiconductor structure and forming method thereof

Info

Publication number: CN116230625A
Application number: CN202210299229.4A
Authority: CN
Inventors: 陈柏安
Original assignee: Nuvoton Technology Corp
Current assignee: Nuvoton Technology Corp
Priority date: 2021-12-06
Filing date: 2022-03-25
Publication date: 2023-06-06
Also published as: TWI819425B; TW202324502A

Abstract

The invention provides a semiconductor structure and a forming method thereof. The method for forming the semiconductor structure comprises the following steps: a first epitaxial layer is formed on a substrate. A first recess is formed in the first epitaxial layer. A first dielectric layer is formed in the first recess. A first conductive layer is formed on the first dielectric layer. A second epitaxial layer is formed on the first epitaxial layer. A gate dielectric layer is similarly formed over the second epitaxial layer. A gate electrode is formed on the gate dielectric layer. The invention can reduce the depth-to-width ratio of the groove and improve the reliability of the component.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to semiconductor structures and methods of forming the same, and more particularly to semiconductor structures with excellent reliability and methods of forming the same.

Background

With the evolution of the age, metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are continually innovated from planar MOSFETs, super-junction MOSFETs, trench MOSFETs to shielded gate trench MOSFETs (shielded gate trench MOSFETs, SGT-MOSFETs) to meet more and lessThe same requirement. The trench MOSFET has a trench structure for accommodating a vertical gate electrode, thereby enabling device size reduction with smaller device pitch and lower gate-to-drain capacitance (C _gd ) Can effectively reduce the on-resistance (R _on ) And switching loss (switching loss). Furthermore, because the SGT-MOSFET includes a source electrode that is a shield electrode, the SGT-MOSFET can achieve lower on-resistance and lower switching losses based on charge balancing techniques.

However, as the use requirements increase, transistors are expected to have smaller dimensions to increase integration density. However, if the transistor is required to be reduced in size, the width of the trench is generally required to be reduced correspondingly, and the aspect ratio is also increased with the reduction of the trench width, which causes a problem of difficult manufacture.

Thus, while existing semiconductor structures and methods of forming them have been increasingly satisfactory for their intended use, they have not been thoroughly satisfactory in all respects. Accordingly, there are still problems to be overcome with respect to semiconductor structures that can be used as SGT-MOSFETs after further processing and methods of forming the same.

Disclosure of Invention

In view of the foregoing, the first epitaxial layer and the second epitaxial layer are sequentially and independently arranged to reduce the aspect ratio of the trench, and parameters such as thickness, doping concentration and the like of the first epitaxial layer and the second epitaxial layer are matched and adjusted at the same time, so that the reliability of the conductive material filled in the trench is improved. For example, one or any combination of undesirable structures such as voids (void), holes (hole), seam defects (seam defect), recesses, etc. in the conductive material filling the trench can be reduced and/or avoided to enhance the reliability and electrical performance of the subsequently formed SGT-MOSFET.

According to some embodiments, methods of forming semiconductor structures are provided. The method for forming the semiconductor structure comprises the following steps: a first epitaxial layer is formed on a substrate. A first recess is formed in the first epitaxial layer. A first dielectric layer is formed in the first recess. A first conductive layer is formed on the first dielectric layer. A second epitaxial layer is formed on the first epitaxial layer. A gate dielectric layer is similarly formed over the second epitaxial layer. A gate electrode is formed on the gate dielectric layer.

According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes: the semiconductor device comprises a substrate, a first epitaxial layer, a first dielectric layer, a first conductive layer, a second epitaxial layer, a gate dielectric layer, a gate electrode and a semiconductor layer. The substrate has a first conductivity type. The first epitaxial layer has a first conductivity type. The first epitaxial layer is disposed on the substrate and includes a first recess. The first dielectric layer is disposed in the first recess. The first conductive layer is disposed on the first dielectric layer. The second epitaxial layer has the first conductivity type. The second epitaxial layer is disposed on the first epitaxial layer and includes a second recess. The gate dielectric layer is disposed in the second recess. The gate electrode is disposed on the gate dielectric layer. The semiconductor layer has a second conductivity type different from the first conductivity type. The semiconductor layer is disposed in the second epitaxial layer and is not disposed in the second recess.

The semiconductor structure of the present invention can be applied to various types of semiconductor devices, and in order to make the components and advantages of the present invention more obvious, preferred embodiments are described below in detail with reference to the accompanying drawings.

Drawings

The aspects of the embodiments of the present invention will be better understood by reference to the following detailed description taken in conjunction with the accompanying drawings. It is noted that some components (features) may not be drawn to scale according to industry standard practices. In fact, the dimensions of the various features may be increased or decreased for clarity of discussion.

Fig. 1-14 are schematic cross-sectional views illustrating the formation of a semiconductor structure at various stages in accordance with some embodiments of the invention.

Reference numerals:

1: a semiconductor structure;

100: a substrate;

200: a first epitaxial layer;

201: a first concave portion;

202: a first trench;

210: a first dielectric layer;

300: a first conductive material;

310: a first conductive layer;

400: a second epitaxial layer;

401: a second concave portion;

402: a second trench;

410: a second dielectric layer;

420: a gate dielectric layer;

500: a second conductive material;

510: a gate electrode;

600: a semiconductor layer;

610: a first doped region;

620: a second doped region;

700: an interlayer dielectric layer;

800: a contact;

900: a metal layer;

d1: a first depth;

d2: a second depth;

d3: a third depth;

d4: a fourth depth;

t1: a first thickness;

t2: a second thickness;

w1: a first width;

w2: a second width;

w3: a third width;

w4: and a fourth width.

Detailed Description

Many different embodiments or examples are provided below for implementing the different components of the provided semiconductor structures. Specific examples of the components and their configurations are described below to simplify the present embodiments. These are, of course, merely examples and are not intended to limit the invention from that described above. For example, references to a first element being formed on a second element may include embodiments in which the first element and the second element are in direct contact, and may include embodiments in which additional elements are formed between the first element and the second element such that they are not in direct contact. In addition, embodiments of the present invention may repeat device symbols and/or characters in different examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or aspects discussed.

Some variations of the embodiments are described below. In the various drawings and illustrated embodiments, like reference numerals are used to designate like elements. It is to be understood that additional operations may be provided before, during, and after the methods, and that some of the described operations may be substituted or deleted for the other embodiments of the methods described above.

Furthermore, spatially relative terms such as "above …," "under …," "above …," "below …," and the like may be used to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is turned to other orientations (90 degrees or other orientations), the spatially relative descriptors used herein interpreted accordingly. Herein, "about," "substantially," or the like generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the numbers provided in the specification are about numbers, i.e., without a specific description of "about", "substantially" or the like, the meaning of "about", "substantially" or the like may still be implied.

Fig. 1-14 are cross-sectional views illustrating various stages in the formation of a semiconductor structure 1, in accordance with some embodiments of the present invention.

Referring to fig. 1, a first epitaxial layer 200 is formed on a substrate 100. In some embodiments, the substrate 100 may be or include a bulk semiconductor (bulk semiconductor) substrate, a semiconductor-on-insulator (SOI) substrate, or the like. Generally, a semiconductor-on-insulator substrate includes a semiconductor film layer formed on an insulator. For example, the insulating layer may be a silicon oxide (silicon oxide) layer, a silicon nitride (silicon nitride) layer, a polysilicon (poly-silicon) layer, or a combination thereof. And providing the insulating layer on a substrate, typically silicon (silicon) or aluminum nitride (AlN). The substrate 100 may be a doped (e.g., using p-type or n-type dopants) substrate or an undoped substrate. The substrate 100 may also be another type of substrate, such as a multi-layered (multi-layered) substrate or a graded (graded) substrate.

In some embodiments, the substrate 100 may be an elemental semiconductor, and the foregoing elemental semiconductor may include: silicon (silicon), germanium (germanium); the substrate 100 may also be a compound semiconductor, and the compound semiconductor may include: for example, but not limited to, silicon carbide (silicon carbide), gallium arsenide (gallium arsenide), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide), indium antimonide (indium antimonide); the substrate 100 may also be an alloy semiconductor, and the alloy semiconductor may include: for example, one of SiGe (silicon germanium), gaAsP (gallium arsenide phosphide), alInAs (aluminum indium arsenide), alGaAs (aluminum gallium arsenide), gaInAs (indium gallium arsenide), gaInP (gallium indium phosphide), gaInAsP (gallium indium arsenide phosphide), or any combination thereof is not limited thereto. In some embodiments, the substrate 100 is a silicon substrate.

As shown in fig. 1, in some embodiments, the first epitaxial layer 200 may include silicon, germanium, silicon germanium, a group III-V compound (a compound of groups III and V of the periodic table), or a combination thereof. The first epitaxial layer 200 may be formed by a deposition process or an epitaxial process such as metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD), atomic layer deposition (Atomic Layer Deposition, ALD), molecular beam epitaxy (Molecular Beam Epitaxy, MBE), liquid phase epitaxy (Liquid Phase Epitaxy, LPE), combinations thereof, or the like. In some embodiments, the first epitaxial layer 200 may have a first thickness T1. In some embodiments, the first epitaxial layer 200 may be formed directly on the substrate 100.

Referring to fig. 2, a first recess 201 is formed in a first epitaxial layer 200. In some embodiments, the first recess 201 does not extend through the first epitaxial layer 200. In some embodiments, a patterned hard mask layer having openings is formed on the first epitaxial layer 200, and a portion of the upper surface of the first epitaxial layer 200 is exposed through the openings of the patterned hard mask layer. Next, the first epitaxial layer 200 is etched using the patterned hard mask layer as an etch mask to remove a portion of the first epitaxial layer 200, thereby forming a first recess 201. In some embodiments, the etching process may include a dry etch, a wet etch, or other etching process. Dry etching may include, but is not limited to, plasma etching, plasma-free gas etching, sputter etching (sputter etching), ion milling (ion milling), reactive ion etching (reactive ion etching, RIE). Wet etching may include, but is not limited to, using an acidic solution, an alkaline solution, or a solvent to remove at least a portion of the structure to be removed. Thereafter, the patterned hard mask layer is removed. It is appreciated that an appropriate patterning hard mask layer, etching process and removal process can be selected according to process conditions, and the size of the first recess 201 can be adjusted according to subsequent electrical requirements. In some embodiments, the first recess 201 has a first width W1 and a first depth D1.

Referring to fig. 3, a first dielectric layer 210 is similarly (formed) in the first recess 201. In some embodiments, the first dielectric layer 210 covers side and lower surfaces of the first recess 201 and an upper surface of the first epitaxial layer 200. In some embodiments, the first dielectric layer 210 may be formed by a deposition process or a thermal oxidation process. The deposition process may be low pressure chemical vapor deposition (low pressure chemical vapor deposition, LPCVD), low temperature chemical vapor deposition (low temperature chemical vapor deposition, LTCVD), rapid thermal chemical vapor deposition (rapid thermal chemical vapor deposition, RTCVD), plasma enhanced chemical vapor deposition (Plasma Enhancement Chemical Vapor Deposition, PECVD), atomic layer deposition (atomic layer deposition, ALD), or other suitable deposition process. In some embodiments, the first dielectric layer 210 may be formed by a thermal oxidation process.

In some embodiments, the first dielectric layer 210 may be silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, any other suitable dielectric material, or a combination thereof. The high-k dielectric material may be a metal oxide, a metal nitride, a metal silicide, a transition metal oxide, a transition metal nitride, a transition metal silicide, a metal oxynitride, a metal aluminate, a zirconium silicate, or a zirconium aluminate. In some embodiments, the first dielectric layer 210 may include an oxide. In some embodiments, the first dielectric layer 210 may include silicon oxide. In some embodiments, the thickness of the first dielectric layer 210 may be adjusted according to electrical requirements. In some embodiments, the first dielectric layer 210 has a shape corresponding to the first recess 201. For example, the first dielectric layer 210 may form the first trench 202, and the shape of the first recess 201 and the shape of the first trench 202 correspond to each other. The first trench 202 may have a second width W2 and a second depth D2. That is, the aspect ratio of the first trench 202 is the ratio of the second depth D2 to the second width W2.

Referring to fig. 4, a first conductive material 300 is formed in the first trench 202 formed in the first dielectric layer 210 to form a subsequent first conductive layer. The first conductive material 300 may be formed directly on the first dielectric layer 210. The first conductive material 300 may be formed by chemical vapor deposition, sputtering, resistive heating evaporation, electron beam evaporation, or any other suitable deposition process. In some embodiments, the first conductive material 300 may include polysilicon, amorphous silicon, metal nitride, conductive metal oxide, other suitable materials, or combinations thereof. In some embodiments, the first conductive material 300 may be polysilicon. In some embodiments, the first conductive material 300 may be doped polysilicon to reduce the resistance of the subsequently formed first conductive layer by increasing the doping concentration of the first conductive material 300. In addition, when the first conductive material 300 is doped polysilicon, it may be more advantageous to form in the first trench 202.

Referring to fig. 5, the first conductive material 300 and the first dielectric layer 210 are planarized to form a first conductive layer 310 on the first dielectric layer 210. In some embodiments, the planarization process may remove a portion of the first conductive material 300 and a portion of the first dielectric layer 210 to expose an upper surface of the first epitaxial layer 200. In some embodiments, the first conductive layer 310, the first dielectric layer 210, and the first epitaxial layer 200 are substantially coplanar. In some embodiments, the planarization process may be a chemical mechanical polishing (chemical mechanical polishing, CMP) process. In some embodiments, since the first conductive layer 310 completely fills the first trench 202, the first conductive layer 310 has a second width W2 corresponding to the first trench 202.

Referring to fig. 6, a second epitaxial layer 400 is formed on the first epitaxial layer 200. In some embodiments, the materials and processes used to form the second epitaxial layer 400 may be the same or different from the materials and processes used to form the first epitaxial layer 200. In some embodiments, after forming the first recess 201, the first dielectric layer 210, and the first conductive layer 310, the second epitaxial layer 400 is formed. In some embodiments, the first epitaxial layer 200 and the second epitaxial layer 400 are formed separately. Therefore, since the first epitaxial layer 200 and the second epitaxial layer 400 are formed independently, the aspect ratio of the recess and/or the trench formed in the first epitaxial layer 200 and the second epitaxial layer 400 can be significantly reduced, and the reliability of the component formed in the recess and/or the trench can be significantly improved. For example, undesirable structures such as voids, cavities, seam defects, and/or depressions in the material filling the recesses and/or trenches may be reduced and/or avoided.

As shown in fig. 6, in some embodiments, the second epitaxial layer 400 may have a second thickness T2. In some embodiments, the first thickness T1 of the first epitaxial layer 200 may be greater than the second thickness T2 of the second epitaxial layer 400. The dimensions of the features disposed in the first epitaxial layer 200 and the features disposed in the second epitaxial layer 400 may be adjusted by adjusting the thickness ratio of the first epitaxial layer 200 and the second epitaxial layer 400. For example, the length of the shielding electrode in the first epitaxial layer 200 and the length of the gate electrode subsequently formed in the second epitaxial layer 400 may be adjusted.

In detail, in some embodiments, the overall thickness of the first epitaxial layer 200 and the second epitaxial layer 400, that is, the sum of the first thickness T1 and the second thickness T2, affects the withstand voltage capability, such as the breakdown voltage, of the subsequently formed SGT-MOSFET. The higher the sum of the first thickness T1 and the second thickness T2, the higher the withstand voltage capability of the subsequently formed SGT-MOSFET. In addition, the lengths of the gate electrodes may be similar for SGT-MOSFETs with different withstand voltage capabilities. Accordingly, the second thickness T2 of the second epitaxial layer 400 of the SGT-MOSFET having high withstand voltage capability and the SGT-MOSFET having low withstand voltage capability may be similar. However, the first thickness T1 of the first epitaxial layer 200 of the SGT-MOSFET with high voltage endurance is larger than the first thickness T1 of the first epitaxial layer 200 of the SGT-MOSFET with low voltage endurance, so as to achieve high voltage endurance by raising the first thickness T1 of the first epitaxial layer 200. Therefore, the embodiment of the present invention can enhance the effect of enhancing the reliability of devices formed in the epitaxial layers while enhancing the voltage endurance capability by independently forming the first epitaxial layer 200 and the second epitaxial layer 400, respectively.

In some embodiments, the second epitaxial layer 400 is the same material as the first epitaxial layer 200. In some embodiments, both the second epitaxial layer 400 and the first epitaxial layer 200 are monocrystalline silicon. In some embodiments, the second epitaxial layer 400 may be undoped or doped monocrystalline silicon.

In some embodiments, the doping concentration of the first epitaxial layer 200 may be greater than or equal to the doping concentration of the second epitaxial layer 400. Therefore, in the case where the doping concentration of the first epitaxial layer 200 may be greater than or equal to the doping concentration of the second epitaxial layer 400, the resistance value of the first epitaxial layer 200 may be reduced, thereby reducing the on-resistance. In addition, since the doping concentration of the second epitaxial layer 400 may be equal to or lower than that of the first epitaxial layer 200, the subsequent formation of other components in the second epitaxial layer 400 may be facilitated. For example, a lower concentration of dopant may be doped in the second epitaxial layer 400, i.e., other features such as a subsequently formed semiconductor layer, a first doped region, and a second doped region may be formed. Therefore, in the embodiment of the present invention, the epitaxial layer having two doping concentrations can be more advantageously formed.

In some embodiments, the second epitaxial layer 400 may be blanket formed on the first epitaxial layer 200 by a deposition process or an epitaxial process. Specifically, the second epitaxial layer 400 may be blanket formed on the first epitaxial layer 200, the first dielectric layer 210, and the first conductive layer 310. It should be noted that, as shown in fig. 6, there may be an interface between the first epitaxial layer 200 and the second epitaxial layer 400. Although the second epitaxial layer 400 is different from the first dielectric layer 210, some mismatch (mismatch) may occur. However, since the area of the first dielectric layer 210 occupies a small proportion of the area of the interface, the reliability of the second epitaxial layer 400 is not affected. In addition, although the second epitaxial layer 400 is different from the first conductive layer 310, some mismatching concerns may arise. However, since the area of the first conductive layer 310 occupies a small proportion of the area of the interface, the reliability of the second epitaxial layer 400 is not affected. Meanwhile, in a subsequent process of forming the second recess in the second epitaxial layer 400, a portion of the second epitaxial layer 400 on the first conductive layer 310 is removed. Thus, the slight mismatch between the second epitaxial layer 400 and the first conductive layer 310 may be further reduced. In other words, the reliability of the second epitaxial layer 400 is not affected by the first conductive layer 310 and the first dielectric layer 210. In addition, when the first epitaxial layer 200 and the second epitaxial layer 400 are formed of the same material, there may be no interface between the first epitaxial layer 200 and the second epitaxial layer 400.

In other embodiments, the second epitaxial layer 400 may be formed on a substrate different from the substrate 100. Next, the second epitaxial layer 400 is bonded to the first epitaxial layer 200 in pairs. Specifically, the upper surface of the second epitaxial layer 400 away from the substrate and the upper surface of the first epitaxial layer 200 away from the substrate 100 are brought into contact with each other and bonded. Then, the substrate is removed. Therefore, the reliability of the second epitaxial layer 400 can be ensured by additionally forming the second epitaxial layer 400 on the substrate and then bonding with the first epitaxial layer 200.

Referring to fig. 7, a second recess 401 is formed in the second epitaxial layer 400. In some embodiments, the second recess 401 may extend through the second epitaxial layer 400 to expose a portion of the upper surface of the first conductive layer 310. In some embodiments, the second epitaxial layer 400 covers a portion of the upper surface of the first conductive layer 310, the upper surface of the first dielectric layer 210, and the upper surface of the first epitaxial layer 200. In some embodiments, the process for forming the second recess 401 may be the same as or different from the process for forming the first recess 201. In some embodiments, after forming the second epitaxial layer 400, a second recess 401 is formed. In some embodiments, the second recess 401 and the first recess 201 are formed in different processes.

In some embodiments, the second recess 401 has a third width W3 and a third depth D3. In some embodiments, a first width W1 of the first recess 201 as shown in fig. 2 is greater than a third width W3 of the second recess 401 as shown in fig. 7. In some embodiments, the third depth D3 of the second recess 401 is substantially equal to the second thickness T2 of the second epitaxial layer 400 as shown in fig. 6.

Referring to fig. 8, a second dielectric layer 410 is formed in the second recess 401. Specifically, the second dielectric layer 410 is formed on the lower surface and side surfaces of the second recess 401 and the upper surface of the second epitaxial layer 400. The rounding of the corners can be achieved by forming the second dielectric layer 410. In some embodiments, the second dielectric layer 410 may be formed by a deposition process or a thermal oxidation process. In embodiments where the second dielectric layer 410 is formed by a thermal oxidation process, the second dielectric layer 410 may further include a portion that extends into the second epitaxial layer 400. The aforementioned portion of the second dielectric layer 410 extending into the second epitaxial layer 400 may cover a portion of the first conductive layer 310 and a portion of the first dielectric layer 210. The aforementioned portion of the second dielectric layer 410 extending into the second epitaxial layer 400 may be formed corresponding to the first conductive layer 310.

In some embodiments, the width of the second dielectric layer 410 is between the width of the first conductive layer 310 and the width of the first dielectric layer 210 when viewed in cross-section. That is, the side surface of the second dielectric layer 410 is between the side surfaces of the first conductive layer 310 and the first dielectric layer 210. In some embodiments, the projection of the first conductive layer 310 onto the substrate 100 is located in the projection of the second dielectric layer 410 onto the substrate 100, and the projection of the second dielectric layer 410 onto the substrate 100 is located in the projection of the first dielectric layer 210 onto the substrate 100. Thus, the side surfaces of the first dielectric layer 210 and the second dielectric layer 410 may have a distance. In some embodiments, the thickness of the second dielectric layer 410 may be adjusted according to electrical requirements. For example, the thickness of the second dielectric layer 410 may be less than the thickness of the first dielectric layer 210.

It should be noted that, in some embodiments, the first dielectric layer 210 and the second dielectric layer 410 may be integrally regarded as a shield dielectric layer (shielded dielectric layer). The width of the second dielectric layer 410 is smaller than the width of the first dielectric layer 210, and the thickness of the second dielectric layer 410 is smaller than the thickness of the first dielectric layer 210. The first dielectric layer 210 and the second dielectric layer 410 may have a step-shaped cross section when viewed in cross section. In the case of a shield dielectric layer having a stepped profile, the electric field distribution can be made more uniform to reduce the on-resistance and/or to increase the breakdown voltage of the semiconductor structure. When the shield dielectric layer near the lower surface of the first recess 201 has a thicker thickness, the electric field concentrated at the lower surface of the first recess 201 can be reduced, so that the electric charge is more uniform. In some embodiments, the semiconductor structure of the present invention has a lower on-resistance, so that a figure of merit (FOM) can be improved to provide more excellent electrical characteristics.

Referring to fig. 9, a portion of the second dielectric layer 410 is removed. Specifically, a portion of the second dielectric layer 410 on the side surface of the second recess 401 and the upper surface of the second epitaxial layer 400 is removed to expose the side surface of the second recess 401 and the upper surface of the second epitaxial layer 400 before the gate dielectric layer is subsequently formed. In some embodiments, the second dielectric layer 410 remains on the first conductive layer 310 and the second dielectric layer 410 remains extending into the second epitaxial layer 400.

Referring to fig. 10, a gate dielectric layer 420 is similarly formed on the second epitaxial layer 400. Specifically, in some embodiments, a gate dielectric layer 420 may be formed on the second epitaxial layer 400 and the second dielectric layer 410. In some embodiments, gate dielectric layer 420 may be, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, combinations thereof, or other suitable dielectric materials. In some embodiments, the gate dielectric layer 420 may include an oxide. In some embodiments, the gate dielectric layer 420 and the first dielectric layer 210 and/or the second dielectric layer 410 may be formed by the same or different processes.

In some embodiments, the thickness of the gate dielectric layer 420 may be adjusted according to electrical requirements. For example, the thickness of the gate dielectric layer 420 may be less than the thicknesses of the first dielectric layer 210 and the second dielectric layer 410. In some embodiments, the gate dielectric layer 420 may form the second trench 402. In some embodiments, the shape of the second recess 401 and the shape of the second trench 402 correspond to each other. The second trench 402 may have a fourth width W4 and a fourth depth D4. That is, the aspect ratio of the second trench 402 is the ratio of the fourth depth D4 to the fourth width W4. In some embodiments, the aspect ratio of the first trench 202 (the ratio of the second depth D2 to the second width W2) is smaller than the aspect ratio of the second trench 402 (the ratio of the fourth depth D4 to the fourth width W4).

In detail, the embodiments are described in the case where the shielding electrode and the gate electrode to be formed later have substantially similar or identical lengths. First, since the first width W1 of the first recess 201 is greater than the third width W3 of the second recess 401 and the thickness of the first dielectric layer 210 is greater than the thickness of the gate dielectric layer 420, the second width W2 of the first trench 202 is greater than the second width W2 of the second trench 402. Furthermore, since the shield electrode and the gate electrode have substantially similar or identical lengths, the second depth D2 and the fourth depth D4 are substantially identical. Accordingly, the aspect ratio of the first trench 202 is smaller than the aspect ratio of the second trench 402. Accordingly, embodiments of the present invention may improve the reliability of the materials formed in the first trench 202 and the second trench 402 by providing the first epitaxial layer 200 and the second epitaxial layer 400 separately, respectively, as compared to sequentially forming the shielding electrode and the gate electrode in the same recess and/or trench. In the case of adjusting the first epitaxial layer 200, the first recess 201, the second epitaxial layer 400, and the second recess 401, the reliability of the material formed in the first trench 202 and the second trench 402 can be further improved.

Referring to fig. 11, a second conductive material 500 is formed in the second trench 402 formed in the gate dielectric layer 420 to form a subsequent gate electrode. The second conductive material 500 may be formed directly on the gate dielectric layer 420. In some embodiments, the materials and processes used to form the second conductive material 500 may be the same as or different from the materials and processes used to form the first conductive material 300. In some embodiments, the second conductive material 500 may be polysilicon.

Referring to fig. 12, the second conductive material 500 and the gate dielectric layer 420 are planarized to form a gate electrode 510 on the gate dielectric layer 420. In some embodiments, the planarization process may remove a portion of the second conductive material 500 to expose an upper surface of the gate dielectric layer 420. In some embodiments, the gate electrode 510 and the gate dielectric layer 420 are substantially coplanar. In some embodiments, the planarization process may be a chemical mechanical polishing process. In some embodiments, since the gate electrode 510 completely fills the second trench 402, the gate electrode 510 has a fourth width W4 corresponding to the second trench 402. In some embodiments, the fourth width W4 of the gate electrode 510 may be smaller than the second width W2 of the first conductive layer 310. In other words, the upper surface of the first conductive layer 310 is larger than the upper surface of the gate electrode 510. In some embodiments, the first conductive layer 310 and the gate electrode 510 are formed in the first recess 201 and the second recess 401, respectively, which are formed by different processes.

It should be noted that, in some embodiments, in the SGT-MOSFET obtained after the subsequent processing, the first conductive layer 310 may be disposed under the gate electrode 510, so the first conductive layer 310 may be regarded as a shielding electrode of the gate electrode 510. In some embodiments, the shielding electrode may be connected to the source electrode of the resulting SGT-MOSFET after subsequent processing, or the shielding electrode may be considered part of the source electrode of the resulting SGT-MOSFET after subsequent processing. In an embodiment in which the second width W2 of the first conductive layer 310 is greater than the fourth width W4 of the gate electrode 510, the area of the active area between the adjacent gate electrodes 510 may be increased. Under the condition that the area of the active region is larger, more current can flow through the active region, so that the on-state current is improved. In addition, the larger active area provides a larger contact area (contact landing area), which helps to reduce alignment issues during subsequent contact formation, thereby improving overall process window. For example, the process margin of a back-end process may be improved.

Referring to fig. 13, a semiconductor layer 600 and a first doped region 610 are formed in a second epitaxial layer 400. The semiconductor layer 600 and the first doped region 610 are not disposed in the second recess 401. The semiconductor layer 600 and/or the first doped region 610 may be formed by an ion implantation (ion implantation) or diffusion (diffusion) process, but is not limited thereto. In addition, the implanted dopants may also be activated by a rapid thermal annealing (rapid thermal annealing, RTA) process.

Referring to fig. 14, an interlayer dielectric (interlayer dielectric) layer 700 can be formed on the gate electrode 510. Specifically, the interlayer dielectric layer 700 may be formed on the gate dielectric layer 420 and the gate electrode 510. In some embodiments, interlayer dielectric layer 700 may be formed using the same or different materials and processes as first dielectric layer 210, second dielectric layer 410, and/or gate dielectric layer 420.

As shown in fig. 14, a contact via hole may be further formed. In some embodiments, the contact via penetrates the interlayer dielectric 700, the gate dielectric 420, and the first doped region 610 to the semiconductor layer 600, and does not penetrate the semiconductor layer 600. Then, the second doped region 620 is formed under the contact via hole, so that the number of times of using the patterned hard mask can be reduced, thereby simplifying the process and reducing the process cost. Wherein the second doped region 620 has a different conductivity type than the first doped region 610.

Thereafter, a via material is filled in the contact via to form the contact 800. In some embodiments, the via material may include a metallic material, a conductive material, other suitable materials, or a combination thereof. Then, a metal layer 900 is formed on the interlayer dielectric layer 700, and the metal layer 900 and the contact 800 are contacted with each other, so as to obtain the semiconductor structure 1. In some embodiments, the metal layer 900 may include a metal material, a conductive material, other suitable materials, or a combination thereof. Semiconductor structure 1 may be or may be further processed as an SGT-MOSFET. In some embodiments, other further processes may be performed. In some embodiments, the methods of forming the present invention may be applied to SGT-MOSFETs where the gate electrode is disposed adjacent to the shielding electrode, and SGT-MOSFETs where the shielding electrode is disposed below the gate electrode. In particular, the method of forming the present invention is applicable to SGT-MOSFETs where the shielding electrode is disposed below the gate electrode.

In some embodiments, the substrate 100, the first epitaxial layer 200, the second epitaxial layer 400, and the first doped region 610 may have a first conductivity type. The doping concentration of the first doping region 610 may be higher than the doping concentrations of the substrate 100, the first epitaxial layer 200, and the second epitaxial layer 400. The semiconductor layer 600 and the second doped region 620 have a second conductivity type different from the first conductivity type. The doping concentration of the second doping region 620 may be higher than that of the semiconductor layer 600. For example, when the substrate 100, the first epitaxial layer 200, and the second epitaxial layer 400 are N-type and the semiconductor layer 600 is P-type, the first doped region 610 may be heavily doped n+ type and the second doped region 620 may be heavily doped p+ type. In other embodiments, when the substrate 100, the first epitaxial layer 200, and the second epitaxial layer 400 are P-type, the semiconductor layer 600 is N-type.

In some embodiments, the first conductivity type and the second conductivity type can be adjusted according to the requirement, and the doping concentration, the doping depth and the size of the doped region can be adjusted according to the requirement. In some embodiments, the semiconductor layer 600 may also be formed in the second epitaxial layer 400 before forming the gate electrode.

In summary, according to some embodiments of the present invention, the two-stage formation process of forming the first epitaxial layer and then forming the second epitaxial layer reduces the aspect ratio of the trenches disposed in the first epitaxial layer and the second epitaxial layer, so as to improve the reliability of the devices disposed in the first epitaxial layer and the second epitaxial layer, thereby avoiding or reducing the poor structures such as voids, cavities, seam defects and/or recesses in the devices, and improving the electrical performance and reliability of the semiconductor structure as a whole. In addition, the invention further improves the reliability of the components arranged in the first epitaxial layer by making the depth-to-width ratio of the first concave part smaller than that of the second concave part. Furthermore, the invention reduces the on-resistance and/or improves the breakdown voltage of the semiconductor structure by the shielding dielectric layer with the step-shaped section. In addition, the invention improves the on-current and the process margin by making the width of the first conductive layer larger than the width of the gate electrode and improving the area of the active region.

The scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but rather should be understood to mean that a person skilled in the art would recognize, from the disclosure of some embodiments of the present invention, that the process, machine, manufacture, composition of matter, means, methods and steps are capable of performing substantially the same function or achieving substantially the same result in some embodiments of the present invention. Accordingly, the scope of the present application includes such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim forms a separate embodiment, and the scope of the present invention also includes combinations of the claims and embodiments.

The foregoing outlines several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present invention. Those skilled in the art will be able to devise and modify other arrangements and processes based on the embodiments of the present invention to achieve the same objects and/or advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present embodiments, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present embodiments.

Claims

1. A method of forming a semiconductor structure, comprising:

forming a first epitaxial layer on a substrate;

forming a first recess in the first epitaxial layer;

forming a first dielectric layer in the first recess;

forming a first conductive layer on the first dielectric layer;

forming a second epitaxial layer on the first epitaxial layer;

similarly forming a gate dielectric layer on the second epitaxial layer; and

a gate electrode is formed on the gate dielectric layer.

2. The method of forming as claimed in claim 1, further comprising:

a second recess is formed in the second epitaxial layer such that the second recess exposes the upper surface of the first conductive layer.

3. The method of forming as claimed in claim 2, further comprising:

a second dielectric layer is formed on the lower surface and side surfaces of the second recess and on the upper surface of the second epitaxial layer, and a portion of the second dielectric layer extends into the second epitaxial layer.

4. The method of claim 3, further comprising, prior to similarly forming the gate dielectric layer on the second epitaxial layer:

a portion of the second dielectric layer is removed to expose a side surface of the second recess and an upper surface of the second epitaxial layer.

5. The method of forming as claimed in claim 1, further comprising:

forming a semiconductor layer in the second epitaxial layer;

forming a first doped region in the semiconductor layer;

forming an interlayer dielectric layer on the gate electrode;

forming a second doped region in the semiconductor layer;

forming a contact passing through the interlayer dielectric layer and the first doped region to contact with the second doped region; and

a metal layer is formed on the interlayer dielectric layer and is electrically connected with the second doped region through the contact.

6. A semiconductor structure, comprising:

a substrate having a first conductivity type;

a first epitaxial layer having the first conductivity type and disposed on the substrate and including a first recess;

a first dielectric layer disposed in the first recess;

a first conductive layer disposed on the first dielectric layer;

a second epitaxial layer having the first conductivity type and disposed on the first epitaxial layer and including a second recess;

a gate dielectric layer disposed in the second recess;

a gate electrode disposed on the gate dielectric layer; and

and a semiconductor layer having a second conductivity type different from the first conductivity type, disposed in the second epitaxial layer, and not disposed in the second recess.

7. The semiconductor structure of claim 6, wherein a thickness of the first epitaxial layer is greater than a thickness of the second epitaxial layer.

8. The semiconductor structure of claim 6, wherein a doping concentration of the first epitaxial layer is greater than or equal to a doping concentration of the second epitaxial layer.

9. The semiconductor structure of claim 6, wherein a width of the first conductive layer is greater than a width of the gate electrode.

10. The semiconductor structure of claim 6, further comprising:

and a second dielectric layer disposed between the first conductive layer and the gate dielectric layer, and a portion of the second dielectric layer extending into the second epitaxial layer.