CN116230525B - Wafer Cleaning Method - Google Patents
Wafer Cleaning Method Download PDFInfo
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- CN116230525B CN116230525B CN202310508818.3A CN202310508818A CN116230525B CN 116230525 B CN116230525 B CN 116230525B CN 202310508818 A CN202310508818 A CN 202310508818A CN 116230525 B CN116230525 B CN 116230525B
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- 238000000034 method Methods 0.000 title claims abstract description 62
- 238000004140 cleaning Methods 0.000 title claims abstract description 45
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 100
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 100
- 238000005530 etching Methods 0.000 claims abstract description 84
- 238000000137 annealing Methods 0.000 claims abstract description 50
- 239000007788 liquid Substances 0.000 claims abstract description 10
- 238000013507 mapping Methods 0.000 claims description 20
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 16
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 8
- 238000004364 calculation method Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 abstract description 11
- 235000012431 wafers Nutrition 0.000 description 89
- 238000005516 engineering process Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000009191 jumping Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000012634 fragment Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Weting (AREA)
Abstract
The application discloses a wafer cleaning method, which comprises the steps of providing a wafer, wherein a first silicon nitride layer and a second silicon nitride layer which are subjected to annealing treatment are respectively formed on the upper surface and the lower surface of the wafer; obtaining an annealing temperature of annealing treatment; calculating based on the current etching solution and annealing temperature to obtain the etching time required by the second silicon nitride layer to be completely etched; and cleaning the wafer by adopting the current etching liquid according to the etching time so as to remove the first silicon nitride layer and the second silicon nitride layer. The scheme can improve the yield of the semiconductor device.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a wafer cleaning method.
Background
Stress memorization technology (Stress Memorization Technique, SMT) is a stress engineering that is raised below the 90nm logic technology node and is aimed at improving the speed of semiconductor devices. The SMT is characterized in that the technology can obviously accelerate the electron mobility of the semiconductor device by virtue of the action of tensile stress, thereby improving the driving current of the semiconductor device.
In practical applications, a silicon nitride layer with tensile stress is generally deposited on the upper surface of a wafer, then the stress in the silicon nitride layer is kept in the wafer through an annealing process, and finally the silicon nitride layer is removed through a cleaning process.
Since the silicon nitride layer is generally prepared by a furnace process, both the upper and lower surfaces of the wafer will form the silicon nitride layer. When the silicon nitride layer on the upper surface of the wafer is removed through the cleaning process, the upper surface and the lower surface of the wafer are soaked in the cleaning liquid at the same time for cleaning. However, the silicon nitride layer on the lower surface of the wafer cannot be completely removed due to the limited cleaning process, so that the silicon nitride layer remains more obviously, especially at the edge of the wafer, and the remaining silicon nitride layer remains until the subsequent process, which affects the yield of semiconductor devices.
Disclosure of Invention
The application provides a wafer cleaning method which can improve the yield of semiconductor devices.
The application provides a wafer cleaning method, which comprises the following steps:
providing a wafer, wherein a first silicon nitride layer and a second silicon nitride layer which are subjected to annealing treatment are respectively formed on the upper surface and the lower surface of the wafer;
obtaining the annealing temperature of the annealing treatment;
calculating based on the current etching solution and the annealing temperature to obtain the etching duration required by the second silicon nitride layer to be completely etched;
and cleaning the wafer by adopting the current etching liquid according to the etching time length so as to remove the first silicon nitride layer and the second silicon nitride layer.
In the wafer cleaning method provided by the application, the calculating based on the current etching solution and the annealing temperature to obtain the etching duration required by the second silicon nitride layer to be completely etched includes:
determining the etching rate of the second silicon nitride layer in the current etching solution according to the annealing temperature;
and calculating based on the etching rate and the thickness of the second silicon nitride layer to obtain the etching duration required by the second silicon nitride layer to be completely etched.
In the wafer cleaning method provided by the application, the calculation formula for obtaining the etching time required by the second silicon nitride layer to be completely etched based on the etching rate and the thickness of the second silicon nitride layer is as follows:
T = (Thk(Pre A)/ER(Ann A))*K
wherein T is the etching duration, thk (Pre a) is the thickness of the second silicon nitride layer, ER (Ann a) is the etching rate, and K is the overetching coefficient.
In the wafer cleaning method provided by the application, before determining the etching rate of the second silicon nitride layer in the current etching solution according to the annealing temperature, the method further comprises:
collecting etching rates of silicon nitride subjected to annealing treatment at different annealing temperatures in etching solutions of different types;
respectively establishing sub-relation mapping tables of annealing temperatures and etching rates of annealed silicon nitride in different types of etching solutions;
and integrating all the sub-relationship mapping tables to obtain a preset relationship mapping table.
In the wafer cleaning method provided by the application, the determining the etching rate of the second silicon nitride layer in the current etching solution according to the annealing temperature comprises the following steps:
determining a sub-relationship mapping table corresponding to the current etching solution in the preset relationship mapping table;
and determining the etching rate of the second silicon nitride layer in the current etching solution according to the annealing temperature and the sub-relation mapping table.
In the wafer cleaning method provided by the application, the thickness of the first silicon nitride layer is smaller than that of the second silicon nitride layer.
In the wafer cleaning method provided by the application, the current etching solution is hot phosphoric acid.
In the wafer cleaning method provided by the application, the temperature of the hot phosphoric acid is 155-165 ℃.
In the wafer cleaning method provided by the application, the mass fraction of the hot phosphoric acid is 75-95 wt%.
In the wafer cleaning method provided by the application, the first silicon nitride layer and the second silicon nitride layer on the upper surface and the lower surface of the wafer are formed simultaneously through a furnace tube process.
In summary, the wafer cleaning method provided by the application comprises the following steps: providing a wafer, wherein a first silicon nitride layer and a second silicon nitride layer which are subjected to annealing treatment are respectively formed on the upper surface and the lower surface of the wafer; obtaining the annealing temperature of the annealing treatment; calculating based on the current etching solution and the annealing temperature to obtain the etching duration required by the second silicon nitride layer to be completely etched; and cleaning the wafer by adopting the current etching liquid according to the etching time length so as to remove the first silicon nitride layer and the second silicon nitride layer. The first silicon nitride layer on the upper surface of the wafer and the second silicon nitride layer on the lower surface of the wafer can be completely removed through the scheme, so that the lower surface of the wafer is smooth, the uniformity of a film layer formed on the wafer is guaranteed, the risk of jumping or breaking is reduced, and the yield of semiconductor devices is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a wafer defect according to an embodiment of the present application.
Fig. 2 is a flow chart of a wafer cleaning method according to an embodiment of the application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element, and furthermore, elements having the same name in different embodiments of the application may have the same meaning or may have different meanings, the particular meaning of which is to be determined by its interpretation in this particular embodiment or by further combining the context of this particular embodiment.
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In the following description, suffixes such as "module", "part" or "unit" for representing elements are used only for facilitating the description of the present application, and have no specific meaning per se. Thus, "module," "component," or "unit" may be used in combination.
In the description of the present application, it should be noted that the positional or positional relationship indicated by the terms such as "upper", "lower", "left", "right", "inner", "outer", etc. are based on the positional or positional relationship shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the front-end process of the semiconductor device, si is formed on both the upper and lower surfaces of the wafer 3 N 4 . Removing Si on the upper surface of the wafer by a cleaning process 3 N 4 And the upper surface and the lower surface of the wafer are soaked in the cleaning liquid at the same time for cleaning. However, due to the limited cleaning process, the Si on the lower surface of the wafer 3 N 4 Cannot be completely removed, and Si is present 3 N 4 The residues, especially at the edge of the Wafer, are more obvious, which causes defects such as Wafer skip (Wafer skip) and Wafer fragment (Wafer fragment) to affect the yield of the semiconductor device.
Wafer jumping and chipping are commonly found in high temperature processes (Rapid Thermal Processing, RTP), in part because different types of films are formed on the surface of the wafer after the wafer is subjected to different processes, and the rate of temperature rise of the wafer during the high temperature processes is also changed due to the different heat emissivity (emittance) of the different types of films.
For example, si 3 N 4 The heat emissivity of the wafer is as high as 0.97, and the heat emissivity of the P-type wafer is only 0.66If Si is 3 N 4 The lower surface of the wafer is in a form shown in fig. 1, so that the temperature rising rate of the part (1) of the wafer is far higher than that of the part (2) in the high-temperature process, and the temperature distribution difference is obvious, so that the uneven film thickness of the upper surface of the wafer can be caused, thick film distribution (THK profile) shown in fig. 1 can be generated, and the risk of jumping and even breaking exists.
The cleaning process cannot realize the Si on the lower surface of the wafer 3 N 4 The reason for the complete removal is mainly two, one is Si for the lower surface 3 N 4 For example, since the shallow trench isolation planarization (STI-CMP) process is not performed, si on the upper surface of the wafer 3 N 4 Is significantly smaller than the thickness of Si on the lower surface of the wafer 3 N 4 This results in Si as the upper surface 3 N 4 After having been cleaned out, the Si on the wafer backside 3 N 4 Residual still exists; secondly, because the trench isolation structure is densified by high temperature annealing after the shallow trench isolation structure is filled, the high temperature annealing process can cause Si 3 N 4 Densification of the film layer of (C) also occurs, resulting in cleaning solution to Si 3 N 4 Is reduced.
Based on this, the embodiment of the application provides a wafer cleaning method, and the technical scheme shown in the application will be described in detail through the specific embodiment. The following description of the embodiments is not intended to limit the priority of the embodiments.
Referring to fig. 2, fig. 2 is a flow chart of a wafer cleaning method according to an embodiment of the application. The specific flow of the wafer cleaning method can be as follows:
101. and providing a wafer, wherein the upper surface and the lower surface of the wafer are respectively provided with a first silicon nitride layer and a second silicon nitride layer which are subjected to annealing treatment.
It will be appreciated that in the fabrication of semiconductor devices, it is often necessary to deposit a silicon nitride layer having a tensile stress on the upper surface of the wafer, then to leave the stress in the silicon nitride layer in the wafer by an annealing process, and finally to remove the silicon nitride layer by a cleaning process. Since the silicon nitride layer is generally prepared by a furnace process, the upper surface and the lower surface of the wafer may simultaneously form the silicon nitride layer. For convenience of description, the silicon nitride layer on the upper surface of the wafer is referred to as a first silicon nitride layer, and the silicon nitride layer on the lower surface of the wafer is referred to as a second silicon nitride layer.
The wafer may be made of monocrystalline silicon, silicon carbide, gallium arsenide, indium phosphide or germanium silicon, or a silicon germanium wafer, a silicon III-V group element compound wafer, a silicon carbide wafer or a laminated structure thereof, or a silicon-on-insulator wafer, or a diamond wafer or other wafers known to those skilled in the art, for example, a wafer in which P atoms can be implanted into monocrystalline silicon to form N-type conductivity, or a wafer in which B atoms can be implanted into monocrystalline silicon to form P-type conductivity.
A drift region, a channel region, a source region, a drain region, and a deep well region plasma implantation region may be disposed within the wafer.
102. And obtaining the annealing temperature of the annealing treatment.
It will be appreciated that the annealing process may be performed at different elevated temperatures. For example, the annealing treatment temperature may be 580 ℃, 760 ℃, 800 ℃, 950 ℃, 1050 ℃, or the like. The annealing temperature of the annealing treatment can be set according to practical situations, and the embodiment of the application does not limit the annealing temperature.
103. And calculating based on the current etching solution and the annealing temperature to obtain the etching time required by the second silicon nitride layer to be completely etched.
Specifically, the etching rate of the second silicon nitride layer in the current etching solution can be determined according to the annealing temperature; and calculating based on the etching rate and the thickness of the second silicon nitride layer to obtain the etching time required by the second silicon nitride layer to be completely etched.
The calculation is performed based on the etching rate and the thickness of the second silicon nitride layer, and a calculation formula for obtaining the etching duration required by the second silicon nitride layer to be completely etched is as follows:
T = (Thk(Pre A)/ER(Ann A))*K
wherein T is the etching duration, thk (Pre a) is the thickness of the second silicon nitride layer, ER (Ann a) is the etching rate, and K is the overetching coefficient. Generally, the value of the overetch coefficient ranges from 1.4 to 1.6.
In some embodiments, a preset relationship mapping table may be established through sample collection before the wafer is cleaned, so as to determine the etching rate of the second silicon nitride layer in the current etching solution according to the annealing temperature.
Specifically, before the step of determining the etching rate of the second silicon nitride layer in the current etching solution according to the annealing temperature, the etching rates of the silicon nitride layer in different types of etching solutions after annealing treatment at different annealing temperatures can be collected; respectively establishing sub-relation mapping tables of annealing temperatures and etching rates of annealed silicon nitride in different types of etching solutions; and integrating all the sub-relationship mapping tables to obtain a preset relationship mapping table.
Then, the etching rate may be determined according to the type of the current etching liquid and a preset relationship map. Specifically, a sub-relationship mapping table corresponding to the current etching solution in the relationship mapping table can be determined; and determining the etching rate of the second silicon nitride layer in the current etching solution according to the annealing temperature and the sub-relation mapping table.
In the embodiment of the application, the current etching solution is hot phosphoric acid. Wherein the temperature of the hot phosphoric acid is 155-165 ℃, and the mass fraction is 75-95 wt%.
104. And cleaning the wafer by adopting the current etching liquid according to the etching time so as to remove the first silicon nitride layer and the second silicon nitride layer.
It will be appreciated that the thickness of the first silicon nitride layer is less than the thickness of the second silicon nitride layer. Therefore, when the second silicon nitride layer is completely removed in the same etching solution, the first silicon nitride layer is also completely removed.
Therefore, in the embodiment of the application, the wafer can be cleaned according to the etching time required by the second silicon nitride layer to be completely etched, so that the purpose of removing the first silicon nitride layer and the second silicon nitride layer is achieved, and the phenomenon of residual second silicon nitride layer is avoided.
In summary, the wafer cleaning method provided by the embodiment of the application includes providing a wafer, wherein a first silicon nitride layer and a second silicon nitride layer which are annealed are respectively formed on the upper surface and the lower surface of the wafer; obtaining an annealing temperature of annealing treatment; calculating based on the current etching solution and annealing temperature to obtain the etching time required by the second silicon nitride layer to be completely etched; and cleaning the wafer by adopting the current etching liquid according to the etching time so as to remove the first silicon nitride layer and the second silicon nitride layer. That is, the present solution can completely remove the first silicon nitride layer on the upper surface and the second silicon nitride layer on the lower surface of the wafer.
In addition, the scheme does not need to increase the processing steps and the measuring machine, only needs to test the etching rates of different types of film layers in various etching solutions on the existing wet etching machine, and then establishes and stores a relation mapping table. And finally, the time length of the cleaning process can be adjusted through calculation, and the wafer is cleaned according to the time length of the cleaning process, so that the first silicon nitride layer on the upper surface and the second silicon nitride layer on the lower surface of the wafer are completely removed, the consistency and the uniformity of the lower surface of the wafer are improved, and the risk of wafer jump and/or fragmentation in the subsequent high-temperature process is reduced.
The wafer cleaning method provided by the application is described in detail, and specific examples are applied to illustrate the principles and the implementation modes of the application, and the description of the examples is only used for helping to understand the core idea of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.
Claims (6)
1. A method of cleaning a wafer, comprising:
providing a wafer, wherein a first silicon nitride layer and a second silicon nitride layer which are subjected to annealing treatment are respectively formed on the upper surface and the lower surface of the wafer, and the thickness of the first silicon nitride layer is smaller than that of the second silicon nitride layer;
obtaining the annealing temperature of the annealing treatment;
collecting etching rates of silicon nitride subjected to annealing treatment at different annealing temperatures in etching solutions of different types;
respectively establishing sub-relation mapping tables of annealing temperatures and etching rates of annealed silicon nitride in different types of etching solutions;
integrating all the sub-relationship mapping tables to obtain a preset relationship mapping table;
determining a sub-relation mapping table corresponding to the current etching solution in the preset relation mapping table;
determining the etching rate of the second silicon nitride layer in the current etching liquid according to the annealing temperature and the sub-relation mapping table;
calculating based on the etching rate and the thickness of the second silicon nitride layer to obtain etching duration required by the second silicon nitride layer to be completely etched;
and cleaning the upper surface and the lower surface of the wafer by adopting the current etching liquid according to the etching time length so as to remove the first silicon nitride layer and the second silicon nitride layer.
2. The method of claim 1, wherein the calculation based on the etching rate and the thickness of the second silicon nitride layer yields a calculation formula of an etching time period required for the second silicon nitride layer to be completely etched, wherein the calculation formula is:
T = (Thk(Pre A)/ER(Ann A))*K
wherein T is the etching duration, thk (Pre a) is the thickness of the second silicon nitride layer, ER (Ann a) is the etching rate, and K is the overetching coefficient.
3. The method of claim 1, wherein the current etching solution is hot phosphoric acid.
4. The method of claim 3, wherein the hot phosphoric acid has a temperature of 155 ℃ to 165 ℃.
5. The wafer cleaning method according to claim 3, wherein the mass fraction of the hot phosphoric acid is 75wt% to 95wt%.
6. The wafer cleaning method of claim 1, wherein the first silicon nitride layer and the second silicon nitride layer on the upper surface and the lower surface of the wafer are simultaneously formed by a furnace process.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310508818.3A CN116230525B (en) | 2023-05-08 | 2023-05-08 | Wafer Cleaning Method |
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| CN202310508818.3A CN116230525B (en) | 2023-05-08 | 2023-05-08 | Wafer Cleaning Method |
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| CN116230525B true CN116230525B (en) | 2023-08-29 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569019A (en) * | 2010-12-17 | 2012-07-11 | 无锡华润上华半导体有限公司 | Dielectric film etching method and shallow trench isolation forming method |
| CN102768993A (en) * | 2011-05-03 | 2012-11-07 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of NMOS (N-channel metal oxide semiconductor) device by stress memorization technique |
| CN110184587A (en) * | 2019-05-23 | 2019-08-30 | 上海华力集成电路制造有限公司 | The method and chemical vapor depsotition equipment of etch rate uniformity between raising silicon wafer |
| CN115241058A (en) * | 2022-09-23 | 2022-10-25 | 广州粤芯半导体技术有限公司 | Semiconductor device etching method and semiconductor device manufacturing method |
-
2023
- 2023-05-08 CN CN202310508818.3A patent/CN116230525B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569019A (en) * | 2010-12-17 | 2012-07-11 | 无锡华润上华半导体有限公司 | Dielectric film etching method and shallow trench isolation forming method |
| CN102768993A (en) * | 2011-05-03 | 2012-11-07 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of NMOS (N-channel metal oxide semiconductor) device by stress memorization technique |
| CN110184587A (en) * | 2019-05-23 | 2019-08-30 | 上海华力集成电路制造有限公司 | The method and chemical vapor depsotition equipment of etch rate uniformity between raising silicon wafer |
| CN115241058A (en) * | 2022-09-23 | 2022-10-25 | 广州粤芯半导体技术有限公司 | Semiconductor device etching method and semiconductor device manufacturing method |
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