CN105590864A - Method for forming embedded SiGe PMOS transistor - Google Patents
Method for forming embedded SiGe PMOS transistor Download PDFInfo
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- CN105590864A CN105590864A CN201410654357.1A CN201410654357A CN105590864A CN 105590864 A CN105590864 A CN 105590864A CN 201410654357 A CN201410654357 A CN 201410654357A CN 105590864 A CN105590864 A CN 105590864A
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Abstract
The present invention provides a method for forming an embedded SiGe PMOS transistor, comprising the steps of: providing a semiconductor substrate, wherein the semiconductor substrate has a grid structure, and grid sidewalls surround the grid structure; etching the semiconductor substrate at two sides of the grid structure to form grooves; performing heat treatment for the grid sidewalls by adopting an annealing process; performing wet cleaning for the semiconductor substrate; and depositing SiGe in the grooves. The method of the present invention can effectively improve the film quality of the grid sidewalls, enables the grid sidewalls to be more compact, and can avoid or reduce the damage to the grid sidewalls due to wet cleaning.
Description
Technical field
The present invention relates to the transistorized manufacturing process of embedded germanium silicon PMOS, relating in particular to one can avoid or subtractThe transistorized formation method of embedded germanium silicon PMOS of the damage defect of few gate lateral wall.
Background technology
Along with constantly dwindling of IC-components size, for the following technical matters of 45nm, a kind of liftingThe method of PMOS transistor performance is to adopt embedded germanium silicon source to leak PMOS transistor. Leak in embedded germanium silicon sourceThe transistorized structure of PMOS as shown in Figure 1, mainly comprises: substrate 10; Be formed on the drain junctions on substrate 10Structure 11; Germanium-silicon thin membrane 12, is filled in the groove in the substrate 10 of grid structure 11 both sides; Dielectric layer 13,Overlies gate structure 11, germanium-silicon thin membrane 12 etc.
The embedded germanium silicon source transistorized formation technical process of leakage PMOS is as follows: etching PMOS source/drain regionTerritory, to form source/drain region (S/D) groove, the shape of source/drain region groove is generally " Σ " shape (Sigmashape);Then source/drain region (S/D) inside grooves forming in etching is introduced epitaxy Si Ge layer, should with the pressure that produces raceway groovePower (compressivestress), this stress distorts the lattice of semiconductor crystal, and producing compression shouldPower, thus the transistorized carrier mobility of PMOS (mobility) improved, and then improve drive current, increaseThe performance of strong device.
In embedded germanium silicon PMOS transistor, germanium-silicon thin membrane is grown on Si substrate, this epitaxial growth workSkill will be carried out wet clean process (pre-clean) to growth interface conventionally, to reduce as far as possible Si substrate surfaceDefect, avoid the pollution of impurity to substrate-epitaxial layer interface. Wet-cleaning is normally used is hydrofluoric acid dipping,Scanned and can be found by transmission electron microscope, after hydrofluoric acid dipping cleans, the transistorized gate lateral wall of PMOS is (logicalNormal material is silicon nitride) almost absolutely there will be serious damage, it is selective that this can affect germanium silicon on the one handEpitaxial growth, also can cause the electric leakage defect of device on the other hand.
With reference to figure 2, in prior art, the technique that forms germanium-silicon thin membrane roughly comprises the steps: step S11,Etching forms groove; Step S12, carries out wet-cleaning before extension; Step S13, deposit Germanium silicon in groove.Traditional technological process can not solve the damage of wet-cleaning to gate lateral wall silicon nitride, device performance is produced tightGhost image rings.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of transistorized formation method of embedded germanium silicon PMOS,Can effectively improve gate lateral wall membranous, make it finer and close, can avoid or alleviate wet-cleaning to gate electrode sideThe damage that wall causes.
For solving the problems of the technologies described above, the invention provides the transistorized formation side of a kind of embedded germanium silicon PMOSMethod, comprising:
Semiconductor substrate is provided, in this Semiconductor substrate, has grid structure, this grid structure is surrounded by grid aroundUtmost point sidewall;
Semiconductor substrate to described grid structure both sides is carried out etching, to form groove;
Adopt annealing process to heat-treat described gate lateral wall;
Described Semiconductor substrate is carried out to wet-cleaning;
Deposit Germanium silicon in described groove.
According to one embodiment of present invention, described annealing process is rapid thermal anneal process.
According to one embodiment of present invention, the technological parameter of described rapid thermal anneal process is: temperature is 850DEG C～1000 DEG C, the time is 0～15 second, gas is the mist of nitrogen or helium or nitrogen and helium.
According to one embodiment of present invention, the material of described sidewall is silicon nitride.
According to one embodiment of present invention, the cleaning fluid of described wet-cleaning employing comprises hydrofluoric acid.
Compared with prior art, the present invention has the following advantages:
In the transistorized formation method of embedded germanium silicon PMOS of the embodiment of the present invention, before wet-cleaning, makeWith annealing process, gate lateral wall is heat-treated, has effectively improved the membranous of gate lateral wall, make it finer and close,Can avoid or reduce the damage of wet-cleaning to gate lateral wall, for example damage of hydrofluoric acid to silicon nitride, thereby energyEnough gate lateral wall defects that significantly reduces, avoid the problems such as the element leakage that causes thus.
Brief description of the drawings
Fig. 1 is the transistorized perspective view of a kind of embedded germanium silicon PMOS in prior art;
Fig. 2 is the schematic flow sheet of a kind of transistorized formation method of embedded germanium silicon PMOS in prior art;
Fig. 3 is the flow process signal according to the transistorized formation method of embedded germanium silicon PMOS of the embodiment of the present inventionFigure;
Fig. 4 to Fig. 6 is according to each in the transistorized formation method of embedded germanium silicon PMOS of the embodiment of the present inventionThe cross-sectional view of step.
Detailed description of the invention
Below in conjunction with specific embodiments and the drawings, the invention will be further described, but should not limit this with thisBright protection domain.
With reference to figure 3, according to one embodiment of present invention, the transistorized formation method of embedded germanium silicon PMOSCan comprise the steps:
Step S31, provides Semiconductor substrate, in this Semiconductor substrate, has grid structure, around this grid structureBe surrounded by gate lateral wall;
Step S32, carries out etching to the Semiconductor substrate of described grid structure both sides, to form groove;
Step S33, adopts annealing process to heat-treat described gate lateral wall;
Step S34, carries out wet-cleaning to described Semiconductor substrate;
Step S35, deposit Germanium silicon in described groove.
Be elaborated below in conjunction with Fig. 4 to Fig. 6.
With reference to figure 4, Semiconductor substrate 30 is provided, in this Semiconductor substrate 30, be formed with grid structure 32, these gridElectrode structure 32 is surrounded by gate lateral wall 33 around.
Wherein, Semiconductor substrate 30 can be the conventional substrate of field of semiconductor processing, for example silicon substrate. Should be partlyIn conductive substrate 30, can be formed with isolation structure 31, for example fleet plough groove isolation structure.
Grid structure 32 can comprise gate dielectric layer, is positioned at the gate electrode on gate dielectric layer and is positioned on gate electrodeCap layer. Wherein, the material of gate dielectric layer can be silica, and the material of gate electrode can be polysilicon, cap layerMaterial can be silicon nitride.
Gate lateral wall 33 is enclosed in around grid structure 32, and the material of gate lateral wall 33 can be for example silicon nitride.Or gate lateral wall 33 can also be the laminated construction that silicon nitride and silica form.
The formation technique of grid structure 32 and gate lateral wall 33 can adopt any suitable work in prior artSkill, is not described in detail here.
With reference to figure 5, the Semiconductor substrate 10 of grid structure 32 both sides is carried out to etching, in the position in source region and drain regionPut and form groove 14.
Groove 14 for example can adopt dry etching to form. The shape of groove 14 is preferably " Σ " shape (SigmaShape) be, also that the sidewall of both sides is outwards outstanding.
After forming groove 34, adopt annealing process to heat-treat gate lateral wall 33, to improve gridSidewall 33 membranous, makes it finer and close.
As a preferred example, the material of gate lateral wall 33 is silicon nitride, adopts rapid thermal anneal process(RTP) gate lateral wall 33 is heat-treated. The optimizing technology parameters of quick thermal treatment process is as follows: temperatureBe 850 DEG C～1000 DEG C, the time is 0～15 second, and gas is the gaseous mixture of nitrogen or helium or nitrogen and heliumBody. Wherein, in the time that annealing time is 0 second, in fact this annealing process changes spike (spike) lehr attendant intoSkill.
Afterwards, Semiconductor substrate is carried out to wet-cleaning. For example, adopt the cleaning fluid that comprises hydrofluoric acid to carry out clearlyWash, to reduce the defect on Semiconductor substrate 30 surfaces. Owing to previously carrying out rapid thermal anneal process, gate electrode sideEnough densifications of wall 33, in wet-cleaning process, cleaning fluid is very little to the damage of gate lateral wall 33.
Adopt in the example that silicon nitride material, cleaning fluid comprise hydrofluoric acid at gate lateral wall 33, applicant is by thoroughlyRadio mirror scanning discovery, after wet-cleaning, the gate lateral wall 33 of silicon nitride material is not almost cleaned liquidCorrosion, wherein almost without any defect.
With reference to figure 6, after wet-cleaning, deposit Germanium silicon 35 in the groove of grid structure 32 both sides. Germanium silicon 35Formation method can be for example selective epitaxial process. The surface of the germanium silicon 35 forming can serve as a contrast higher than semiconductorThe surface at the end 30.
Afterwards, can complete the transistorized manufacture process of embedded germanium silicon PMOS according to conventional technique. ExampleAs, can in germanium silicon 35, inject P type ion, to form source region and drain region; Again at whole semiconductor liningMetallization medium layer at the end 30, and in dielectric layer, form contact embolism.
The technical scheme of the embodiment of the present invention is applicable to the embedded germanium silicon PMOS transistor of various technological levels,Be particularly useful for 40 nanometers and the PMOS transistor of high technology level more.
Although the present invention with preferred embodiment openly as above, it is not for limiting the present invention, Ren HebenThose skilled in the art without departing from the spirit and scope of the present invention, can make possible variation and repairChange, therefore protection scope of the present invention should be as the criterion with the scope that the claims in the present invention were defined.
Claims (5)
1. the transistorized formation method of embedded germanium silicon PMOS, is characterized in that, comprising:
Semiconductor substrate is provided, in this Semiconductor substrate, has grid structure, this grid structure is surrounded by grid aroundUtmost point sidewall;
Semiconductor substrate to described grid structure both sides is carried out etching, to form groove;
Adopt annealing process to heat-treat described gate lateral wall;
Described Semiconductor substrate is carried out to wet-cleaning;
Deposit Germanium silicon in described groove.
2. the transistorized formation method of embedded germanium silicon PMOS according to claim 1, is characterized in that,Described annealing process is rapid thermal anneal process.
3. the transistorized formation method of embedded germanium silicon PMOS according to claim 2, is characterized in that,The technological parameter of described rapid thermal anneal process is: temperature is 850 DEG C～1000 DEG C, and the time is 0～15 second, gasFor the mist of nitrogen or helium or nitrogen and helium.
4. according to the transistorized formation method of embedded germanium silicon PMOS described in any one in claims 1 to 3,It is characterized in that, the material of described sidewall is silicon nitride.
5. the transistorized formation method of embedded germanium silicon PMOS according to claim 1, is characterized in that,The cleaning fluid that described wet-cleaning adopts comprises hydrofluoric acid.
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| CN201410654357.1A CN105590864A (en) | 2014-11-17 | 2014-11-17 | Method for forming embedded SiGe PMOS transistor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110120368A (en) * | 2018-02-05 | 2019-08-13 | 联华电子股份有限公司 | The method for forming dynamic random access memory |
| CN114335256A (en) * | 2022-03-10 | 2022-04-12 | 北京通美晶体技术股份有限公司 | Method for cleaning germanium wafer by dry method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856258A (en) * | 2011-07-01 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
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- 2014-11-17 CN CN201410654357.1A patent/CN105590864A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102856258A (en) * | 2011-07-01 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110120368A (en) * | 2018-02-05 | 2019-08-13 | 联华电子股份有限公司 | The method for forming dynamic random access memory |
| CN110120368B (en) * | 2018-02-05 | 2021-05-11 | 联华电子股份有限公司 | Method for forming dynamic random access memory |
| CN114335256A (en) * | 2022-03-10 | 2022-04-12 | 北京通美晶体技术股份有限公司 | Method for cleaning germanium wafer by dry method |
| CN114335256B (en) * | 2022-03-10 | 2022-05-20 | 北京通美晶体技术股份有限公司 | Method for cleaning germanium wafer by dry method |
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Application publication date: 20160518 |