CN116225142B - Non-resistance band gap reference voltage source, reference voltage generating method and integrated circuit - Google Patents
Non-resistance band gap reference voltage source, reference voltage generating method and integrated circuit Download PDFInfo
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- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The application provides a resistance-free band gap reference voltage source, a reference voltage generation method and an integrated circuit. The reference voltage source includes first and second circuits; the reference voltage generating method is that the first circuit generates a first voltage with a negative temperature coefficient through the bipolar device, and the second circuit generates a second voltage with a positive temperature coefficient. The second circuit comprises a plurality of voltage buffers which are sequentially connected in series, and generates offset voltage of positive temperature coefficient through MOS tubes working in a subthreshold region, and the offset voltage and the second voltage form second voltage together. The first and second voltages together form a reference voltage, and the negative temperature coefficient and the positive temperature coefficient are matched such that the reference voltage has a zero temperature coefficient. The first stages of voltage buffers adopt PMOS tube differential pairs, and the later stages adopt NMOS tube differential pairs. An equivalent width to length ratio adjustable voltage buffer of the differential pair can also be included. The integrated circuit includes the reference voltage source described above. The method has the advantages of flexible configuration, low power consumption, small chip area and high voltage precision.
Description
Technical Field
The present disclosure relates to reference voltage sources and integrated circuits, and more particularly to a non-resistive bandgap reference voltage source, a reference voltage generating method, and an integrated circuit.
Background
Bandgap reference voltage sources are capable of providing reference voltages that are nearly independent of temperature variations and are widely used in various types of integrated circuits. To provide a zero temperature coefficient reference voltage, it is generally necessary to add two voltage quantities having opposite temperature coefficients.
In a conventional bandgap reference voltage source structure, the base emitter voltage of a bipolar transistorHaving a negative temperature coefficient, when two bipolar transistors are operated at different current densities>Voltage difference->Has a positive temperature coefficient. Through at least two resistors and one operational amplifier, can be +.>And->The weighted addition yields a reference voltage with zero temperature coefficient.
In these circuit structures, since the magnitude of the current is determined by the resistance, a large resistance is required to achieve low power consumption, which often means that a large chip area is occupied, and the cost and the difficulty of application of the circuit are increased.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present application is to provide a low-power consumption resistance-free bandgap reference voltage source, a corresponding reference voltage generating method, and an integrated circuit based on the reference voltage source.
In order to achieve the above object, the present application provides the following technical solutions.
A non-resistive bandgap reference voltage source comprising: a first circuit for generating a first voltage with a negative temperature coefficient through the bipolar device; a second circuit for generating a second voltage having a positive temperature coefficient, the second circuit comprising a plurality of voltage buffers serially connected in sequence; the voltage buffer generates offset voltage of positive temperature coefficient through MOS tube working in sub-threshold area, and the offset voltage of the voltage buffer forms the second voltage together; the first voltage is connected to the input end of the second circuit, and the first voltage and the second voltage form a reference voltage together; the negative temperature coefficient and the positive temperature coefficient are matched so that the reference voltage has a zero temperature coefficient.
In some embodiments, the voltage buffer comprises a differential pair, a tail current source and a current mirror, wherein the differential pair comprises an in-phase end MOS (metal oxide semiconductor) tube and an opposite-phase end MOS tube which all work in a subthreshold region, the in-phase end MOS tube is connected with a reference current branch of the current mirror, and the opposite-phase end MOS tube is connected with a mirror image current branch of the current mirror; the grid electrode of the MOS tube at the same phase end forms the input end of the voltage buffer, and the grid electrode and the drain electrode of the MOS tube at the opposite phase end are in short circuit to form the output end of the voltage buffer; the ratio of the width to length of the differential pair isAnd enabling the offset voltage to be:
；
wherein the method comprises the steps ofFor the purpose of regulating voltage>And->The voltages at the input and output of the voltage buffer respectively,and->Gate-source voltages of the in-phase end MOS tube and the reversed-phase end MOS tube respectively,/->Is the thermal voltage of the MOS tube,for the current ratio of the current mirror, +.>Is the substrate coefficient of the MOS tube.
In some embodiments, the voltage buffer includes a first voltage buffer and a second voltage buffer; the differential pair of the first voltage buffer is formed by PMOS tubes, and the differential pair of the second voltage buffer is formed by NMOS tubes; the second circuit comprises N voltage buffers, and the first N is 1 The voltage buffers are first voltage buffers, and then N-N 1 The voltage buffers are second voltage buffers.
In some embodiments, the current ratio of the current mirror is 1; the ratio of the width to the length is 2 or 4 or 8 or 16; the first circuit comprises a first current source and a first triode, wherein the base electrode and the collector electrode of the first triode are in short circuit, the first current source supplies power for the first triode, and the voltage drop between the base electrode and the emitting stage of the first triode forms the first voltage.
In some embodiments, the differential pair is further connected to an aspect ratio adjustment circuit, such that the voltage buffer forms an adjustable voltage buffer; when the differential pair is formed by NMOS tubes, the in-phase end MOS tube is used as an adjusted MOS tube to be connected to the width-to-length ratio adjusting circuit, and when the differential pair is formed by PMOS tubes, the opposite-phase end MOS tube is used as an adjusted MOS tube to be connected to the width-to-length ratio adjusting circuit; the width-to-length ratio regulating circuit comprises a first parallel branch circuit to an Mth parallel branch circuit, and each parallel branch circuit comprises a switching tube and a regulating tube which are connected in series; when the switching tube is conducted, the regulating tube of the parallel branch is connected in parallel to the regulated MOS tube; the width-to-length ratio of the regulating tube of the first parallel branch is equal to that of the regulated MOS tube, and the width-to-length ratios of the regulating tubes of the first parallel branch to the Mth parallel branch are multiplied in sequence; the controlled MOS tube and the width-to-length ratio adjusting circuit form an equivalent MOS tube, and the control ends of the M switching tubes are connected to an M-bit control bus, so that the control bus is suitable for adjusting the equivalent width-to-length ratio of the equivalent MOS tube.
In some embodiments, the number of parallel branches is 4, and the ratio of the width to length of the differential pair of the adjustable voltage buffer is 1; or, the number of the parallel branches is 3, and the ratio of the width to the length of the differential pair of the adjustable voltage buffer is 2.
In some embodiments, the second circuit includes 3 first voltage buffers and 5 second voltage buffers connected in sequence; wherein at least one of the 5 second voltage buffers is an adjustable voltage buffer.
In some embodiments, the current mirror has a current ratio of 2.
The present application also provides an integrated circuit comprising any of the aforementioned non-resistive bandgap reference voltage sources.
The application also provides a band gap reference voltage generation method, which is used for generating a first voltage with a negative temperature coefficient through a bipolar device; generating a positive temperature coefficient second voltage through a plurality of voltage buffers which are sequentially connected in series, wherein the voltage buffers generate positive temperature coefficients through MOS (metal oxide semiconductor) tubes working in a subthreshold regionThe offset voltages of the voltage buffers jointly generate the second voltage; the first voltage and the second voltage jointly generate a reference voltage, and the negative temperature coefficient is matched with the positive temperature coefficient so that the reference voltage has a zero temperature coefficient; the voltage buffer comprises a differential pair, a tail current source and a current mirror, wherein the differential pair comprises an in-phase end MOS tube and an opposite-phase end MOS tube which are all operated in a subthreshold region, the in-phase end MOS tube is connected with a reference current branch of the current mirror, and the opposite-phase end MOS tube is connected with a mirror image current branch of the current mirror; the grid electrode of the MOS tube at the same phase end forms the input of the voltage buffer, and the grid electrode and the drain electrode of the MOS tube at the opposite phase end are in short circuit to form the output of the voltage buffer; the ratio of the width to length of the differential pair isAnd enabling the offset voltage to be:
；
wherein the method comprises the steps ofFor the purpose of regulating voltage>And->Gate-source voltages of the in-phase end MOS tube and the reversed-phase end MOS tube respectively,/->Is MOS tube thermal voltage->For the current ratio of the current mirror, +.>Is the substrate coefficient of the MOS tube.
Various embodiments of the present application have at least one of the following technical effects:
1. the zero temperature coefficient reference voltage is formed by simply superposing the first voltage with the negative temperature coefficient and the offset voltage with the positive temperature coefficient of the voltage buffer, and the weighting is not needed by a resistor, so that the chip area with low power consumption and small size can be realized;
2. different width-to-length ratios are set for the differential pair working in the subthreshold region, so that offset voltage with positive temperature coefficient is obtained, and the circuit is simple and low in power consumption; by utilizing the logarithmic characteristic of the positive temperature coefficient, the total chip area of the second circuit can be reduced through a multi-stage voltage buffer;
3. the overall performance of the second circuit can be optimized by using a PMOS input stage for the first few stages of voltage buffers at lower input voltages and an NMOS input stage for the second few stages of voltage buffers at higher input voltages;
4. through the arrangement of the width-to-length ratio regulating circuit, the offset voltage and the positive temperature coefficient of part of the voltage buffers can be accurately regulated, and other parameters of the second circuit, such as the number of stages of the voltage buffers, the width-to-length ratio setting of the differential pair of each stage of the voltage buffers and the like, can be flexibly regulated;
5. the chip size occupied by the second circuit can be further reduced by setting the current mirror of the voltage buffer to be asymmetric.
Drawings
The above features, technical features, advantages and implementation of the present invention will be further described in the following description of preferred embodiments with reference to the accompanying drawings in a clear and easily understood manner.
FIG. 1 is a schematic diagram of a resistance-free bandgap reference voltage source structure of an embodiment;
FIG. 2 is a first voltage buffer circuit diagram of one embodiment;
FIG. 3 is a second voltage buffer circuit diagram of one embodiment;
FIG. 4 is a third voltage buffer circuit diagram of one embodiment;
FIG. 5 is a schematic diagram of another embodiment of a resistance-free bandgap reference voltage source structure;
reference numerals illustrate:
100. first circuit, 200, second circuit, 210, first voltage buffer, 220, second voltage buffer, 230, adjustable voltage buffer, 231, width to length ratio adjustment circuit.
Detailed Description
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will explain specific embodiments of the present application with reference to the accompanying drawings. The drawings in the following description are only examples of the present application and other drawings and other embodiments may be made by those skilled in the art without undue burden.
For simplicity of the drawing, only the parts relevant to the present application are schematically shown in each drawing, and they do not represent the actual structure thereof as a product. In some of the figures, only one of which is schematically depicted, or only one of which is labeled, components having the same structure or function. Herein, "a" means not only "only this one" but also "more than one" case. The term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations. The terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
Unless specifically stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
Embodiment one. As shown in fig. 1, the present embodiment is a low-power consumption resistance-free bandgap reference voltage source, comprising a first circuit 100 and a second circuit 200, the first circuit 100 generates a first voltage of negative temperature coefficient by a bipolar deviceThe method comprises the steps of carrying out a first treatment on the surface of the The second circuit 200 is configured to generate a second voltage having a positive temperature coefficient, and the second circuit 200 includes a plurality of voltage buffers serially connected in sequence; wherein, the voltage buffer generates offset voltage of positive temperature coefficient through MOS tube working in sub-threshold regionOffset voltage of voltage buffer +.>Together forming a second voltage; first voltage->Connected to the input of the second circuit 200, a first voltage +.>And the second voltage together form a reference voltage +.>The method comprises the steps of carrying out a first treatment on the surface of the First voltage->Matching the negative temperature coefficient of the second voltage with the positive temperature coefficient of the reference voltage +.>With a zero temperature coefficient.
As shown in fig. 1, the first circuit 100 includes a first current source I 1 And a first triode Q 1 First triode Q 1 Is grounded after being short-circuited with the base and the collector, a first current source I 1 Is a first triode Q 1 Providing current, a first triode Q 1 The voltage drop between the base and emitter of (2) constitutes a first voltage. First triode Q of the present embodiment 1 The first circuit is constituted by NPN triode, the base and collector of NPN triode are short-circuited, then the current source is connected, and the emitter is grounded, and the first voltage is formed by the voltage drop between base and emitter>。
First current source I 1 Is smaller in current, Q 1 Generating a voltage having a negative temperature coefficient；P 1 、P 2 To P N Is an N-stage voltage buffer responsible for generating offset voltage with positive temperature coefficient>Offset voltage of all voltage buffers +.>The sum is the second voltage, the first voltage +.>And a second voltage, which together produce a zero temperature coefficient reference voltage +.>As shown in formula (1):
（1）。
the specific structure of the voltage buffer can be various, and the invention point of the application is that a mode of sequentially connecting the voltage buffers in series is adopted to realize more accurate reference voltageAnd low power consumption and more flexible circuit arrangement and smaller chip size are achieved.
Embodiment two. On the basis of embodiment one, this embodiment describesOne preferred arrangement of the voltage buffer is described. As shown in fig. 2, the voltage buffer of the present embodiment includes a differential pair, a tail current source I b And a current mirror; the differential pair comprises a first MOS tube M1 and a second MOS tube M2 which are both operated in a subthreshold region, wherein the first MOS tube M1 is a same-phase end MOS tube, and the second MOS tube M2 is an opposite-phase end MOS tube. The first MOS tube M1 is connected with a reference current branch of the current mirror, namely, is connected with a branch formed by the third MOS tube M3, and the second MOS tube M2 is connected with a mirror image current branch of the current mirror, namely, is connected with a branch formed by the fourth MOS tube M4.
The in-phase end MOS tube of the differential pair, namely the grid electrode of the first MOS tube M1 in FIG. 2, forms the input end of the voltage bufferThe inverting-end MOS tube, namely the second MOS tube M2 gate-drain short circuit in figure 2, forms the output end of the voltage buffer +.>The method comprises the steps of carrying out a first treatment on the surface of the Offset voltageAs shown in formula (2):
（2）；
wherein the method comprises the steps ofAnd->The gate source voltages of the first MOS transistor M1 and the second MOS transistor M2 are respectively. For simplicity, equation (2) includes the case of both circuit configurations of fig. 2 and 3. According to the MOS transistor drain-source current formula in the subthreshold region provided by the prior art:
（3）；
wherein the method comprises the steps ofIs drain-source current->Is MOS tube thermal voltage->Is the substrate coefficient of the MOS tube, W/L is the width-to-length ratio of the MOS tube, and +.>Is the threshold voltage of MOS tube, +.>Capacitance per unit area of gate oxide, +.>Electron mobility for inversion layer; wherein only MOS transistor is hot-pressed +>And temperature dependent. The deformation of the above method can be obtained:
（4）；
further obtaining the offset voltage according to the formula (4)Is defined by the specific calculation formula:
（5）；
wherein the method comprises the steps ofIs the ratio of the width to length ratio of the differential pair, +.>The current ratio of the current mirror is the ratio of the width-to-length ratio of the fourth MOS transistor M4 to the width-to-length ratio of the third MOS transistor M3.The current ratio of a current mirror is usually +.>1->Preferably a value of 2 or 4 or 8 or 16. For the sake of simplicity of the formula, unless otherwise specified, the aspect ratio of the differential pair in the present application refers to the aspect ratio of the MOS transistor with a larger aspect ratio in the differential pair divided by the aspect ratio of the MOS transistor with a smaller aspect ratio, except that the aspect ratio of the differential pair is 1 when the differential pair is symmetrically arranged, so that the aspect ratio is always greater than or equal to 1. Likewise, the current ratio of the current mirror is 1, or the larger current in the reference current branch and the mirror current branch divided by the smaller current, thus +.>And always 1 or more, so that the formula (5) can be used for both the circuit configurations of fig. 2 and 3. Since the current mirrors are typically symmetrically arranged, the above formula is typically:
（6）。
the voltage buffer of the embodiment has simple structure and reliable operation. The innovation point of the application is not only that the specific structure of the voltage buffer is adopted, but also that the differential pair working in the subthreshold region is utilized, and the offset voltage with positive temperature coefficient is obtained by setting different width-to-length ratios for the differential pair. In practice, the voltage buffer may be implemented by various voltage followers or differential amplifiers including differential pairs, and only needs to make the differential pairs work in sub-threshold regions through circuit design, and set two MOS transistors of the differential pairs to different width-to-length ratios. The differential pair working in the subthreshold region not only can realize offset voltage with positive temperature coefficient +.>Also, since it operates at a very small current in the nA stage, extremely low power consumption can be achieved.
It can be found by observing the formula (6) that, because of the characteristics of the logarithmic function, if simply by increasingIs less increased in positive temperature coefficient. Such as handle->Increasing from 16 to 256%>The coefficient of (2) is only from 2.77>To 5.55. The positive temperature coefficient is not increased much, but the aspect ratio of one of the MOS transistors, such as the second MOS transistor M2 in fig. 2, is increased exponentially, which often means a sharp increase in chip area, and makes layout matching difficult.
But if the characteristics are based on logarithmic operation,it can be found that the same ++ ->The increase of the coefficient of (2) greatly saves the chip area. The settings of the voltage buffers at each stage may be different from each other, but for ease of understanding, it is assumed that the settings of the voltage buffers at each stage are the same, and the bandgap reference voltage generated after passing through the N-stage voltage buffers is:
（7）；
due to MOS tube thermoelectricPressingThe calculation formula of (this formula is the prior art):
（8）；
wherein the method comprises the steps ofIs Bozmann constant, < >>Absolute temperature>Is an electron charge; by designing N and->The value of (1) is such that
（9）；
The bandgap reference voltage with zero temperature coefficient can be obtained, namely:
（10）。
embodiment three. On the basis of the second embodiment, this embodiment provides a preferred arrangement of the second circuit 200. The N voltage buffers of the present embodiment include a plurality of first voltage buffers 210 and a plurality of second voltage buffers 220; the differential pair of the first voltage buffer 210 is formed by PMOS transistors as shown in fig. 2, and the differential pair of the second voltage buffer 220 is formed by NMOS transistors as shown in fig. 3. As shown in fig. 5, the second circuit 200 includes N voltage buffers, and the first N1 voltage buffers are the first voltage buffer 210, and the second N-N1 voltage buffers are the second voltage buffer 220, where N is a natural number greater than 1, and N1 is a natural number less than N. The two different types of voltage buffers can be combined to conveniently compensate the negative temperature coefficients of the bipolar transistors of different types under different processes, so that good expansibility is realized. In practical applications, the number of different types of voltage buffers can be freely combined as desired.
In the second embodiment, the structure of the PMOS transistor as the voltage buffer of the input stage is shown in fig. 2. Because of the conduction characteristics of the PMOS tube, the voltage buffer of the type can be connected with very low input voltage, and is particularly suitable for being used as a bipolar transistor, namely a first triode Q 1 The first few stages of voltage buffers thereafter. The first MOS tube M1 and the second MOS tube M2 are PMOS input pair tubes, and the width-to-length ratio of the second MOS tube M2 is the width-to-length ratio of the first MOS tube M1Multiple times. The third MOS tube M3 and the fourth MOS tube M4 form a current mirror, and the ratio of the width to the length is 1, so that the source leakage current of the first MOS tube M1 and the source leakage current of the second MOS tube M2 are equal. Due to tail current I b The first MOS transistor M1 and the second MOS transistor M2 are in the subthreshold region because they are very small.
The structure of the second voltage buffer 220 with the NMOS transistor as the input stage is shown in FIG. 3, and the NMOS transistor as the input stage can realize offset voltage with higher positive temperature coefficient under the same ratio of width to length than the PMOS transistor as the input stageThe number of voltage buffer stages is advantageously reduced. And because of the characteristic of NMOS tube, it is smaller than leakage current of PMOS tube at high temperature, therefore +.>The accuracy of (c) has less impact. However, the NMOS transistor as an input stage has poor performance when connected to a very low input voltage, so that the second voltage buffer 220 using the NMOS transistor as an input stage is arranged behind the first voltage buffer 210 using the corresponding PMOS transistor as an input stage to be used in cooperation. The fifth MOS tube M5 and the sixth MOS tube M6 are NMOS tube input pair tubes respectively forming a second voltage bufferThe in-phase end MOS tube and the opposite-phase end MOS tube of the device 220, the width-to-length ratio of the fifth MOS tube M5 is ≡f of the sixth MOS tube M6>Multiple times. The seventh MOS transistor M7 and the eighth MOS transistor M8 form a current mirror, and the ratio of the width to the length is 1, so that the source leakage currents of the fifth MOS transistor M5 and the sixth MOS transistor M6 are equal. Due to input voltage and tail current I b The fifth MOS transistor M5 and the sixth MOS transistor M6 are all in the subthreshold region because the fifth MOS transistor M and the sixth MOS transistor M6 are very small.
Example four. On the basis of the second or third embodiment, as shown in fig. 4, this embodiment illustrates that the voltage buffer can be set to be offset voltageAn adjustable voltage buffer 230. The differential pair of the adjustable voltage buffer 230 is also connected to an aspect ratio adjustment circuit 231 based on the circuit configuration of fig. 2 or 3. The differential pair shown in fig. 4 is composed of NMOS transistors, and the ratio of the width to the length of the differential pair is 1. At this time, the width-to-length ratio adjusting circuit 231 is connected to the in-phase side MOS transistor, that is, the ninth MOS transistor M9, so that it becomes an adjusted MOS transistor. When the differential pair is formed by PMOS transistors, the width-to-length ratio adjusting circuit 231 is connected to the inverting-side MOS transistor, so that the inverting-side MOS transistor becomes an adjusted MOS transistor. For example, when the first voltage buffer 210 shown in fig. 2 needs to be connected to a matching width-to-length ratio adjusting circuit, it should be connected to the second MOS transistor M2, so as to adjust the ratio of the width-to-length ratio of the differential pair.
As shown in fig. 4, the width-to-length ratio adjusting circuit 231 of the present embodiment includes a first parallel branch to a fourth parallel branch, each parallel branch including a switching tube and an adjusting tube connected in series; when the switch tube is conducted, the regulating tube of the parallel branch is connected in parallel to the regulated MOS tube, namely connected in parallel to the ninth MOS tube M9. Specifically, the eleventh MOS transistor M11 to the fourteenth MOS transistor M14 are all adjusting transistors, and the seventeenth MOS transistor M17 to the twentieth MOS transistor M20 are switching transistors, which are sequentially paired to form first to fourth parallel branches.
The width-to-length ratio of the regulating tube of the first parallel branch, namely the eleventh MOS tube M11, is equal to the width-to-length ratio of the ninth MOS tube M9; the width-length ratios of the regulating tubes from the first parallel branch to the fourth parallel branch, namely the eleventh MOS tube to the fourteenth MOS tube are multiplied in sequence and are respectively 1, 2, 4 and 8 times of the width-length ratio of the ninth MOS tube M9. The control ends of the 4 switching tubes, i.e. their gates, are connected to a 4-bit control bus (i.e. the 4-bit trim bus in fig. 4), so that the control bus is adapted to adjust the equivalent width-to-length ratio of the equivalent MOS tube formed by the ninth MOS tube M9 and the width-to-length ratio adjusting circuit 231. Specifically, the width-to-length ratio of the ninth MOS transistor M9 is set to be (W/L), and the 4-bit control bus can provide 16 kinds of control signals represented by 4-bit binary data 0000 to 1111, so that the equivalent width-to-length ratio of the equivalent MOS transistor formed by the ninth MOS transistor M9 and the width-to-length ratio adjusting circuit 231 is adjustable between (W/L) to 16 (W/L), and the resolution is adjusted to be doubled (W/L).
In addition, the number of parallel branches may be 3, and the ratio of the width to length ratio of the differential pair of the adjustable voltage buffer 230 is set to 2:1. if the width-to-length ratio of the MOS tube at the in-phase end is 2 (W/L), the width-to-length ratios of the 3 regulating tubes are sequentially 2 (W/L), 4 (W/L) and 8 (W/L), the equivalent width-to-length ratio of the equivalent MOS tube formed by the MOS tube at the in-phase end and the width-to-length ratio regulating circuit 231 is adjustable between 2 (W/L) and 16 (W/L), and the regulating resolution is 2 (W/L); the corresponding control bus requires only 3 bits. The circuit is simpler and can be used for coarse adjustment.
According to the requirement, other numbers of M parallel branches can be arranged, and M-bit control buses are correspondingly arranged, so that the M-th-power equivalent width-to-length ratio of 2 is realized. At this time, according to equation (6), the offset voltage of the adjustable voltage buffer 230 can be adjustedAnd adjusting the positive temperature coefficient. In addition, a tenth MOS transistor M10 and a ninth MOS transistor M9 in fig. 4 form a differential pair, and a fifteenth MOS transistor M15 and a sixteenth MOS transistor M16 form a current mirror. C in fig. 2 to 4 is a capacitance.
According to the simulation result, a preferred arrangement of the second circuit 200 comprises 3 first voltage buffers 210 and 5 second voltage buffers 220 connected in sequence; two of the 5 second voltage buffers 220 are adjustable voltage buffers 230.
The addition of the adjustable voltage buffer 230 can greatly increase the flexibility of circuit configuration, improve the reliability of the circuit and reduce the test cost. For example, when the resistance-free band-gap reference voltage source is used for an MCU, after the current sheet is completed, a trim signal of a control bus can be controlled through a register of the MCU, so that offset voltages with different positive temperature coefficients can be conveniently realizedTo finally achieve an accurate reference voltage +.>. The adjustable range of 4 bits is adopted in fig. 4, and precise adjustment of the ratio of the width to the length of the differential pair in the range from 1:1 to 16:1 can be realized. In practical applications, the bit number of the trim signal can be increased or decreased as required, and the number of stages of the adjustable voltage buffer 230 can be flexibly increased or decreased. In fig. 4, the ninth MOS transistor M9 to the fourteenth MOS transistor M14 are all in the subthreshold region, wherein the eleventh MOS transistor M11 to the fourteenth MOS transistor M14 are adjustable portions.
As shown in fig. 5, the MOS transistors of the present embodiment are all implemented based on a 40nm CMOS process, and the first transistor Q of the first circuit 100 1 The subsequent second circuit 200 comprises 8 stages of voltage buffers, wherein the first 3 stages are the first voltage buffer 210 with PMOS as input stage and the second 5 stages are the second voltage buffer 220 with NMOS as input stage; the 6 th and 7 th stages of the 5 second voltage buffers 220 are adjustable voltage buffers 230.I 1 Tail current I of each voltage buffer b All adopt 5nA bias current to supply power, the total current of whole reference voltage source is about 45nA, has realized ultra-low power consumption. Based on the results of the simulation calculations, a reference voltage is typicallyThe rate of change with temperature was about 15.75 ppm/. Degree.C; the operable power supply voltage range is 1.71V-3.60V. According to Monte Carlo simulation results with the temperature ranging from-40 ℃ to 135 ℃, the reference voltage is +.>The voltage variation range of the voltage-variable resistor is less than +/-2%, and higher precision is achieved.
Example five. This embodiment is a variation of the second to fourth embodiments. In embodiment II, it is mentioned that the current ratio of the current mirror in equation (5)Typically 1, but may also be set to an integer multiple greater than 1, for example, the current mirror current ratio of the first voltage buffer 210 and the second voltage buffer 220 in both the second and third embodiments may be set to 2. At this time, the ratio of the width to length ratio of the respective differential pairs of the first voltage buffer 210 and the second voltage buffer 220 may be reduced to half, for example, from 16 times to 8 times, and as can be seen from comparison between equation (5) and equation (6), the same can be achieved>. Alternatively, the ratio of the width to length ratios of the differential pairs may be kept unchanged, and the number of stages of the voltage buffers included in the second circuit 200 may be correspondingly reduced, further increasing the flexibility of the circuit arrangement.
Example six. This embodiment is an integrated circuit comprising a non-resistive bandgap reference voltage source of any of the embodiments described above. Since a large-scale integrated circuit such as an MCU or MPU generally includes an AD conversion channel, a reference voltage source is required to secure its conversion accuracy. The resistance-free band gap reference voltage source does not need to be provided with a resistor, occupies small chip area, is low in power consumption, is high in precision and flexible in setting, and can be used for selecting a specific circuit according to specific requirements.
Example seven. The embodiment is a band gap reference voltage generating method. In particular, the present embodiment generates a negative temperature coefficient first voltage through a bipolar deviceThe method comprises the steps of carrying out a first treatment on the surface of the Generating a positive temperature coefficient second voltage through a plurality of voltage buffers which are sequentially connected in series, wherein the voltage buffers generate offset voltage +_ with positive temperature coefficient through MOS (metal oxide semiconductor) tubes working in a subthreshold region>Offset voltage +.>Collectively generating a second voltage; first voltage->And a second voltage to generate a reference voltage +.>First voltage->Matching the negative temperature coefficient of the second voltage with the positive temperature coefficient of the reference voltage +.>With a zero temperature coefficient. Wherein the first voltage->And a specific generation method of the second voltage, and a realization method of the zero temperature coefficient refer to the detailed description of the first to fifth embodiments, and relate to the formulas (1) to (10).
Wherein the specific derivation procedure from the formula (4) to the formula (5) is as follows. Taking the circuit structure of fig. 3 as an example, the width-to-length ratio of the first MOS transistor M1 is the width-to-length ratio of the second MOS transistor M2The width-to-length ratio of the first MOS transistor M1 is +.>The width-to-length ratio of the (W/L) and the second MOS tube M2 is (W/L). At this time, the width-to-length ratio of the fourth MOS transistor M4 of the current mirror needs to be set to be +.>The drain and source of the second MOS transistor M1 are multiplied according to the characteristics of the current mirrorCurrent->Drain-source current for first MOS transistor M1>Is->Multiple, and according to equation (4), can be obtained:
（11）。
the foregoing description is only of the preferred embodiments of the present application and the technical principles employed, and various obvious changes, modifications and substitutions may be made without departing from the spirit of the present application. Additional advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. The above embodiments and features of the embodiments may be combined with each other without conflict.
Claims (9)
1. A non-resistive bandgap reference voltage source, comprising:
a first circuit for generating a first voltage with a negative temperature coefficient through the bipolar device;
a second circuit for generating a second voltage having a positive temperature coefficient, the second circuit comprising a plurality of voltage buffers serially connected in sequence;
the voltage buffer generates offset voltage of positive temperature coefficient through MOS tube working in sub-threshold area, and the offset voltage of the voltage buffer forms the second voltage together; the first voltage is connected to the input end of the second circuit, and the first voltage and the second voltage form a reference voltage together; the negative temperature coefficient is matched with the positive temperature coefficient, so that the reference voltage has a zero temperature coefficient;
the voltage buffer comprises a differential pair, a tail current source and a current mirror; the differential pair comprises an in-phase end MOS tube and an opposite-phase end MOS tube which are both operated in a subthreshold region, the in-phase end MOS tube is connected with a reference current branch of the current mirror, and the opposite-phase end MOS tube is connected with a mirror image current branch of the current mirror; the differential pair of at least one voltage buffer is also connected to an aspect ratio adjusting circuit, so that the voltage buffer forms an adjustable voltage buffer; when the differential pair is formed by NMOS tubes, the in-phase end MOS tube is used as an adjusted MOS tube to be connected to the width-to-length ratio adjusting circuit, and when the differential pair is formed by PMOS tubes, the opposite-phase end MOS tube is used as an adjusted MOS tube to be connected to the width-to-length ratio adjusting circuit;
the width-to-length ratio regulating circuit comprises a first parallel branch circuit to an Mth parallel branch circuit, and each parallel branch circuit comprises a switching tube and a regulating tube which are connected in series; when the switching tube is conducted, the regulating tube of the parallel branch is connected in parallel to the regulated MOS tube;
the width-to-length ratio of the regulating tube of the first parallel branch is equal to that of the regulated MOS tube, and the width-to-length ratios of the regulating tubes of the first parallel branch to the Mth parallel branch are multiplied in sequence;
the controlled MOS tube and the width-to-length ratio adjusting circuit form an equivalent MOS tube, and the control ends of the M switching tubes are connected to an M-bit control bus, so that the control bus is suitable for adjusting the equivalent width-to-length ratio of the equivalent MOS tube.
2. The resistively bandgap reference voltage source of claim 1, characterized in that,
the grid electrode of the MOS tube at the same phase end forms the input end of the voltage buffer, and the grid electrode and the drain electrode of the MOS tube at the opposite phase end are in short circuit to form the output end of the voltage buffer;
the ratio of the width to length of the differential pair isMake the followingThe offset voltage is as follows:
；
wherein the method comprises the steps ofFor the purpose of regulating voltage>And->The voltages at the input and output of the voltage buffer respectively,and->Gate-source voltages of the in-phase end MOS tube and the reversed-phase end MOS tube respectively,/->Is MOS tube thermal voltage->For the current ratio of the current mirror, +.>Is the substrate coefficient of the MOS tube.
3. The resistively bandgap reference voltage source of claim 2, characterized in that,
the voltage buffer comprises a first voltage buffer and a second voltage buffer; the differential pair of the first voltage buffer is formed by PMOS tubes, and the differential pair of the second voltage buffer is formed by NMOS tubes;
the second circuit comprises N voltage buffers, and the first N is 1 Voltage slowThe flusher is a first voltage buffer, and is N-N after 1 The voltage buffers are second voltage buffers.
4. The resistively bandgap reference voltage source of claim 2, characterized in that,
the current ratio of the current mirror is 1; the ratio of the width to the length is 2 or 4 or 8 or 16;
the first circuit comprises a first current source and a first triode, wherein the base electrode and the collector electrode of the first triode are in short circuit, the first current source supplies power for the first triode, and the voltage drop between the base electrode and the emitting stage of the first triode forms the first voltage.
5. A resistively bandgap reference voltage source according to claim 3, characterized in that,
the number of the parallel branches is 4, and the ratio of the width to the length of the differential pair of the adjustable voltage buffer is 1;
or alternatively, the first and second heat exchangers may be,
the number of the parallel branches is 3, and the ratio of the width to the length of the differential pair of the adjustable voltage buffer is 2.
6. A resistively bandgap reference voltage source according to claim 3, characterized in that,
the second circuit comprises 3 first voltage buffers and 5 second voltage buffers which are connected in sequence; wherein at least one of the 5 second voltage buffers is an adjustable voltage buffer.
7. The resistively bandgap reference voltage source of claim 2, characterized in that,
the current ratio of the current mirror is 2.
8. An integrated circuit, characterized in that,
comprising a non-resistive bandgap reference voltage source as claimed in any of claims 1 to 7.
9. A band gap reference voltage generation method is characterized in that,
generating a first voltage of negative temperature coefficient by a bipolar device;
generating a second voltage with a positive temperature coefficient through a plurality of voltage buffers which are sequentially connected in series, wherein the voltage buffers generate offset voltages with the positive temperature coefficient through MOS (metal oxide semiconductor) tubes working in a subthreshold region, and the offset voltages of the voltage buffers jointly generate the second voltage; the first voltage and the second voltage jointly generate a reference voltage, and the negative temperature coefficient is matched with the positive temperature coefficient so that the reference voltage has a zero temperature coefficient;
the voltage buffer comprises a differential pair, a tail current source and a current mirror, wherein the differential pair comprises an in-phase end MOS tube and an opposite-phase end MOS tube which are all operated in a subthreshold region, the in-phase end MOS tube is connected with a reference current branch of the current mirror, and the opposite-phase end MOS tube is connected with a mirror image current branch of the current mirror;
the grid electrode of the MOS tube at the same phase end forms the input of the voltage buffer, and the grid electrode and the drain electrode of the MOS tube at the opposite phase end are in short circuit to form the output of the voltage buffer;
the ratio of the width to length of the differential pair isAnd enabling the offset voltage to be:
；
wherein the method comprises the steps ofFor the purpose of regulating voltage>And->The same-phase end MOS tube and the same-phase end MOS tube are respectivelyGate-source voltage of inverted-end MOS transistor, +.>Is MOS tube thermal voltage->For the current ratio of the current mirror, +.>The substrate coefficient of the MOS tube;
the differential pair of at least one voltage buffer is also connected to an aspect ratio adjusting circuit, so that the voltage buffer forms an adjustable voltage buffer; when the differential pair is formed by NMOS tubes, the in-phase end MOS tube is used as an adjusted MOS tube to be connected to the width-to-length ratio adjusting circuit, and when the differential pair is formed by PMOS tubes, the opposite-phase end MOS tube is used as an adjusted MOS tube to be connected to the width-to-length ratio adjusting circuit;
the width-to-length ratio regulating circuit comprises a first parallel branch circuit to an Mth parallel branch circuit, and each parallel branch circuit comprises a switching tube and a regulating tube which are connected in series; when the switching tube is conducted, the regulating tube of the parallel branch is connected in parallel to the regulated MOS tube;
the width-to-length ratio of the regulating tube of the first parallel branch is equal to that of the regulated MOS tube, and the width-to-length ratios of the regulating tubes of the first parallel branch to the Mth parallel branch are multiplied in sequence;
the controlled MOS tube and the width-to-length ratio adjusting circuit form an equivalent MOS tube, and the control ends of the M switching tubes are connected to an M-bit control bus, so that the control bus is suitable for adjusting the equivalent width-to-length ratio of the equivalent MOS tube.
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| KR20000070664A (en) * | 1997-12-02 | 2000-11-25 | 요트.게.아. 롤페즈 | Reference voltage source with temperature-compensated output reference voltage |
| JP2002270768A (en) * | 2001-03-08 | 2002-09-20 | Nec Corp | Cmos reference voltage circuit |
| US6642699B1 (en) * | 2002-04-29 | 2003-11-04 | Ami Semiconductor, Inc. | Bandgap voltage reference using differential pairs to perform temperature curvature compensation |
| JP2008271503A (en) * | 2007-03-26 | 2008-11-06 | Matsushita Electric Ind Co Ltd | Reference current circuit |
| US8665005B2 (en) * | 2010-12-03 | 2014-03-04 | Marvell World Trade Ltd. | Process and temperature insensitive inverter |
| FR2975512B1 (en) * | 2011-05-17 | 2013-05-10 | St Microelectronics Rousset | METHOD AND DEVICE FOR GENERATING AN ADJUSTABLE REFERENCE VOLTAGE OF BAND PROHIBITED |
| CN103926966B (en) * | 2014-04-11 | 2015-07-08 | 安徽大学 | Low-voltage band-gap reference circuit |
| KR102124241B1 (en) * | 2016-08-16 | 2020-06-18 | 선전 구딕스 테크놀로지 컴퍼니, 리미티드 | Linear regulator |
| WO2019104467A1 (en) * | 2017-11-28 | 2019-06-06 | 深圳市汇顶科技股份有限公司 | Voltage regulator and power supply |
| US10359801B1 (en) * | 2018-05-29 | 2019-07-23 | Iowa State University Research Foundation, Inc. | Voltage reference generator with linear and non-linear temperature dependency elimination |
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