CN116209268A - Semiconductor Flash structure and preparation method thereof - Google Patents
Semiconductor Flash structure and preparation method thereof Download PDFInfo
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- CN116209268A CN116209268A CN202310488809.2A CN202310488809A CN116209268A CN 116209268 A CN116209268 A CN 116209268A CN 202310488809 A CN202310488809 A CN 202310488809A CN 116209268 A CN116209268 A CN 116209268A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 106
- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 86
- 238000000034 method Methods 0.000 claims abstract description 42
- 238000002955 isolation Methods 0.000 claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims abstract description 18
- 238000003860 storage Methods 0.000 claims abstract description 15
- 230000005641 tunneling Effects 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 86
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 20
- 239000011241 protective layer Substances 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 239000011229 interlayer Substances 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 125000006850 spacer group Chemical group 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 125000004437 phosphorous atom Chemical group 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- -1 i.e. Chemical compound 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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Abstract
The application relates to the technical field of semiconductors and discloses a semiconductor Flash structure and a preparation method thereof, wherein the semiconductor Flash structure comprises a semiconductor substrate and a cell storage area, and the cell storage area comprises a control gate group, a selection gate group, a P+ source area, a P+ drain area and an intermediate node area; the middle node region is positioned between the P+ source region and the P+ drain region, side walls of the control gate group and the selection gate group are respectively provided with a side wall isolation layer, the control gate group spans between the P+ source region and the middle node region, and the selection gate group spans between the middle node region and the P+ drain region; the control gate group comprises a tunneling dielectric layer, an N+ floating gate layer, an ONO dielectric layer and a P+ control gate which are sequentially stacked and deposited from bottom to top relative to the semiconductor substrate; the P+ source region, the P+ drain region and the P+ control grid are formed in the same P+ ion implantation doping procedure. The method simplifies the whole preparation process of the Flash device and improves the cost performance of the preparation of the Flash device.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor Flash structure and a preparation method thereof.
Background
In the semiconductor manufacturing process, embedded Flash (EMB Flash) is increasingly widely applied in MCUs (microcontroller units) and DSPs (DigitalSignal Process, digital signal processors), almost all MCUs and DSPs are provided with embedded Flash, the floating gate of the existing embedded Flash is generally doped with N type, the corresponding control gate is also doped with N type, in the forming process of the N type doped control gate, after the polysilicon layer is undoped and deposited, an additional mask layer process is required to be added for isolation so as to facilitate p+ ion implantation of a Source Line (SL) region and a Bit Line (BL) region, thus increasing the process complexity and the preparation cost for the overall preparation of Flash devices.
Disclosure of Invention
In view of this, the present application provides a semiconductor Flash structure and a preparation method thereof, so as to simplify the overall preparation process of the Flash device and improve the cost performance of the Flash device preparation.
To achieve the above object, according to a first aspect, the following technical solution is adopted:
a preparation method of a semiconductor Flash structure comprises the following steps:
providing a semiconductor substrate, and depositing a side wall isolation layer on the semiconductor substrate;
etching the side wall isolation layer to form a gate groove with a distance maintained, and exposing an undoped source region and an undoped drain region of the semiconductor substrate;
forming a control gate group and a selection gate group in the gate trench, wherein the control gate group comprises a tunneling dielectric layer, an N+ floating gate layer, an ONO dielectric layer and an undoped control gate which are sequentially stacked from bottom to top relative to the semiconductor substrate;
and simultaneously carrying out P+ ion implantation on the undoped source region, the undoped drain region and the undoped control grid electrode to form a P+ source region, a P+ drain region and a P+ control grid electrode respectively.
The application is further configured to: depositing silicon nitride on the semiconductor substrate to form a protective layer covering the control gate group, the selection gate group and the side wall isolation layer;
and depositing silicon oxide on the protective layer to form an interlayer dielectric layer covering the protective layer.
The application is further configured to: before the side wall isolation layer is deposited on the semiconductor substrate, the method further comprises the following steps: and P+ ion implantation is carried out on the semiconductor substrate to form an intermediate node region, and the intermediate node region is positioned between the undoped source region and the undoped drain region.
The application is further configured to: the semiconductor substrate comprises an N-type doped silicon substrate or an N-type well region formed in a P-type silicon substrate, and the doping concentrations of the P+ source region, the P+ drain region and the intermediate node region are higher than those of the semiconductor substrate.
The application is further configured to: the control gate group, the selection gate group, the P+ source region, the P+ drain region and the intermediate node region form a cell storage region on the semiconductor substrate.
According to a second aspect, the technical scheme adopted is as follows:
a semiconductor Flash structure, comprising:
the semiconductor device comprises a semiconductor substrate and a plurality of cell storage areas arranged on the semiconductor substrate, wherein each cell storage area comprises a control gate group, a selection gate group, a P+ source area, a P+ drain area and an intermediate node area;
the P+ source region, the P+ drain region and the intermediate node region are all arranged in the semiconductor substrate, the intermediate node region is positioned between the P+ source region and the P+ drain region, the control gate group and the selection gate group are arranged on the semiconductor substrate, side walls of the control gate group and the selection gate group are provided with side wall isolation layers, the control gate group spans between the P+ source region and the intermediate node region, and the selection gate group spans between the intermediate node region and the P+ drain region;
the control gate group comprises a tunneling dielectric layer, an N+ floating gate layer, an ONO dielectric layer and a P+ control gate which are sequentially stacked and deposited from bottom to top relative to the semiconductor substrate;
the P+ source region, the P+ drain region and the P+ control grid are formed in the same P+ ion implantation doping procedure.
The application is further configured to: the semiconductor device further comprises a protection layer and an interlayer dielectric layer, wherein the protection layer covers the control gate group, the selection gate group and the side wall isolation layer, and the interlayer dielectric layer is deposited on the protection layer.
The application is further configured to: the side wall isolation layer comprises silicon oxide and/or silicon nitride, the P+ control grid electrode comprises P-type polycrystalline silicon, the N+ floating gate layer comprises N-type polycrystalline silicon, the ONO dielectric layer comprises laminated silicon oxide, silicon nitride and silicon oxide, the protection layer comprises silicon nitride, and the interlayer dielectric layer comprises silicon oxide.
The application is further configured to: the semiconductor substrate comprises an N-type doped silicon substrate or an N-type well region formed in a P-type silicon substrate, and the doping concentrations of the P+ source region, the P+ drain region and the intermediate node region are higher than those of the semiconductor substrate.
The application is further configured to: and a distance is kept among the P+ source region, the P+ drain region and the intermediate node region.
In summary, compared with the prior art, the application discloses a semiconductor Flash structure and a preparation method thereof, wherein a cell storage area is arranged on a semiconductor substrate, the cell storage area comprises a control gate group, a select gate group, a P+ source region, a P+ drain region and an intermediate node region, the control gate group spans between the P+ source region and the intermediate node region, the select gate group spans between the intermediate node region and the P+ drain region, and the control gate group comprises a tunneling dielectric layer, an N+ floating gate layer, an ONO dielectric layer and a P+ control gate which are sequentially deposited from bottom to top relative to the semiconductor substrate, wherein the P+ source region, the P+ drain region and the P+ control gate are formed in the same P+ ion implantation doping procedure, that is, through the arrangement, the overall preparation process of the Flash device is simplified, and the cost performance of the Flash device is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following description will briefly explain the drawings needed in the description of the embodiments, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for manufacturing a semiconductor Flash structure of the present embodiment;
fig. 2 is a cross-sectional structural view of the semiconductor Flash structure of the present embodiment;
fig. 3 is a diagram showing a comparison of write/erase windows of a p+ control gate of a semiconductor Flash structure and an n+ control gate of a conventional Flash structure according to this embodiment.
Description of the drawings: 1. a semiconductor substrate; 2. a cell storage area; 3. a control gate group; 4. selecting a gate group; 5. a P+ source region; 6. a P+ drain region; 7. an intermediate node area; 8. a side wall isolation layer; 9. a protective layer; 10. an interlayer dielectric layer.
Detailed Description
As described in the background art, the floating gate of Flash in the prior art is generally N-doped, the corresponding control gate is also N-doped, and in the formation process of the N-doped control gate, after the undoped polysilicon layer is deposited, an additional mask layer process is required to be added for isolation so as to facilitate p+ ion implantation in the Source Line (SL) region and the Bit Line (BL) region, which increases the process complexity and the preparation cost for the overall preparation of the Flash device.
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element, and furthermore, elements having the same name in different embodiments of the present application may have the same meaning or may have different meanings, a particular meaning of which is to be determined by its interpretation in this particular embodiment or by further combining the context of this particular embodiment.
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
In the following description, suffixes such as "module", "component", or "unit" for representing elements are used only for facilitating the description of the present application, and are not of specific significance per se. Thus, "module," "component," or "unit" may be used in combination.
In the description of the present application, it should be noted that the positional or positional relationship indicated by the terms such as "upper", "lower", "left", "right", "inner", "outer", etc. are based on the positional or positional relationship shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The technical solutions shown in the present application will be described in detail by specific examples. The following description of the embodiments is not intended to limit the priority of the embodiments.
Referring to fig. 1 and 2, fig. 1 is a flowchart of a method for manufacturing a semiconductor Flash structure according to the present embodiment, and fig. 2 is a cross-sectional structure diagram of the semiconductor Flash structure according to the present embodiment, where the method for manufacturing the semiconductor Flash structure specifically includes:
s101, providing a semiconductor substrate, and depositing a side wall isolation layer on the semiconductor substrate.
In this step, the sidewall spacer may be formed by chemical vapor deposition, and the sidewall spacer may include silicon oxide and/or silicon nitride, i.e., silicon oxide and/or silicon nitride is deposited on the semiconductor substrate to form the sidewall spacer.
Further, the semiconductor substrate comprises an N-type doped silicon substrate or an N-type well region formed in a P-type silicon substrate so as to exert the electrical property of the Flash structure.
It should be noted that, the semiconductor substrate of this embodiment may be formed of monocrystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, or the like, and the semiconductor substrate may be a SiGe substrate, a group iii-v compound substrate, a silicon carbide substrate, or a stacked structure thereof, or a silicon-on-insulator structure, or may be a diamond substrate or another semiconductor material substrate known to those skilled in the art, for example, a semiconductor substrate in which P atoms may be implanted into monocrystalline silicon to form N-type conductivity, so as to improve the material selectivity and adaptability to the actual production environment.
And S102, etching the side wall isolation layer to form a gate groove with a kept distance, and exposing an undoped source region and an undoped drain region of the semiconductor substrate.
In this step, before etching the sidewall spacer, an etching pattern of the sidewall spacer may be formed by coating a photoresist layer on the semiconductor substrate, exposing and developing, so as to facilitate etching of the sidewall spacer, thereby exposing an undoped source region and an undoped drain region of the semiconductor substrate. And forming a gate trench with a distance maintained.
And S103, forming a control gate group and a selection gate group in the gate groove, wherein the control gate group comprises a tunneling dielectric layer, an N+ floating gate layer, an ONO dielectric layer and an undoped control gate which are sequentially stacked from bottom to top relative to the semiconductor substrate.
It will be appreciated that referring to fig. 2, the p+ source region and p+ drain region structures are undoped source region and undoped drain region before ion implantation, and the control gate group and the select gate group are both located in the gate trench formed by the sidewall spacers.
In this step, the n+ floating gate layer comprises N-type polysilicon and the ONO dielectric layer comprises a stack of silicon oxide-silicon nitride-silicon oxide.
S104, P+ ion implantation is carried out on the undoped source region, the undoped drain region and the undoped control grid electrode at the same time so as to form a P+ source region, a P+ drain region and a P+ control grid electrode respectively.
In the embodiment, the undoped source region, the undoped drain region and the undoped control gate are doped with P+ ions in the same ion implantation step, namely, the process steps of forming and removing an additional mask layer for the N+ control gate are saved, so that the overall preparation process of the Flash device is simplified, and the cost performance of the preparation of the Flash device is improved.
Before depositing the side wall isolation layer on the semiconductor substrate, p+ ion implantation can be performed on the semiconductor substrate to form an intermediate node region, the intermediate node region is located between the undoped source region and the undoped drain region, and doping concentrations of the p+ source region, the p+ drain region and the intermediate node region are higher than those of the semiconductor substrate so as to bring the electrical performance of the Flash structure into play.
Further, the control gate group, the select gate group, the p+ source region, the p+ drain region, and the intermediate node region constitute a cell storage region on the semiconductor substrate.
Specifically, the control gate group is a control gate transistor, the selection gate group is a selection gate transistor, the control gate group spans between the P+ source region and the middle node region, the selection gate group spans between the middle node region and the P+ drain region, namely, in the working process of the Flash device, the P+ source region is used as the source region of the control gate group, the P+ source region is connected with the source line SL, the P+ control gate is connected with the control gate line CG, the middle node region is used as the drain region of the control gate group and the source region of the selection gate group, the P+ drain region is used as the drain region of the selection gate group, the P+ drain region is connected with the bit line BL, and the selection gate is connected with the selection gate line SG in series, so that the actual function of the Flash structure can be conveniently exerted.
In some embodiments, after forming the p+ source region, the p+ drain region, and the p+ control gate, silicon nitride is deposited on the semiconductor substrate to form a protective layer covering the control gate group, the select gate group, and the sidewall spacers, and silicon oxide is deposited on the protective layer to form an interlayer dielectric layer covering the protective layer to facilitate device protection and device packaging for subsequent processes.
Referring to fig. 3, a comparison diagram of write/erase window of a p+ control gate of the semiconductor Flash structure and an n+ control gate of the existing Flash structure is shown, wherein a control gate group having the p+ control gate is regarded as a P-type control gate, vcg represents a control gate voltage, and compared with an N-type control gate of the existing n+ control gate, on the basis of the same control gate voltage, an erase and write access curve of the semiconductor Flash structure almost coincides, that is, after the control gate is improved, device performance of the semiconductor Flash structure of the embodiment remains unchanged, so that on the premise of ensuring the performance of the Flash device, an overall preparation process of the Flash device is simplified, and cost performance of Flash device preparation is improved.
Based on the above method for manufacturing a semiconductor Flash structure, this embodiment also discloses a semiconductor Flash structure, and referring to fig. 2, the semiconductor Flash structure specifically includes:
a semiconductor substrate 1, and a plurality of cell storage areas 2 arranged on the semiconductor substrate 1, wherein the cell storage areas 2 comprise a control gate group 3, a selection gate group 4, a P+ source area 5, a P+ drain area 6 and an intermediate node area 7; the P+ source region 5, the P+ drain region 6 and the intermediate node region 7 are all arranged in the semiconductor substrate 1, the intermediate node region 7 is positioned between the P+ source region 5 and the P+ drain region 6, the control gate group 3 and the selection gate group 4 are arranged on the semiconductor substrate 1, side edges of the control gate group 3 and the selection gate group 4 are both provided with side wall isolation layers 8, the control gate group 3 spans between the P+ source region 5 and the intermediate node region 7, and the selection gate group 4 spans between the intermediate node region 7 and the P+ drain region 6.
In a specific implementation process, the control gate group 3 comprises a tunneling dielectric layer 31, an n+ floating gate layer 32, an ONO dielectric layer 33 and a p+ control gate 34 which are sequentially deposited from bottom to top relative to the semiconductor substrate 1, specifically, in a working process of the Flash device, a distance is kept between a p+ source region 5, a p+ drain region 6 and an intermediate node region 7, the p+ source region 5 is used as a source region of the control gate group, the p+ source region 5 is connected with a source line SL, the p+ control gate 34 is connected with a control gate line CG, the intermediate node region 7 is simultaneously used as a drain region of the control gate group 3 and a source region of the selection gate group 4, the p+ drain region 6 is used as a drain region of the selection gate group 4, the p+ drain region 6 is connected with a bit line BL, and the selection gate group 4 is connected with the selection gate line SG, so that the control gate group and the selection gate group are connected in series so as to conveniently exert a practical function of the Flash structure.
Furthermore, the p+ source region 5, the p+ drain region 6 and the p+ control gate 34 are formed in the same p+ ion implantation doping procedure, that is, the process steps of forming and removing an additional mask layer for the existing Flash structure n+ control gate are saved, so that the overall preparation process of the Flash device is simplified, and the cost performance of the Flash device preparation is improved.
In this embodiment, the semiconductor substrate 1 includes an N-type doped silicon substrate, or an N-type well region formed in a P-type silicon substrate, so as to improve the selectivity of Flash structure formation and to improve the cost performance of the product.
In some embodiments, the semiconductor substrate 1 may be formed of polysilicon, amorphous silicon or doped silicon, or may be a SiGe substrate, a iii-v element compound substrate, a silicon carbide substrate or a stacked structure thereof, or a silicon-on-insulator structure, or may be a diamond substrate or other semiconductor material substrate known to those skilled in the art, for example, a P-atom implanted semiconductor substrate to form N-type conductivity in monocrystalline silicon, so as to improve the selectivity of the material and the adaptability to the actual production environment.
In some embodiments, the Flash structure further includes a protective layer 9 and an interlayer dielectric layer 10, where the protective layer 9 covers the control gate set 3, the select gate set 4, and the sidewall spacer 8, and the interlayer dielectric layer 10 is deposited on the protective layer 9 to facilitate device protection and device packaging in subsequent processes.
Further, the protective layer 9 comprises silicon nitride, and the interlayer dielectric layer 10 comprises silicon oxide, i.e. silicon nitride is deposited by chemical vapor deposition to form the protective layer 9, and silicon oxide is deposited to form the interlayer dielectric layer 10, wherein the interlayer dielectric layer 10 may further comprise a suitable insulating layer of other materials.
In this embodiment, the p+ control gate 34 includes P-type polysilicon, the n+ floating gate layer 32 includes N-type polysilicon, that is, by the P-type polysilicon design of the p+ control gate 34, it is ensured that in the ion implantation process for the p+ source region 5 and the p+ drain region 6, the p+ source region 5, the p+ drain region 6 and the p+ control gate 34 can be formed in the same p+ ion implantation doping process.
In some embodiments, the spacer 8 comprises silicon oxide and/or silicon nitride, the ONO dielectric layer 33 comprises stacked silicon oxide, silicon nitride and silicon oxide, or the ONO dielectric layer 33 comprises stacked upper silicon oxide layer, middle silicon nitride layer and lower silicon oxide layer, wherein the doping concentrations of the p+ source region 5, the p+ drain region 6 and the middle node region 7 are higher than the doping concentration of the semiconductor substrate 1 so as to exert the electrical performance of the Flash structure.
It is understood that the select gate set 4 of this embodiment may include the tunneling dielectric layer 31, the n+ floating gate layer 32, the ONO dielectric layer 33 and the select gate, where in the structural arrangement, the select gate set 4 may be arranged the same as the control gate set 3, and the tunneling dielectric layer 31, the n+ floating gate layer 32, the ONO dielectric layer 33 and the select gate may be deposited by stacking from bottom to top, or the tunneling dielectric layer 31, the select gate, the ONO dielectric layer 33 and the n+ floating gate layer 32 may be deposited by stacking from bottom to top, and when the structural arrangement of the select gate set 4 and the control gate set 3 is the same, it may be prepared synchronously with the control gate set 3 in the foregoing semiconductor Flash structure preparation method.
In summary, in the semiconductor Flash structure of the embodiment, the cell storage area 2 includes the control gate group 3, the select gate group 4, the p+ source region 5, the p+ drain region 6 and the intermediate node region 7, the intermediate node region 7 is located between the p+ source region 5 and the p+ drain region 6, the side edges of the control gate group 3 and the select gate group 4 are both provided with the sidewall spacer layer 8, the control gate group 3 spans between the p+ source region 5 and the intermediate node region 7, the select gate group 4 spans between the intermediate node region 7 and the p+ drain region 6, wherein the p+ source region 5, the p+ drain region 6 and the p+ control gate 34 are formed in the same p+ ion implantation doping procedure, that is, the process steps of forming and removing an additional mask layer for the n+ control gate of the existing Flash structure are saved, so that the overall manufacturing process of the Flash device is simplified, and the cost performance of manufacturing the Flash device is improved.
The foregoing has outlined rather broadly the more detailed description of the present application, wherein specific examples have been provided to illustrate the principles and embodiments of the present application, the description of the examples being provided solely to assist in the understanding of the core concepts of the present application; meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. The preparation method of the semiconductor Flash structure is characterized by comprising the following steps:
providing a semiconductor substrate, and depositing a side wall isolation layer on the semiconductor substrate;
etching the side wall isolation layer to form a gate groove with a distance maintained, and exposing an undoped source region and an undoped drain region of the semiconductor substrate;
forming a control gate group and a selection gate group in the gate trench, wherein the control gate group comprises a tunneling dielectric layer, an N+ floating gate layer, an ONO dielectric layer and an undoped control gate which are sequentially stacked from bottom to top relative to the semiconductor substrate;
and simultaneously carrying out P+ ion implantation on the undoped source region, the undoped drain region and the undoped control grid electrode to form a P+ source region, a P+ drain region and a P+ control grid electrode respectively.
2. The method for manufacturing the semiconductor Flash structure according to claim 1, further comprising:
depositing silicon nitride on the semiconductor substrate to form a protective layer covering the control gate group, the selection gate group and the side wall isolation layer;
and depositing silicon oxide on the protective layer to form an interlayer dielectric layer covering the protective layer.
3. The method for preparing a semiconductor Flash structure according to claim 1, wherein before depositing the sidewall spacer on the semiconductor substrate, the method further comprises:
and P+ ion implantation is carried out on the semiconductor substrate to form an intermediate node region, and the intermediate node region is positioned between the undoped source region and the undoped drain region.
4. The method for manufacturing the semiconductor Flash structure according to claim 3, wherein the semiconductor substrate comprises an N-type doped silicon substrate or an N-type well region formed in a P-type silicon substrate, and doping concentrations of the p+ source region, the p+ drain region and the intermediate node region are higher than those of the semiconductor substrate.
5. The method for manufacturing a semiconductor Flash structure according to claim 3, wherein said control gate group, said select gate group, said p+ source region, said p+ drain region, and said intermediate node region constitute a cell storage region on said semiconductor substrate.
6. A semiconductor Flash structure made by the method for manufacturing a semiconductor Flash structure according to any one of claims 1 to 5, comprising:
the semiconductor device comprises a semiconductor substrate and a plurality of cell storage areas arranged on the semiconductor substrate, wherein each cell storage area comprises a control gate group, a selection gate group, a P+ source area, a P+ drain area and an intermediate node area;
the P+ source region, the P+ drain region and the intermediate node region are all arranged in the semiconductor substrate, the intermediate node region is positioned between the P+ source region and the P+ drain region, the control gate group and the selection gate group are arranged on the semiconductor substrate, side walls of the control gate group and the selection gate group are provided with side wall isolation layers, the control gate group spans between the P+ source region and the intermediate node region, and the selection gate group spans between the intermediate node region and the P+ drain region;
the control gate group comprises a tunneling dielectric layer, an N+ floating gate layer, an ONO dielectric layer and a P+ control gate which are sequentially stacked and deposited from bottom to top relative to the semiconductor substrate;
the P+ source region, the P+ drain region and the P+ control grid are formed in the same P+ ion implantation doping procedure.
7. The semiconductor Flash structure of claim 6, further comprising a protective layer covering said control gate set, said select gate set, and said sidewall spacer, and an interlayer dielectric layer deposited on said protective layer.
8. The semiconductor Flash structure of claim 7, wherein the sidewall spacer comprises silicon oxide and/or silicon nitride, the p+ control gate comprises P-type polysilicon, the n+ floating gate layer comprises N-type polysilicon, the ONO dielectric layer comprises a stack of silicon oxide, silicon nitride and silicon oxide, the protective layer comprises silicon nitride, and the interlayer dielectric layer comprises silicon oxide.
9. The semiconductor Flash structure of claim 6, wherein the semiconductor substrate comprises an N-doped silicon substrate or an N-well region formed in a P-type silicon substrate, the p+ source region, the p+ drain region, and the intermediate node region each having a doping concentration that is higher than a doping concentration of the semiconductor substrate.
10. The semiconductor Flash structure of claim 6, wherein a distance is maintained between said p+ source region, said p+ drain region, and said intermediate node region.
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| CN202310488809.2A CN116209268A (en) | 2023-05-04 | 2023-05-04 | Semiconductor Flash structure and preparation method thereof |
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| CN202310488809.2A CN116209268A (en) | 2023-05-04 | 2023-05-04 | Semiconductor Flash structure and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113113415A (en) * | 2021-03-31 | 2021-07-13 | 华虹半导体(无锡)有限公司 | Floating gate type split gate flash memory device structure and manufacturing process thereof |
| CN114709216A (en) * | 2022-06-06 | 2022-07-05 | 广州粤芯半导体技术有限公司 | pFlash structure and preparation method thereof |
| CN114758955A (en) * | 2022-06-13 | 2022-07-15 | 广州粤芯半导体技术有限公司 | Flash memory structure and manufacturing method thereof |
| CN114883335A (en) * | 2022-07-11 | 2022-08-09 | 广州粤芯半导体技术有限公司 | Flash memory and layout structure thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113113415A (en) * | 2021-03-31 | 2021-07-13 | 华虹半导体(无锡)有限公司 | Floating gate type split gate flash memory device structure and manufacturing process thereof |
| CN114709216A (en) * | 2022-06-06 | 2022-07-05 | 广州粤芯半导体技术有限公司 | pFlash structure and preparation method thereof |
| CN114758955A (en) * | 2022-06-13 | 2022-07-15 | 广州粤芯半导体技术有限公司 | Flash memory structure and manufacturing method thereof |
| CN114883335A (en) * | 2022-07-11 | 2022-08-09 | 广州粤芯半导体技术有限公司 | Flash memory and layout structure thereof |
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