CN115295610A - NORD Flash device and manufacturing method thereof - Google Patents

NORD Flash device and manufacturing method thereof Download PDF

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Publication number
CN115295610A
CN115295610A CN202211060266.6A CN202211060266A CN115295610A CN 115295610 A CN115295610 A CN 115295610A CN 202211060266 A CN202211060266 A CN 202211060266A CN 115295610 A CN115295610 A CN 115295610A
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word line
silicon
layer
dielectric layer
forming
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王进峰
张剑
金宏峰
王辉
陈华伦
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate

Abstract

The application provides a NORD Flash device and a manufacturing method thereof, wherein the NORD Flash device at least comprises the following components: a silicon-on-insulator substrate; an isolation feature disposed in the silicon-on-insulator substrate; a back gate region disposed below the insulator layer in the silicon-on-insulator substrate inside the isolation feature; NORD Flash unit cell set on the silicon substrate of the insulator; a body pull-out region disposed in the silicon-on-insulator substrate, the isolation feature forming an insulating barrier between the body pull-out region and the NORD Flash cell. The control effect of the back grid region on the channel region of the NORD Flash device is improved by changing the applied voltage of the body leading-out region, and the degree of freedom of controlling the channel region can be increased.

Description

NORD Flash device and manufacturing method thereof
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a NORD Flash device and a manufacturing method thereof.
Background
Flash devices have the advantages of high density, low price, electrical programmability, erasability, and the like, and are widely used in nonvolatile memory devices. The floating gate type flash memory has a stacked gate structure including a floating gate and a control gate coupled to control storage and release of electrons in the floating gate.
For NORD Flash devices, short channel effects are evident as the device channel length is shortened. In order to solve the problems caused by short channel effects such as high leakage and the like, a complex ion implantation process is required to adjust the threshold voltage of a channel so as to improve the electrical performance.
The manufacturing process of the NORD Flash device requires a large number of annealing processes, inevitably resulting in diffusion of implanted ions, thereby making it difficult to precisely control the ion implantation effect. And a large number of ion implantation processes may affect junction breakdown voltage, thereby causing a serious crosstalk problem.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present application is to provide a NORD Flash device and a method for manufacturing the same, which are used to solve the problems of poor short channel effect and junction breakdown voltage influence caused by a complex ion implantation process in the prior art.
To achieve the above objects and other related objects, the present application provides a NORD Flash device and a method for fabricating the same. The technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a NORD Flash device, including:
a silicon-on-insulator substrate;
an isolation feature disposed in the silicon-on-insulator substrate;
a back gate region disposed below the insulator layer in the silicon-on-insulator substrate inside the isolation feature;
NORD Flash unit cell set on the silicon substrate of the insulator;
a body pull-out region in the silicon-on-insulator substrate disposed outside the isolation feature, the isolation feature constituting an insulating barrier between the body pull-out region and the NORD Flash cell.
Preferably, the NORD Flash cell comprises a first laminated structure and a second laminated structure which are formed by laminating a gate dielectric layer, a floating gate, an inter-electrode dielectric layer, a control gate and a word line side wall from bottom to top, and word line polysilicon which is arranged on the gate dielectric layer and the bottom of which is positioned between the first laminated structure and the second laminated structure.
Preferably, a tunneling oxide layer is arranged between the word line polysilicon and the first and second stacked structures.
Preferably, a first dielectric layer and a second dielectric layer are arranged on the outer side of the tunneling oxide layer.
Preferably, the NORD Flash device further comprises a grid side wall, a light-doped source drain region and a heavy-doped source drain region.
In a second aspect, an embodiment of the present application provides a method for manufacturing an NORD Flash device, including:
providing a silicon-on-insulator substrate, and forming an isolation component in the silicon-on-insulator substrate;
performing an ion implantation to form a back gate region below the insulator layer in the silicon-on-insulator substrate inside the isolation feature;
forming NORD Flash unit cells on a silicon substrate on an insulator;
a body extraction region is formed in the silicon-on-insulator substrate outside the isolation feature, and the isolation feature forms an insulating barrier between the body extraction region and the NORD Flash cell.
Preferably, the ion implantation is a P-type ion implantation.
Preferably, the body leading-out region includes:
forming a mask layer on the silicon-on-insulator substrate, and forming an ion implantation window in the mask layer;
performing another ion implantation to form a body extraction region in the SOI substrate;
and removing the mask layer.
Preferably, the ion type of the another ion implantation is p type.
Preferably, before the formation of the body extraction region, the method further comprises:
performing first ion implantation in the silicon substrate on the insulator to form a lightly doped source drain region;
forming a grid side wall;
and performing second ion implantation in the silicon substrate on the insulator by taking the NORD Flash cell and the grid side wall as masks to form a heavily doped source-drain region.
Preferably, the ion type of the first ion implantation and the second ion implantation is n-type.
Preferably, before forming the lightly doped source and drain regions, a step of forming a gate masking layer on the top and the side wall of the NORD Flash cell is further included.
Preferably, after the heavily doped source/drain region is formed, a rapid annealing step is further included to activate ions in the lightly doped source/drain region and the heavily doped source/drain region.
Preferably, the NORD Flash cell is formed, including:
forming a gate dielectric layer on the upper surface of the silicon-on-insulator substrate;
forming a floating gate polysilicon layer, an interelectrode dielectric layer and a control gate polysilicon layer on the gate dielectric layer in sequence;
defining a word line window, and forming a word line side wall in the word line window;
sequentially forming a first dielectric layer, a second dielectric layer, a tunneling oxide layer and word line polysilicon in a region corresponding to the word line window;
and removing the control gate polysilicon layer, the interelectrode dielectric layer, the floating gate polysilicon layer and the gate dielectric layer which are positioned at the outer side of the word line side wall.
Preferably, defining a word line window and forming a word line sidewall in the word line window includes:
depositing a hard mask layer on the control gate polysilicon layer;
forming a word line window in the hard mask layer through photoetching and etching processes;
and depositing an oxidation layer and carrying out back etching to form word line side walls in the word line windows.
Preferably, the forming of the first dielectric layer, the second dielectric layer, the tunneling oxide layer and the word line polysilicon in the region corresponding to the word line window in sequence includes:
removing the control gate polysilicon layer, the inter-electrode dielectric layer and the floating gate polysilicon layer which are not covered by the word line side wall in the region corresponding to the word line window;
sequentially forming a first dielectric layer, a second dielectric layer and a tunneling oxide layer in a region corresponding to the word line window;
and depositing polycrystalline silicon, carrying out chemical mechanical polishing, and forming word line polycrystalline silicon in the area corresponding to the word line window.
As described above, the NORD Flash device and the manufacturing method thereof provided by the present application have the following beneficial effects: the method is characterized in that a back gate region is formed on the basis of a silicon-on-insulator substrate by performing P-type ion implantation, the control effect of the back gate region on the working channel of the NORD Flash device is improved by changing the voltage of a body leading-out region, and the degree of freedom of channel control can be increased.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts.
FIG. 1 is a schematic cross-sectional view of a NORD Flash device provided in the prior art;
FIG. 2 is a schematic cross-sectional view of a NORD Flash device provided in an embodiment of the present application;
FIG. 3 is a flow chart illustrating a method for manufacturing a NORD Flash device according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram illustrating a structure of a device formed after step 301 is completed in a method for manufacturing a NORD Flash device according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram illustrating a structure of a device formed after step 302 is completed in a method for manufacturing a NORD Flash device according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram illustrating a structure of a device formed after step 303 is completed in a method for manufacturing a NORD Flash device according to an embodiment of the present disclosure.
Detailed Description
The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. The present application is capable of other and different embodiments and its several details are capable of modifications and variations in various respects, all without departing from the spirit of the present invention.
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships, and are only used for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be connected through the inside of the two elements, or may be connected wirelessly or through a wire. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a schematic cross-sectional structure diagram of a NORD Flash device provided in the prior art is shown.
As shown in fig. 1, the NORD Flash device includes at least a substrate 100, a word line polysilicon 110, a floating gate, and a control gate 120. A gate dielectric layer 130 is formed on the substrate 100, and a first floating gate 140 and a second floating gate 150 are disposed on the gate dielectric layer 130. An inter-electrode dielectric layer 160, a control gate 120 and word line spacers 170 are sequentially disposed above the first floating gate 140 and the second floating gate 150.
The word line polysilicon 110 is disposed on the gate dielectric layer 130 with its bottom between the first floating gate 140 and the second floating gate 150. A tunnel oxide layer 180 is disposed between the word line polysilicon 110 and the floating gate, the inter-electrode dielectric layer 160, the control gate 120, and the word line sidewall 170.
A first dielectric layer 190 and a second dielectric layer 191 are disposed outside the tunnel oxide layer 180. The inner sides of the bottom of the word line spacers 170, the inner sides of the control gates 120, and the inner sides of the inter-electrode dielectric layers 160 are covered by a first dielectric layer 190, and the inner sides of the first dielectric layer 190 and the word line spacers 170 are covered by a second dielectric layer 191.
Optionally, the inter-electrode dielectric layer 160 is formed by stacking an oxide layer 1603, a silicon nitride layer 1602 and an oxide layer 1601. Optionally, the word line sidewall spacers 170 are oxide layers, the first dielectric layer 190 is an oxide layer, and the second dielectric layer 191 is a silicon nitride layer.
The NORD Flash device further comprises a gate sidewall spacer 101, a lightly doped source drain region 102, a halo region 103 and a heavily doped source drain region 104. After the gate mask layer 105 is disposed, a first ion implantation is performed on the substrate 100 to form lightly doped source/drain regions 102. Next, a second ion implantation is performed on the substrate 100 to form a halo region 103.
The halo region 103 serves to limit the diffusion of ions from the lightly doped source/drain region 102, so that the lightly doped source/drain region 102 is formed to be shallow. And performing complex ion implantation in the halo region 103, wherein the complex ion implantation enters defects generated by ion implantation in the substrate 100, and prevents ions in the lightly doped source/drain region 102 and the halo region 103 from diffusing into the defects, so that the halo region 103 and the lightly doped source/drain region 102 are shallower, thereby reducing the overlap capacitance of the device, and simultaneously adjusting the threshold voltage of a channel and improving the short channel effect.
After the gate spacers 101 are disposed, a third ion implantation is performed on the substrate 100 to form a heavily doped source/drain region 104.
After the lightly doped source drain region 102 and the halo region 103 are formed, a rapid annealing process is performed to activate ions in the lightly doped source drain region 102 and the halo region 103. After the heavily doped source/drain regions 104 are formed, a rapid annealing process is performed again to activate ions in the heavily doped source/drain regions 104.
The large-scale annealing process implemented above inevitably causes diffusion of implanted ions, which makes precise control of the ion implantation effect difficult. And a large number of ion implantation processes may affect junction breakdown voltage, thereby causing a serious crosstalk problem.
To solve the above problems in the prior art, please refer to fig. 2, which is a schematic cross-sectional structure diagram of a NORD Flash device provided in the present application.
As shown in fig. 2, the NORD Flash device includes a silicon-on-insulator (SOI) substrate 200, isolation features 202, NORD Flash cells 20, a back gate region 205, and a body pull-out region 206.
The NORD Flash cell 20 includes a first stacked structure 240 and a second stacked structure 241 formed by stacking a gate dielectric layer 230, a floating gate 250, an inter-electrode dielectric layer 260, a control gate 220, and word line spacers 270 from bottom to top, and a word line polysilicon 210 disposed on the gate dielectric layer 230 and having a bottom located between the first stacked structure 240 and the second stacked structure 241.
The gate dielectric layer 230 is disposed on the soi substrate 200, and a tunnel oxide layer 280 is disposed between the word line polysilicon 210 and the first and second stacked structures 240 and 241.
A first dielectric layer 290 and a second dielectric layer 291 are disposed on the outer side of the tunnel oxide layer 280. The inner sides of the bottom of the word line sidewall spacers 270, the inner sides of the control gates 220, and the inner sides of the inter-electrode dielectric layers 260 are all covered by the first dielectric layer 290, and the inner sides of the first dielectric layer 290 and the word line sidewall spacers 270 are covered by the second dielectric layer 291.
Optionally, the inter-electrode dielectric layer 260 is formed by stacking an oxide layer 2603, a silicon nitride layer 2602, and an oxide layer 2601. Optionally, the word line sidewall spacers 270 are oxide layers, the first dielectric layer 290 is an oxide layer, and the second dielectric layer 291 is a silicon nitride layer.
The NORD Flash device further comprises a gate sidewall spacer 201, a lightly doped source drain region 203 and a heavily doped source drain region 204. Optionally, the top and sidewalls of NORD Flash cell 20 are provided with a gate masking layer 231.
The back gate region 205 is disposed below the insulator layer 2001 in the silicon-on-insulator substrate 200 inside the spacer members 202, the insulator layer 2001 acting as the gate dielectric layer for the back gate region. In the embodiment of the present application, P-type ion implantation is performed to form a P-type ion implanted region below the insulator layer 2001 in the silicon-on-insulator substrate 200 inside the spacer members 202, constituting the back gate region 205.
The body pull-out region 206 is disposed in the silicon-on-insulator substrate 200 outside the isolation feature 202, the isolation feature 202 constituting an insulating barrier between the body pull-out region 206 and the NORD Flash cell 20. The control effect of the back gate region on the channel region of the NORD Flash device is improved by changing the applied voltage to the body pull-out region 206, and the degree of freedom of the control on the channel region can be increased.
Referring to fig. 3, a flowchart of a method for manufacturing a NORD Flash device according to an embodiment of the present application is shown, where the method includes the following steps:
in step 301, a silicon-on-insulator substrate is provided, and isolation features are formed in the silicon-on-insulator substrate.
As shown in FIG. 4, a silicon-on-insulator substrate 200 is provided, and the insulator layer 2001 in the silicon-on-insulator substrate 200 may be comprised of one or more oxide compounds, and any other now known or later developed electrically insulating material, such as silicon dioxide (SiO) 2 )。
Isolation features 202 are formed in a silicon-on-insulator substrate 200. In the present embodiment, the Isolation feature 202 is formed by a Shallow Trench Isolation (STI) process, which includes, but is not limited to, shallow Trench etching, oxide filling, and oxide planarization.
The shallow trench etching includes, but is not limited to, isolation oxide layer, nitride deposition, shallow trench isolation using a mask, and STI shallow trench etching. Wherein the STI oxide fill includes, but is not limited to, trench liner silicon oxide, trench CVD (chemical vapor deposition) oxide fill, or PVD (physical vapor deposition) oxide fill. Wherein the planarization of the silicon wafer surface can be achieved by a variety of methods. The planarization of the wafer can be achieved by filling the gap with SOG (spin-on-glass) which can be composed of 80% solvent and 20% silicon dioxide, baking the SOG after deposition, evaporating the solvent to leave the silicon dioxide in the gap, or etching back the entire surface to reduce the thickness of the entire wafer. Planarization processes, including but not limited to polishing of trench oxide (chemical mechanical polishing may be used) and nitride removal, may also be effectively performed by CMP processes (also referred to as chemical mechanical polishing processes).
The isolation feature 202 may be formed of, for example, silicon dioxide (SiO) 2 ) Any insulating material, or a "high-k" dielectric having a high dielectric constant, which may be higher than 3.9, for example. In some cases, the isolation feature 202 may be comprised of an oxide material. Suitable materials for forming the isolation feature 202 may include, for example, silicon dioxide (SiO) 2 ) Hafnium oxide (HfO) 2 ) Alumina (Al) 2 O 3 ) Yttrium oxide (Y) 2 O 3 ) Tantalum oxide (Ta) 2 O 5 ) Titanium dioxide (TiO) 2 ) Praseodymium oxide (Pr) 2 O 3 ) Zirconium oxide (ZrO) 2 ) Erbium oxide (ErOx), and other materials with similar properties now known or later developed.
In step 302, an ion implantation is performed to form back gate regions under the insulator layer in the silicon-on-insulator substrate inside the isolation features.
As shown in fig. 5, a P-type ion implantation is performed to form a back gate region 205 below the insulator layer 2001 in the silicon-on-insulator substrate 200 inside the spacer members 202. Optionally, the P-type ions are boron ions or indium ions. The insulator layer 2001 in the silicon-on-insulator substrate 200 forms the gate dielectric of the back gate region 205, which isolates the back gate region 205 from the channel region of the subsequently formed NORD Flash device.
In step 303, NORD Flash cells are formed on the silicon-on-insulator substrate.
As shown in fig. 6, the NORD Flash cell 20 is formed on a silicon-on-insulator substrate 200 by a self-aligned process. The NORD Flash cell 20 includes a first stacked structure 240 and a second stacked structure 241, which are formed by stacking a gate dielectric layer 230, a floating gate 250, an inter-electrode dielectric layer 260, a control gate 220, and word line spacers 270 from bottom to top, and a word line polysilicon 210 disposed on the gate dielectric layer 230 and having a bottom located between the first stacked structure 240 and the second stacked structure 241.
The method for manufacturing the NORD Flash unit cell 20 comprises the following steps:
in a first step, a gate dielectric layer 230 is formed on the upper surface of the soi substrate 200. The gate dielectric layer 230 is made of silicon dioxide, hafnium oxide, aluminum oxide, high-K dielectric material or silicon oxynitride, the forming process is a deposition process, preferably a chemical vapor deposition method, and when the gate dielectric layer 230 is made of silicon dioxide, the forming process can also be thermal furnace oxidation or rapid thermal oxidation, and the silicon dioxide is nitrided to form a silicon oxynitride layer.
In the second step, a floating gate polysilicon layer, an inter-electrode dielectric layer 260 and a control gate polysilicon layer are sequentially formed on the gate dielectric layer 230 by a deposition process, preferably a chemical vapor deposition method. Optionally, the inter-electrode dielectric layer 260 is formed by stacking an oxide layer 2603, a silicon nitride layer 2602, and an oxide layer 2601.
A third step of defining a word line window and forming a word line sidewall spacer 270 in the word line window, which may be implemented as follows:
depositing a hard mask layer, such as a silicon nitride layer, on the control gate polysilicon layer;
forming a word line window in the hard mask layer by photolithography and etching processes, including: coating photoresist on the surface of the hard mask layer, carrying out exposure and development through a mask plate with word line window patterns, copying the word line window patterns into the photoresist layer, etching the hard mask layer by taking the photoresist as a mask, and forming word line windows in the hard mask layer;
an oxide layer is deposited and etched back to form word line spacers 270 in the word line windows.
A fourth step of sequentially forming a first dielectric layer 290, a second dielectric layer 291, a tunnel oxide layer 280 and word line polysilicon 210 in a region corresponding to the word line window, which can be implemented as follows:
removing the control gate polysilicon layer, the inter-electrode dielectric layer 260 and the floating gate polysilicon layer which are not covered by the word line side wall in the region corresponding to the word line window;
sequentially forming a first dielectric layer 290, a second dielectric layer 291 and a tunneling oxide layer 280 in a region corresponding to the word line window;
polysilicon is deposited and chemical mechanical polishing is performed to form word line polysilicon 210 in the region corresponding to the word line window.
Optionally, the first dielectric layer 290 is an oxide layer, and the second dielectric layer 291 is a silicon nitride layer.
The fifth step, removing the control gate polysilicon layer, the inter-electrode dielectric layer 260, the floating gate polysilicon layer and the gate dielectric layer 230 which are located outside the word line sidewall 270, includes: the word line polysilicon 210 is protected by a photolithography process, the remaining hard mask layer above the control gate polysilicon layer is removed, the control gate polysilicon layer, the inter-electrode dielectric layer 260, the floating gate polysilicon layer, and the gate dielectric layer 230, which are not covered by the word line sidewall 270, are sequentially removed, and the Photoresist (PR) on the top of the word line polysilicon 210 is removed.
In step 304, a body extraction region is formed in the silicon-on-insulator substrate outside the isolation feature.
As shown in fig. 2, first, a gate hard mask layer 231 is optionally formed on the top and sidewalls of the NORD Flash cell 20 by a deposition process, preferably chemical vapor deposition.
Next, a first ion implantation is performed in the soi substrate 200 using the gate hard mask layer 231 as a mask, thereby forming lightly doped source and drain regions 203.
The ion type of the first ion implantation is n type and is phosphorus ion or arsenic ion; optionally, when the ions implanted by the first ion implantation are phosphorus ions, the ion implantation energy range is 1 to 20keV, and the ion implantation dosage is 1E14 to 1E15atoms/cm 2 (ii) a Optionally, when the first ion implantation is arsenic ion, the ion implantation energy range is 2-35 KeV, and the ion implantation dose is 1E 14-1E 15atoms/cm 2 。
Next, a gate sidewall 201 is formed outside the gate hard mask layer 231. The forming process of the gate sidewall 201 is as follows: a dielectric layer is formed on the gate masking layer 231 and the upper surface of the soi substrate 200 by a chemical vapor deposition method or a physical vapor deposition method, and a gate sidewall 201 is formed by an etch-back process.
Then, a second ion implantation is performed in the soi substrate 200 using the NORD Flash cell 20 and the gate sidewall 201 as masks to form a heavily doped source/drain region 204.
The second ion implantation is of n-type and includes phosphorus ion or arsenic ion, and the second ion implantation may be one ion implantation step, multiple phosphorus ion implantation or multiple arsenic ion implantation, or multiple phosphorus ion and arsenic ion implantation combined.
And performing rapid annealing to activate ions in the lightly doped source drain region 203 and the heavily doped source drain region 204 and eliminate defects generated during ion implantation. Optionally, the rapid annealing process is: annealing at 900-1000 deg.c for 10-20 sec in inert gas environment.
Finally, a body pull-out region 206 is formed in the silicon-on-insulator substrate 200 outside the isolation feature 202, the isolation feature 202 constituting an insulating barrier between the body pull-out region 206 and the NORD Flash cell 20.
The formation process of the body pull-out region 206 is: forming a mask layer on the soi substrate 200, forming an ion implantation window in the mask layer by using photolithography and etching processes, performing another ion implantation, forming a body extraction region 206 in the soi substrate 200, and removing the mask layer by using an etching process.
The ion type of the other ion implantation is p type. Optionally, the p-type ions are boron ions or indium ions.
The back gate region 205 may be electrically coupled to the back gate node through body pull-out regions 206 to further affect the characteristics of NORD Flash. Applying a voltage to the body pull-out region 206 at the back gate node may induce a charge within the back gate region, thereby establishing a potential difference across the insulator layer 2001 between the back gate region 205 and the source/drain regions, channel regions, comprised of the activated heavily doped source/drain regions 204. By changing the potential difference, the control effect of the back gate region 205 on the channel region can be improved, and the degree of freedom of control over the channel region can be increased. Meanwhile, the process step of forming the halo region by carrying out ion implantation on the substrate in the prior art can be omitted, and the problems of poor control of short channel effect and influence on junction breakdown voltage caused by complex ion implantation are avoided.
In summary, the present application effectively overcomes various disadvantages of the prior art and has a high industrial utility value.
It should be noted that the drawings provided in this embodiment are only for schematically illustrating the basic idea of the present application, and the components related to the present invention are only shown in the drawings and not drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may be more complicated.
The above embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the present application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present application.

Claims (16)

1. A NORD Flash device, wherein the NORD Flash device comprises:
a silicon-on-insulator substrate;
an isolation feature disposed in the silicon-on-insulator substrate;
a back gate region disposed below the insulator layer in the silicon-on-insulator substrate inside the isolation feature;
the NORD Flash unit cell is arranged on the silicon-on-insulator substrate;
a body pull-out region in the silicon-on-insulator substrate disposed outside the isolation feature, the isolation feature constituting an insulating barrier between the body pull-out region and the NORD Flash cell.
2. The NORD Flash device of claim 1, wherein the NORD Flash cell comprises a first stacked structure and a second stacked structure which are formed by stacking a gate dielectric layer, a floating gate, an inter-electrode dielectric layer, a control gate and a word line sidewall from bottom to top, and a word line polysilicon which is arranged on the gate dielectric layer and has a bottom located between the first stacked structure and the second stacked structure.
3. The NORD Flash device of claim 2, wherein a tunneling oxide layer is disposed between the word line polysilicon and the first and second stacked structures.
4. The NORD Flash device of claim 3, wherein a first dielectric layer and a second dielectric layer are disposed outside the tunneling oxide layer.
5. The NORD Flash device of claim 1, further comprising a gate sidewall, lightly doped source drain regions, and heavily doped source drain regions.
6. A method for manufacturing a NORD Flash device is characterized by comprising the following steps:
providing a silicon-on-insulator substrate, and forming an isolation component in the silicon-on-insulator substrate;
performing an ion implantation to form a back gate region below the insulator layer in the silicon-on-insulator substrate inside the isolation feature;
forming NORD Flash unit cells on the silicon-on-insulator substrate;
forming a body pull-out region in the silicon-on-insulator substrate outside of the isolation feature, the isolation feature constituting an insulating barrier between the body pull-out region and the NORD Flash cell.
7. The method of claim 6 wherein the ion implantation is a P-type ion implantation.
8. The method of claim 6, wherein forming the body pull-out region comprises:
forming a mask layer on the silicon-on-insulator substrate, and forming an ion implantation window in the mask layer;
performing another ion implantation to form the body pull-out region in the silicon-on-insulator substrate;
and removing the mask layer.
9. The method of claim 8 wherein the another ion implanted ion type is p-type.
10. The method of manufacturing a NORD Flash device according to claim 6 or 8, further comprising, before forming the body pull-out region:
performing first ion implantation in the silicon-on-insulator substrate to form a lightly doped source drain region;
forming a grid side wall;
and performing second ion implantation in the silicon substrate on the insulator by taking the NORD Flash unit cells and the grid side wall as masks to form a heavily doped source-drain region.
11. The method of fabricating the NORD Flash device of claim 10, wherein the first ion implantation and the second ion implantation are of n-type.
12. The method of fabricating the NORD Flash device of claim 10, further comprising a step of forming a gate masking layer on top and sidewalls of the NORD Flash cell before forming the lightly doped source drain region.
13. The method of claim 10, wherein after the heavily doped source drain region is formed, a rapid annealing step is performed to activate ions in the lightly doped source drain region and the heavily doped source drain region.
14. The method of fabricating the NORD Flash device of claim 6, wherein forming the NORD Flash cell comprises:
forming a gate dielectric layer on the upper surface of the silicon-on-insulator substrate;
forming a floating gate polysilicon layer, an interelectrode dielectric layer and a control gate polysilicon layer on the gate dielectric layer in sequence;
defining a word line window, and forming a word line side wall in the word line window;
sequentially forming a first dielectric layer, a second dielectric layer, a tunneling oxide layer and word line polysilicon in the region corresponding to the word line window;
and removing the control gate polysilicon layer, the interelectrode dielectric layer, the floating gate polysilicon layer and the gate dielectric layer which are positioned at the outer side of the word line side wall.
15. The method of claim 14, wherein the defining the word line window and forming the word line sidewall in the word line window comprises:
depositing a hard mask layer on the control gate polysilicon layer;
forming the word line window in the hard mask layer through photoetching and etching processes;
and depositing an oxidation layer and carrying out back etching to form the word line side wall in the word line window.
16. The method of fabricating the NORD Flash device of claim 14, wherein the sequentially forming the first dielectric layer, the second dielectric layer, the tunneling oxide layer, and the word line polysilicon in the region corresponding to the word line window comprises:
removing the control gate polysilicon layer, the inter-electrode dielectric layer and the floating gate polysilicon layer which are not covered by the word line side wall in the region corresponding to the word line window;
sequentially forming the first dielectric layer, the second dielectric layer and the tunneling oxide layer in a region corresponding to the word line window;
and depositing polycrystalline silicon and carrying out chemical mechanical polishing, and forming the word line polycrystalline silicon in the area corresponding to the word line window.
CN202211060266.6A 2022-08-31 2022-08-31 NORD Flash device and manufacturing method thereof Pending CN115295610A (en)

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