CN114883335A - Flash memory and layout structure thereof - Google Patents
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- CN114883335A CN114883335A CN202210807510.4A CN202210807510A CN114883335A CN 114883335 A CN114883335 A CN 114883335A CN 202210807510 A CN202210807510 A CN 202210807510A CN 114883335 A CN114883335 A CN 114883335A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
Abstract
The invention provides a flash memory and a layout structure thereof, wherein a redundant grid graph of the layout structure of the flash memory comprises a redundant selection grid graph and a redundant control grid graph which are connected into a whole, namely the redundant selection grid graph and the redundant control grid graph are integrated. Therefore, the overall size of the redundant grid formed by the redundant control grid and the redundant selection grid is larger, and the contact area of the redundant grid and the bottom film layer is increased. Therefore, in the manufacturing process of the flash memory, the redundant grid is not easy to strip, and particularly, the redundant grid can be prevented from stripping in a cleaning process, so that the problem of stripping of the redundant grid can be solved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a flash memory and a layout structure thereof.
Background
Flash memory (flash) is a safe and fast memory bank, and becomes the most main carrier of data and programs in embedded systems due to a series of advantages of small volume, large capacity, low cost, no loss of power-down data and the like. In the manufacturing process of forming the flash memory, the redundant grid is easy to peel off in the cleaning process, so that the device is polluted, and the qualification rate of the device is influenced.
Disclosure of Invention
The invention aims to provide a flash memory and a layout structure thereof, which are used for solving the problem of peeling of a redundant grid.
In order to solve the technical problem, the invention provides a layout structure of a flash memory, which comprises a grid graph and redundant grid graphs positioned at two sides of the grid graph, wherein the redundant grid graphs comprise a redundant selection grid graph and a redundant control grid graph which are connected into a whole, and the redundant control grid graph is closer to the grid graph than the redundant selection grid graph.
Optionally, in the layout structure of the flash memory, the redundant gate patterns and the gate patterns are arranged along a first direction, the redundant gate patterns extend along a second direction, the redundant gate patterns and the gate patterns are parallel to each other, and the second direction is perpendicular to the first direction.
Optionally, in the layout structure of the flash memory, the redundant gate pattern is in a straight strip shape, and the size of the redundant control gate pattern is the same as the size of the redundant select gate pattern in the second direction.
Optionally, in the layout structure of the flash memory, the gate patterns include a select gate pattern and a control gate pattern arranged along the first direction, the size of the control gate pattern is larger than that of the select gate pattern in the second direction, and one end of the select gate pattern is aligned with one end of the control gate pattern.
Optionally, in the layout structure of the flash memory, the shape of the select gate pattern is a straight bar shape, and the select gate pattern extends along the second direction; the control gate pattern is in an inverted L shape, wherein the control gate pattern comprises a first partial pattern extending along the first direction and a second partial pattern extending along the second direction, and one end of the second partial pattern, which is far away from the first partial pattern, is aligned with one end of the control gate pattern.
Optionally, in the layout structure of the flash memory, the flash memory layout further includes an active region pattern extending along the first direction, a redundant active region pattern extending along the first direction, and redundant active region patterns connected to two ends of the active region pattern, a projection of the active region pattern corresponds to a projection of the gate pattern, and a projection of the redundant active region pattern corresponds to a projection of the redundant gate pattern.
Optionally, in the layout structure of the flash memory, the layout of the flash memory further includes a connection pattern extending along the second direction, and the connection pattern is located between the active region pattern and the redundant active region pattern.
Based on the same inventive concept, the present invention also provides a flash memory, comprising: the grid formed on the semiconductor substrate and the redundant grid located at two sides of the grid, wherein the redundant grid comprises a redundant selection grid and a redundant control grid, the redundant control grid is contacted with the redundant selection grid, and the redundant control grid is closer to the grid than the redundant selection grid.
Optionally, in the flash memory, the redundant gate and the gate are arranged along a first direction, the redundant gate extends along a second direction, and the redundant gate and the gate are parallel to each other, wherein the second direction is perpendicular to the first direction.
Optionally, in the flash memory, the redundant gate is shaped as a straight strip, and the size of the redundant control gate is the same as the size of the redundant select gate in the second direction.
In the layout structure of the flash memory provided by the invention, the redundant grid graph comprises a redundant selection grid graph and a redundant control grid graph which are connected into a whole, namely the redundant selection grid graph and the redundant control grid graph are integrated. Therefore, the overall size of the redundant grid formed by the redundant control grid and the redundant selection grid is larger, and the contact area of the redundant grid and the bottom film layer is increased. Therefore, in the manufacturing process of the flash memory, the redundant grid is not easy to strip, and particularly, the redundant grid can be prevented from stripping in a cleaning process, so that the problem of stripping of the redundant grid is solved.
Drawings
Fig. 1 is a schematic structural diagram of a layout structure of a flash memory according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a redundant gate pattern and a gate pattern of a layout structure of a flash memory according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of an active region pattern and a redundant active region pattern of a flash memory layout structure according to an embodiment of the present invention.
Fig. 4 is a top view of a flash memory according to an embodiment of the invention.
Fig. 5 is a schematic sectional view along a-a' direction of fig. 4.
Fig. 6 is a schematic sectional view taken along the direction B-B' of fig. 4.
Wherein the reference numerals are as follows: 110-redundant gate pattern; 111-redundant select gate pattern; 112-redundant control gate patterns; 120-gate pattern; 121-control gate pattern; 1211 — first partial graph; 1212-second partial graphic; 122-select gate pattern; 130-redundant active area pattern; 140-active area pattern; 150-connection pattern; 160-contact pattern; 200-a semiconductor substrate; 201-shallow trench isolation structures; 210-redundant gates; 211-redundant select gates; 212-redundant control gates; 220-a gate; 221-a control gate; 2211-first part; 2212-second part; 222-a select gate; 230-redundant active areas; 240-active region; 250-a connecting portion; 251-a contact portion; 261-redundant gate oxide layer; 262-redundant dummy gate; 263-redundant isolation layer; 271-redundant tunneling oxide layer; 272-redundant floating gates; 273-redundant intergate dielectric layer.
Detailed Description
The flash memory and the layout structure thereof proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 1 is a schematic structural diagram of a layout structure of a flash memory according to an embodiment of the present invention; fig. 2 is a schematic structural diagram of a redundant gate pattern and a gate pattern of a layout structure of a flash memory according to an embodiment of the present invention.
Referring to fig. 1 in combination with fig. 2, the layout structure of the flash memory includes a gate pattern 120 and redundant gate patterns 110 located at two sides of the gate pattern 120, where the redundant gate patterns 110 include a redundant selection gate pattern 111 and a redundant control gate pattern 112 connected as a whole, and the redundant control gate pattern 112 is closer to the gate pattern 120 than the redundant selection gate pattern 111.
Specifically, the redundant gate pattern 110 is used to define a redundant gate in a flash memory. The redundant selection gate pattern 111 is used for defining a redundant selection gate, and the redundant control gate pattern 112 is used for defining a redundant control gate. Since the redundant selection gate pattern 111 and the redundant control gate pattern 112 are connected into a whole, the overall size of the redundant gate formed by the redundant control gate and the redundant selection gate can be made larger, and the contact area between the redundant gate and the bottom film layer is increased, so that the redundant gate is not easy to peel off in the manufacturing process of the flash memory. In particular, the peeling of the redundant gate in a cleaning process (e.g., an ultrasonic cleaning process) can be avoided, so that the problem of the peeling of the redundant gate can be solved.
As shown in fig. 2, the redundant gate patterns 110 and the gate patterns 120 are arranged along a first direction Y. The redundant gate pattern 110 extends along a second direction X, and the redundant gate pattern 110 and the gate pattern 120 are parallel to each other, wherein the second direction X is perpendicular to the first direction Y.
In this embodiment, the redundant gate pattern 110 is a straight bar, and the size of the redundant control gate pattern 112 is the same as the size of the redundant selection gate pattern 111 in the second direction X, that is, the length of the redundant control gate pattern 112 is the same as the length of the redundant selection gate pattern 111. In this way, the end portions of the redundant control gate patterns 112 are aligned with the end portions of the redundant select gate patterns 111, so that the redundant control gates defined by the redundant control gate patterns 112 and the redundant select gates defined by the redundant select gate patterns 111 are not easy to peel off in the manufacturing process of the flash memory, and particularly, the peeling off in the cleaning process can be avoided, thereby solving the problem of the peeling off of the redundant gates.
As shown in fig. 2, the gate pattern 120 includes a control gate pattern 121 and a select gate pattern 122 arranged in the first direction Y. The select gate pattern 122 is used to define a select gate, and the control gate pattern 121 is used to define a control gate. The size of the control gate pattern 121 is larger than that of the select gate pattern 122 in the second direction X, and one end of the select gate pattern 122 is aligned with one end of the control gate pattern 121. By the arrangement, the preparation difficulty of the selection gate and the control gate can be reduced.
In this embodiment, the shape of the select gate pattern 122 is a straight bar shape, and the select gate pattern 122 extends along the second direction X.
As shown in fig. 2, the control gate pattern 121 has an inverted L-shape, wherein the control gate pattern 121 includes a first partial pattern 1211 extending along the first direction Y and a second partial pattern 1212 extending along the second direction X, and an end of the second partial pattern 1212, which is away from the first partial pattern 1211, is aligned with an end of the selection gate pattern 122. The second portion 1212 is used to define a body portion of the control gate, and the first portion 1211 is used to define a portion of the control gate electrically connected to the outside (i.e., a portion electrically connected to the contact plug).
In this embodiment, the size of the redundant gate pattern 110 in the second direction X may be the same as the size of the control gate pattern 121, that is, the length of the redundant gate pattern 110 may be the same as the length of the control gate pattern 121. Therefore, the uniformity of the selection gate and the control gate in the flash memory can be improved, the difference of the sizes of the control gates in the flash memory is improved, and the difference of the sizes of the selection gates in the flash memory is improved.
Fig. 3 is a schematic structural diagram of the active region pattern 140 and the redundant active region pattern 130 of the flash memory layout structure according to the embodiment of the present invention. As shown in fig. 3, the flash memory layout structure further includes a redundant active area pattern 130 extending along the first direction Y and an active area pattern 140 extending along the first direction Y, the redundant active area pattern 130 is connected to two ends of the active area pattern 140, a projection of the active area pattern 140 corresponds to a projection of the gate pattern 120, and a projection of the redundant active area pattern 130 corresponds to a projection of the redundant gate pattern 110.
Specifically, the gate pattern 120 is located on the active region pattern 140, and the redundancy gate pattern 110 is located on the redundancy active region pattern 130. In this embodiment, the active region pattern 140 is used to define an active region, the redundant active region pattern 130 is used to define a redundant active region, and the existence of the redundant active region pattern 130 can improve the uniformity of the active region, such as the uniformity of the active region surface after chemical mechanical polishing.
In this embodiment, the flash memory layout structure further includes a connection pattern 150 extending along the second direction X, the connection pattern 150 is located between the active region pattern 140 and the redundant active region pattern 130, and the connection pattern 150 is connected to the active region pattern 140 and the redundant active region pattern 130. The connection pattern 150 may be used to define an electrical connection structure between the active regions to electrically connect the active regions.
As shown in fig. 3, the flash memory layout structure further includes a contact pattern 160, and the contact pattern 160 is connected to the active region pattern 140 to define a contact hole.
In this embodiment, the flash memory layout structure may be used to form a non-volatile flash memory.
Fig. 4 is a top view of a flash memory according to an embodiment of the invention. Fig. 5 is a schematic sectional view along a-a' direction of fig. 4. Fig. 6 is a schematic sectional view taken along the direction B-B' of fig. 4. Based on the same inventive concept, an embodiment of the present invention provides a flash memory, as shown in fig. 4, the flash memory includes a gate 220 formed on a semiconductor substrate 200 and a redundant gate 210 located at two sides of the gate 220, the redundant gate 210 includes a redundant select gate 211 and a redundant control gate 212, the redundant control gate 212 is in contact with the redundant select gate 211, and the redundant control gate 212 is closer to the gate 220 than the redundant select gate 211.
Since the redundant control gate 212 is in contact with the redundant select gate 211, there is no gap between them. In this way, the overall size of the redundant gate 210 formed by the redundant control gate 212 and the redundant select gate 211 is large, and the contact area between the redundant gate 210 and the bottom film layer thereof is increased, so that the redundant gate 210 is not easy to peel off in the manufacturing process of the flash memory. In particular, the peeling of the redundant gate 210 during the cleaning process can be avoided, so that the problem of the peeling of the redundant gate 210 can be solved.
As shown in fig. 5 and fig. 6, the semiconductor substrate 200 may be a silicon substrate, and a shallow trench isolation structure 201 is formed in the semiconductor substrate 200, where the shallow trench isolation structure 201 is used to define an active region of the semiconductor substrate 200.
As shown in fig. 4, the redundant gate 210 and the gate 220 are arranged along a first direction Y; the redundant gate 210 extends along a second direction X, which is perpendicular to the first direction Y.
In this embodiment, the cross-sectional shape (the cross-sectional shape in the horizontal direction) of the redundant gate 210 is a straight bar, and the size of the redundant control gate 212 is the same as the size of the redundant select gate 211 in the second direction X, that is, the length of the redundant control gate 212 is the same as the length of the redundant select gate 211. In this way, the end of the redundant control gate 212 is aligned with the end of the redundant select gate 211, which can reduce the area occupied by the redundant control gate 212 and the redundant select gate 211.
In this embodiment, the flash memory further includes a gate 220, and the gate 220 includes a control gate 221 and a select gate 222 arranged along the first direction Y, where the select gate 222 may be used to form a select transistor, and the control gate 221 may be used to form a control transistor. The size of the control gate 221 in the second direction X may be larger than the size of the select gate 222. In other embodiments, the size of control gate 221 may be the same as the size of select gate 222.
In this embodiment, one end of the select gate 222 is aligned with one end of the control gate 221. By such an arrangement, the difficulty in manufacturing the select gate 222 and the control gate 221 can be reduced.
In this embodiment, the cross-sectional shape of the select gate 222 is a straight bar, and the select gate 222 extends along the second direction X. The control gate 221 has an inverted L shape, wherein the control gate 221 includes a first portion 2211 extending along the first direction Y and a second portion 2212 extending along the second direction X, and an end of the second portion 2212 away from the first portion 2211 is aligned with an end of the select gate 222. The second portion 2212 is used for forming a main body portion of the control gate 221, and the first portion 2211 is used for forming a portion where the control gate 221 is electrically connected to the outside (i.e., a portion where the control gate is electrically connected to a contact plug).
In this embodiment, the size sum of the redundant gate 210 in the second direction X may be the same as the size sum of the control gate 221, that is, the length of the redundant gate 210 may be the same as the length of the control gate 221. Therefore, the uniformity of the redundant gate 210 and the control gate 221 in the flash memory can be improved, and the size difference between the control gate 221 and the redundant gate 210 in the flash memory can be improved.
As shown in fig. 5, the flash memory further includes a redundant gate oxide layer 261 and a redundant dummy gate 262 between the semiconductor substrate 200 and the redundant select gate 211, wherein the redundant dummy gate 262 covers the redundant gate oxide layer 261. Further, there is a trench between the redundant dummy gates 262, and the redundant select gate 211 fills the trench between the redundant dummy gates 262 and covers the redundant dummy gates 262. And, the flash memory further includes a redundant isolation layer 263, the redundant isolation layer 263 covers the bottom wall and the sidewall of the trench between the redundant dummy gates 262 for isolation.
As shown in fig. 6, the flash memory further includes a redundant tunneling oxide layer 271 and a redundant floating gate 272 between the semiconductor substrate 200 and the redundant control gate 212, and the redundant floating gate 272 covers the redundant tunneling oxide layer 271. The material of the redundant floating gate 272 may be doped polysilicon. The redundant floating gates 272 have trenches between them, and the redundant control gates 212 fill the trenches between the redundant floating gates 272 and extend over the redundant floating gates 272. Further, a redundant inter-gate dielectric layer 273 is formed between the redundant floating gate 272 and the redundant control gate 212, and the redundant inter-gate dielectric layer 273 is used for isolating the redundant floating gate 272 from the redundant control gate 212.
In this embodiment, the flash memory further includes a tunneling oxide layer and a floating gate (not shown) between the semiconductor substrate 200 and the control gate 221, and the floating gate covers the tunneling oxide layer. The floating gate may be made of doped polysilicon, and is used for storing electrons. Electrons in the floating gate can tunnel through the tunneling oxide layer to a semiconductor substrate. The tunneling oxide layer may be made of silicon oxide. The floating gates have trenches between them, and the control gates 221 fill the trenches between the floating gates and extend over the control gates 221. Further, an inter-gate dielectric layer (not shown) is formed between the floating gate and the control gate 221, and the inter-gate dielectric layer is used for isolating the floating gate from the control gate 221.
In this embodiment, the flash memory further includes a gate oxide layer and a dummy gate between the semiconductor substrate 200 and the select gate 222, and the dummy gate covers the gate oxide layer, wherein the gate oxide layer, the tunnel oxide layer, the redundant tunnel oxide layer 271, and the redundant gate oxide layer 261 are all made of silicon oxide and may be formed in the same process step.
Trenches are formed between the dummy gates, and the select gates 222 fill the trenches between the dummy gates and cover the dummy gates. And, the flash memory further includes an isolation layer (not shown) covering a bottom wall and a sidewall of the trench between the dummy gates for isolation.
In this embodiment, the dummy gate and the control gate 221 may be doped polysilicon. The dummy gate, redundant dummy gate 262, floating gate, and redundant floating gate 272 may be formed in the same process. The redundant control gates 212, the redundant select gates 211, the select gates and the control gates may be formed in the same process to save process steps.
In this embodiment, the flash memory may be a non-volatile flash memory.
In summary, in the flash memory and the layout structure thereof provided by the invention, the redundant gate patterns of the layout structure of the flash memory comprise the redundant selection gate patterns and the redundant control gate patterns which are connected into a whole, namely the redundant selection gate patterns and the redundant control gate patterns are integrated, in the manufacturing process of the flash memory, the redundant selection gates defined by the redundant selection gate patterns are contacted with the control gates defined by the redundant control gate patterns, and no gap exists between the redundant selection gates and the control gates. Therefore, the overall size of the redundant grid formed by the redundant control grid and the redundant selection grid is larger, and the contact area of the redundant grid and the bottom film layer is increased. Therefore, in the manufacturing process of the flash memory, the redundant grid is not easy to strip, and particularly, the redundant grid can be prevented from stripping in a cleaning process, so that the problem of stripping of the redundant grid can be solved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A layout structure of a flash memory is characterized by comprising a grid graph and redundant grid graphs positioned on two sides of the grid graph, wherein the redundant grid graphs comprise a redundant selection grid graph and a redundant control grid graph which are connected into a whole, and the redundant control grid graph is closer to the grid graph than the redundant selection grid graph.
2. The flash memory layout structure of claim 1, wherein the redundancy gate patterns and the gate patterns are arranged along a first direction, the redundancy gate patterns extend along a second direction, the redundancy gate patterns and the gate patterns are parallel to each other, wherein the second direction is perpendicular to the first direction.
3. The flash memory layout structure of claim 2, wherein the redundant gate pattern is shaped as a straight bar, and the size of the redundant control gate pattern is the same as the size of the redundant select gate pattern in the second direction.
4. The flash memory layout structure of claim 2, wherein the gate patterns comprise a control gate pattern and a select gate pattern arranged along the first direction, the control gate pattern and the select gate pattern are parallel to each other, a size of the control gate pattern is larger than a size of the select gate pattern in the second direction, and one end of the select gate pattern is aligned with one end of the control gate pattern.
5. The flash memory layout structure of claim 4, wherein the select gate pattern is in the shape of a straight bar, and the select gate pattern extends along the second direction; the control gate pattern is in an inverted L shape, wherein the control gate pattern comprises a first partial pattern extending along the first direction and a second partial pattern extending along the second direction, and one end of the second partial pattern, which is far away from the first partial pattern, is aligned with one end of the control gate pattern.
6. The flash memory layout structure of claim 2, wherein the flash memory layout further comprises an active region pattern extending along the first direction and a redundant active region pattern extending along the first direction, the redundant active region pattern being connected at both ends of the active region pattern, a projection of the active region pattern corresponding to a projection of the gate pattern, and a projection of the redundant active region pattern corresponding to a projection of the redundant gate pattern.
7. The flash memory layout structure of claim 6, wherein the flash memory layout further comprises a connection pattern extending along the second direction, the connection pattern being located between the active region pattern and the redundant active region pattern.
8. A flash memory, comprising:
the grid formed on the semiconductor substrate and the redundant grid located at two sides of the grid, wherein the redundant grid comprises a redundant selection grid and a redundant control grid, the redundant control grid is contacted with the redundant selection grid, and the redundant control grid is closer to the grid than the redundant selection grid.
9. The flash memory of claim 8 wherein the redundant gate and the gate are arranged along a first direction, the redundant gate extends along a second direction, the redundant gate and the gate are parallel to each other, and wherein the second direction is perpendicular to the first direction.
10. The flash memory of claim 9 wherein the cross-sectional shape of the redundancy gate is a straight stripe and the size of the redundancy control gate and the size of the redundancy select gate in the second direction are the same.
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| CN116209268A (en) * | 2023-05-04 | 2023-06-02 | 粤芯半导体技术股份有限公司 | Semiconductor Flash structure and preparation method thereof |
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