CN114758955A - Flash memory structure and manufacturing method thereof - Google Patents

Flash memory structure and manufacturing method thereof Download PDF

Info

Publication number
CN114758955A
CN114758955A CN202210659132.XA CN202210659132A CN114758955A CN 114758955 A CN114758955 A CN 114758955A CN 202210659132 A CN202210659132 A CN 202210659132A CN 114758955 A CN114758955 A CN 114758955A
Authority
CN
China
Prior art keywords
layer
passivation layer
passivation
flash memory
interconnection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202210659132.XA
Other languages
Chinese (zh)
Other versions
CN114758955B (en
Inventor
沈安星
张有志
胡晓峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yuexin Semiconductor Technology Co.,Ltd.
Original Assignee
Guangzhou Yuexin Semiconductor Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangzhou Yuexin Semiconductor Technology Co Ltd filed Critical Guangzhou Yuexin Semiconductor Technology Co Ltd
Priority to CN202210659132.XA priority Critical patent/CN114758955B/en
Publication of CN114758955A publication Critical patent/CN114758955A/en
Application granted granted Critical
Publication of CN114758955B publication Critical patent/CN114758955B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Abstract

The invention provides a method for manufacturing a flash memory structure, which comprises the following steps: forming an interconnection layer on the semiconductor layer, wherein a storage unit is arranged in the semiconductor layer, and the top surface of the interconnection layer is exposed out of the top metal connecting line layer; forming a first passivation layer on the interconnection layer; an alloying annealing step at a temperature above 400 ℃; and sequentially forming a second passivation layer, a third passivation layer and a fourth passivation layer on the first passivation layer, wherein the fourth passivation layer comprises a silicon nitride layer, and the material of the first passivation layer is different from that of the fourth passivation layer. The manufacturing method of the flash memory structure advances the alloying annealing step to the front of the silicon nitride deposition, and the high-temperature process is not arranged behind the silicon nitride deposition process flow of the passivation layer, so that H + ions cannot be decomposed from hydrogen rich in the silicon nitride film, and the possibility that electrons in the tunneling dielectric layer and even in the floating gate are sucked out due to the larger electric field intensity is eliminated. DRB test results show that the DRB performance of the flash memory structure is obviously improved, and the flash memory structure meets the reliability requirement.

Description

Flash memory structure and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a flash memory structure and a manufacturing method thereof.
Background
The Flash Memory (Flash Memory) is a non-volatile Memory integrated circuit, and has the main characteristics of high working speed, small unit area, high integration level, good reliability, repeated erasing and writing for more than 10 ten thousand times, and reliable data retention for more than 10 years. FLASH basic cells are classified into N-channel FLASH memory (nFLASH) and P-channel FLASH memory (pFLASH) according to the type of carriers generating current.
In the manufacture of flash memory structures, basic memory cells are typically fabricated on a semiconductor substrate, and then an interconnect layer including a metal interconnect layer and a metal plug is formed on the semiconductor layer on which the memory cells are fabricated to provide the necessary connections for the various devices. In addition, to avoid the integrated circuit from moisture, impurities and external mechanical damage, a passivation layer is formed on the interconnection layer.
In the prior art, after a passivation layer forming process is completed, high-temperature alloying treatment is generally required to be carried out on top layer metal of an interconnection layer, so that better conductive performance and bonding strength between the metal and a chip can be ensured, and a dangling bond formed in the previous process can be repaired. However, since the passivation layer usually comprises a silicon nitride layer, which is a hydrogen-rich thin film and thick, the hydrogen-rich in the silicon nitride film in the passivation layer is decomposed into H + ions by high temperature during the high temperature alloying process, and the H + ions are small in volume and easily and rapidly move to the bottom of the floating gate channel of pFlash through metal and via/contact connection vias. H + ions rapidly moving to the lower part of the pFlash floating gate channel can be bonded with a dangling bond of a tunneling oxide layer/silicon interface, and electrons in the tunneling oxide layer and even in the floating gate can be sucked out due to larger electric field intensity, so that poorer pFlash Data Retention baking (Data Retention baker, DRB for short) performance is caused.
Therefore, how to improve the manufacturing process of the flash memory structure to further improve the data retention capability of the flash memory structure becomes an important technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a flash memory structure and a method for fabricating the same, which are used to solve the problem that the data retention capability of the flash memory structure is reduced due to the fact that hydrogen ions are easily moved under a floating gate and electrons in the floating gate are absorbed by the existing process for fabricating the flash memory structure.
To achieve the above and other related objects, the present invention provides a method for fabricating a flash memory structure, comprising the steps of:
forming an interconnection layer on a semiconductor layer, wherein a storage unit is arranged in the semiconductor layer, the interconnection layer comprises at least one dielectric layer and a plurality of metal connecting line layers which are stacked, adjacent metal connecting line layers are connected through a metal plug, and the top surface of the interconnection layer is exposed out of the top metal connecting line layer;
forming a first passivation layer on the interconnection layer to cover the top metal wiring layer;
an alloying annealing step at a temperature above 400 ℃;
and sequentially forming a second passivation layer, a third passivation layer and a fourth passivation layer on the first passivation layer, wherein the fourth passivation layer comprises a silicon nitride layer, and the material of the first passivation layer is different from that of the fourth passivation layer.
Optionally, the alloying annealing step adopts an annealing temperature range of 400-500 ℃ and an annealing time of 10-60 minutes.
Optionally, the first passivation layer comprises a silicon-rich oxide layer, the second passivation layer comprises a high density plasma chemical vapor deposition silicon oxide layer, the third passivation layer comprises a plasma-assisted undoped silicon glass layer, and the fourth passivation layer comprises a silicon nitride layer.
Optionally, the thickness of the fourth passivation layer ranges from 5000 angstroms to 7000 angstroms.
Optionally, after forming the third passivation layer and before forming the fourth passivation layer, a step of performing chemical mechanical polishing on the third passivation layer is further included.
Optionally, after the fourth passivation layer is formed, a passivation layer patterning step is further included to form an opening sequentially penetrating through the fourth passivation layer, the third passivation layer, the second passivation layer and the first passivation layer from top to bottom, and a preset region of the top metal interconnection layer is exposed at the bottom of the opening.
Optionally, the method further comprises a step of forming a pad on the fourth passivation layer, wherein the pad is electrically connected with the top metal wiring layer through the opening.
Optionally, the memory cell comprises a P-channel control gate transistor and a P-channel select gate transistor in series.
Optionally, the control gate transistor and the select gate transistor both include a tunneling dielectric layer, a floating gate layer, an isolation layer, and a logic layer stacked in sequence from bottom to top.
The present invention also provides a flash memory structure, comprising:
a semiconductor layer having a memory cell therein;
the interconnection layer is positioned on the semiconductor layer and electrically connected with the storage unit, the interconnection layer comprises at least one dielectric layer and a plurality of metal connecting line layers which are stacked, adjacent metal connecting line layers are connected through a metal plug, and the top surface of the interconnection layer is exposed out of the top metal connecting line layer;
the passivation layer is positioned on the interconnection layer and comprises a first passivation layer, a second passivation layer, a third passivation layer and a fourth passivation layer which are sequentially stacked from bottom to top, wherein the fourth passivation layer comprises a silicon nitride layer, and the material of the first passivation layer is different from that of the fourth passivation layer;
the flash memory structure is manufactured by adopting the manufacturing method of the flash memory structure.
As described above, the method for fabricating a flash memory structure of the present invention includes forming an interconnection layer on a semiconductor layer, forming a first passivation layer on the interconnection layer to cover a top metal interconnection layer, performing an alloying annealing step at a temperature higher than 400 ℃, and sequentially forming a second passivation layer, a third passivation layer, and a fourth passivation layer on the first passivation layer, wherein the fourth passivation layer includes a silicon nitride layer, and the material of the first passivation layer is different from that of the fourth passivation layer. According to the invention, the alloying annealing step is advanced before the silicon nitride deposition, a high-temperature process is not required behind the silicon nitride deposition process flow of the passivation layer, and H + ions cannot be decomposed from hydrogen rich in the silicon nitride film, so that the possibility that electrons in the tunneling dielectric layer and even in the floating gate are sucked out due to high electric field intensity is eliminated. DRB test results show that the DRB performance of the flash memory structure is obviously improved, and the programming threshold voltage Vt _ Pgm is only 0.4V lower than the initial threshold voltage, so that the flash memory structure meets the reliability requirement.
Drawings
FIG. 1 is a process flow diagram of a method for fabricating a flash memory structure according to the present invention.
FIG. 2 is a schematic diagram of a method for fabricating a flash memory structure according to the present invention, in which an interconnection layer is formed on a semiconductor layer.
Fig. 3 is a schematic diagram illustrating a first passivation layer formed on the interconnect layer according to the method for fabricating a flash memory structure of the present invention.
Fig. 4 is a schematic diagram illustrating a method for manufacturing a flash memory structure according to the present invention, in which a second passivation layer, a third passivation layer, and a fourth passivation layer are sequentially formed on the first passivation layer.
Fig. 5 is a schematic diagram illustrating passivation layer patterning performed by the method for fabricating a flash memory structure according to the present invention.
Fig. 6 is a schematic diagram illustrating the formation of a bonding pad 5 on the fourth passivation layer 304 according to the method for fabricating a flash memory structure of the present invention.
Fig. 7 shows DRB performance after baking at 250 ℃ for 24 hours comparing the pFlash structure with the pFlash structure made by the flash memory structure fabrication method of the present invention.
Element number description: the semiconductor substrate comprises a semiconductor layer 1, a 101N-type substrate, a 102P-type source region, a 103P-type internal node region, a 104P-type drain region, a 105a tunneling dielectric layer, a 105b floating gate layer, a 105c isolation layer, a 105d logic layer, a 106a tunneling dielectric layer, a 106b floating gate layer, a 106c isolation layer, a 106d logic layer, a 107 side wall, a 108 protective layer, an 109 interlayer dielectric layer, a 2 interconnection layer, a 201 dielectric layer, a 202 metal connecting line layer, a 203 metal plug, a 3 passivation layer, a 301 first passivation layer, a 302 second passivation layer, a 303 third passivation layer, a 304 fourth passivation layer, a 4 opening and a 5 bonding pad.
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 7. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
In this embodiment, a method for fabricating a flash memory structure is provided, please refer to fig. 1, which shows a process flow diagram of the method, including the following steps:
s1: forming an interconnection layer on a semiconductor layer, wherein a storage unit is arranged in the semiconductor layer, the interconnection layer comprises at least one dielectric layer and a plurality of metal connecting line layers which are stacked, adjacent metal connecting line layers are connected through a metal plug, and the top surface of the interconnection layer is exposed out of the top metal connecting line layer;
s2: forming a first passivation layer on the interconnection layer to cover the top metal connecting line layer;
s3: performing an alloying annealing step at a temperature above 400 ℃ to alloy the metal interconnect layer;
s4: and sequentially forming a second passivation layer, a third passivation layer and a fourth passivation layer on the first passivation layer, wherein the fourth passivation layer comprises a silicon nitride layer, and the material of the first passivation layer is different from that of the fourth passivation layer.
Referring to fig. 2, the step S1 is executed: forming an interconnection layer 2 on the semiconductor layer 1, wherein a storage unit is arranged in the semiconductor layer 1, the interconnection layer 2 comprises at least one dielectric layer 201 and a plurality of metal interconnection layers 202 which are stacked, adjacent metal interconnection layers 202 are connected through metal plugs 203, and the top metal interconnection layer is exposed on the top surface of the interconnection layer 2.
In this embodiment, the memory cell is exemplified by a P-channel Flash memory cell, and includes a P-channel control gate transistor and a P-channel select gate transistor connected in series.
As an example, the semiconductor layer 1 includes an N-type substrate 101, the memory cell includes a P-type source region 102, a P-type internal node region 103, a P-type drain region 104, a control gate structure and a select gate structure, the P-type source region 102, the P-type internal node region 103 and the P-type drain region 104 are all located in the N-type substrate 101, the P-type internal node region 103 is located between the P-type source region 102 and the P-type drain region 104 and is spaced from the P-type source region 102 and the P-type drain region 104 by a predetermined distance, the control gate structure is located on the N-type substrate 101 and spans between the P-type source region 102 and the P-type internal node region 103, the select gate structure is located on the N-type substrate 101 and spans between the P-type internal node region 103 and the P-type drain region 104, and the control gate structure includes a tunneling dielectric layer 105a, a, The select gate structure comprises a tunneling dielectric layer 106a, a floating gate layer 106b, an isolation layer 105c and a logic layer 105d which are sequentially stacked from bottom to top, wherein the P-type source region 102 serves as a source region of the control gate transistor, the P-type internal node region 103 serves as a drain region of the control gate transistor and a source region of the select gate transistor at the same time, the P-type drain region 104 serves as a drain region of the select gate transistor, the P-type source region 102 is connected with a source line SL, the P-type drain region 104 is connected with a bit line BL, the logic layer 105d of the control gate structure is connected with a control gate line CG, and the floating gate layer 106b of the select gate structure is connected with a select gate line SG.
As an example, the N-type base 101 may be an N-type doped silicon substrate, or may be an N-type well region formed in a P-type silicon substrate, and the doping concentrations of the P-type source region 102, the P-type internal node region 103, and the P-type drain region 104 are all higher than the doping concentration of the N-type base 1.
As an example, the tunneling dielectric layer of the control gate structure and the tunneling dielectric layer of the select gate structure comprise silicon dioxide grown by a thermal oxidation method, the floating gate layer comprises N-type or P-type polysilicon, the isolation layer comprises a silicon oxide layer-silicon nitride layer-silicon oxide layer laminated structure, and the logic layer comprises P-type polysilicon.
As an example, the semiconductor layer 1 further includes sidewalls 107 located at two sides of the control gate structure and two sides of the select gate structure, and includes a protection layer 108 covering the control gate structure and the select gate structure, and an interlayer dielectric layer 109 located on the protection layer 108, where the sidewalls 107 may include at least one of a silicon oxide layer and a silicon nitride layer, the protection layer 108 may be a silicon nitride layer or another suitable insulating layer, and the interlayer dielectric layer 109 may be a silicon oxide layer or another suitable insulating layer.
As an example, the interconnection layer 2 is obtained by alternately forming a metal interconnection layer and a dielectric layer, wherein before forming the next metal interconnection layer, the dielectric layer may be patterned by photolithography, etching, and the like to obtain a contact hole, so that when forming the metal interconnection layer subsequently, a metal material may be filled in the contact hole to obtain the metal plug 203.
As an example, the thickness of the top metal wiring layer is larger than the thickness of the other metal wiring layers in the interconnect layer 2 to buffer the bonding stress.
By way of example, the material of the dielectric layer 201 may be silicon oxide or other suitable materials, and the material of the metal wire layer 202 may include one or more of copper, aluminum, silver, and gold, and may also include other suitable materials.
Referring back to fig. 3, the step S2 is executed: a first passivation layer 301 is formed on the interconnect layer 2 to cover the top metal wiring layer.
By way of example, the first passivation layer 301 includes a silicon-rich oxide layer that provides protection to the top metal interconnect layer during a subsequent alloying anneal. The silicon-rich oxide refers to a silicon oxide material with silicon content larger than that of conventional silicon dioxide, and can be prepared by a plasma chemical vapor deposition method.
The step S3 is then executed: the alloying annealing step is carried out at a temperature above 400 ℃.
Specifically, the alloying annealing can release stress among layers, strengthen the interface bonding tightness of the metal connecting line layer and the dielectric layer so as to prevent the metal connecting line layer from peeling off when the bonding pad is subsequently subjected to wire bonding, reduce the resistance between the contact surfaces of the layers so as to enhance the conductive performance of the device and repair a suspended bond formed in the previous process.
As an example, the alloying annealing step adopts the annealing temperature range of 400-500 ℃ and the annealing time of 10-60 minutes. In this embodiment, the annealing temperature adopted in the alloying annealing step is 410 ℃, and the annealing time is 30 minutes.
Finally, referring to fig. 4, the step S4 is executed: a second passivation layer 302, a third passivation layer 303 and a fourth passivation layer 304 are sequentially formed on the first passivation layer 301, wherein the fourth passivation layer 304 includes a silicon nitride layer, and the material of the first passivation layer 301 is different from that of the fourth passivation layer 304.
As an example, the second passivation layer 302 includes a high density plasma chemical vapor deposition (HDP) silicon oxide layer, which can better fill the gap between the top metal layers and prevent voids from occurring.
As an example, the third passivation layer 303 includes a plasma-assisted undoped silicon glass (PE-USG), and in this embodiment, before forming the fourth passivation layer 304, a step of performing chemical mechanical polishing on the third passivation layer 303 is further included to improve uniformity and smoothness of the passivation layer.
As an example, the fourth passivation layer 304 includes a silicon nitride layer, which can effectively block water vapor and alkali metal ions. As an example, the thickness of the fourth passivation layer 304 ranges from 5000 angstroms to 7000 angstroms, and in this embodiment, the thickness of the fourth passivation layer 304 is 6000 angstroms as an example.
As an example, a silicon nitride layer is prepared by Plasma Enhanced Chemical Vapor Deposition (PECVD), wherein the gases used include hydrogen (which acts to passivate internal defects of the film), nitrogen, and silane. Since the reaction gas contains hydrogen, the fourth passivation layer 304 is a hydrogen-rich thin film. Since the alloying annealing step is advanced to the time before the silicon nitride deposition in the embodiment, a high-temperature process is not needed behind the silicon nitride deposition process flow of the passivation layer, and H + ions cannot be decomposed from hydrogen rich in the silicon nitride film, so that the possibility that electrons in the tunneling dielectric layer and even in the floating gate are sucked out due to high electric field intensity is eliminated.
As an example, referring to fig. 5, after the fourth passivation layer 304 is formed, a passivation layer patterning step is further performed to form an opening 4 sequentially penetrating through the fourth passivation layer 304, the third passivation layer 303, the second passivation layer 302 and the first passivation layer 301 from top to bottom, and a predetermined region of the top metal interconnection layer is exposed at the bottom of the opening 4.
As an example, referring to fig. 6, a pad 5 is further formed on the fourth passivation layer 304, and the pad 5 is electrically connected to the top metal wiring layer through the opening 4.
Thus, the manufacture of the flash memory structure is completed. Referring to fig. 7, the DRB performance of the comparison pFlash structure and the pFlash structure manufactured by the method for manufacturing the flash memory structure of the present invention after baking at 250 ℃ for 24 hours is shown, wherein the alloying annealing step of the comparison pFlash structure is performed after the fourth passivation layer is formed, and the abscissa Vcg in the figure represents the control gate voltage, which shows that the DRB performance of the comparison pFlash structure after baking at 250 ℃ for 24 hours is very poor, and the programming threshold voltage Vt — Pgm drops by 3V relative to the initial threshold voltage; the DRB performance of the pFlash structure manufactured by the manufacturing method of the flash memory structure is obviously improved after the pFlash structure is baked for 24 hours at 250 ℃, and Vt _ Pgm only drops 0.4V, so that the reliability requirement is met.
The reason for the above difference in performance is that the fourth passivation layer 304 is a hydrogen-rich thin film and has a very thick thickness, and after the alloying annealing process, the hydrogen-rich in the silicon nitride thin film is decomposed into H + ions at a high temperature of 400 ℃ or higher, and the H + ions have a very small volume and are easily and rapidly moved to the lower side of the floating gate channel of pFlash through metal and via/contact connection vias. H + ions moving rapidly to the bottom of the pFlash floating gate channel will bond with the dangling bonds at the tunnel oxide/silicon interface and will also draw electrons out of the tunnel oxide and even the floating gate due to the large electric field strength, resulting in poor pFlash DRB (250 ℃, 24 hours) performance. The manufacturing method of the flash memory structure advances the alloying annealing step to the front of the deposition of the thick silicon nitride layer, so that the high-temperature process with the temperature of more than 400 ℃ does not exist behind the thick silicon nitride deposition process flow, and H + ions cannot be decomposed from hydrogen rich in the thick silicon nitride film, thereby avoiding the possibility of sucking electrons in a tunneling oxide layer and even a floating gate due to higher electric field intensity.
Example two
In this embodiment, a flash memory structure is provided, which can be manufactured by the method for manufacturing a flash memory structure described in the first embodiment, and please refer to fig. 6, which shows a schematic cross-sectional structure diagram of the flash memory structure, and includes a semiconductor layer 1, an interconnection layer 2 and a passivation layer 3, wherein a memory cell is disposed in the semiconductor layer 1, the interconnection layer 2 is disposed on the semiconductor layer 1 and electrically connected to the memory cell, the interconnection layer 2 includes at least one stacked dielectric layer 201 and a plurality of metal interconnection layers 202, adjacent metal interconnection layers 202 are connected by a metal plug 203, a top metal interconnection layer is exposed on a top surface of the interconnection layer 2, the passivation layer 3 is disposed on the interconnection layer, the passivation layer 3 includes a first passivation layer 301, a second passivation layer 302, a third passivation layer 303 and a fourth passivation layer 304 that are sequentially stacked from bottom to top, the fourth passivation layer 304 includes a silicon nitride layer, and the material of the first passivation layer 301 is different from that of the fourth passivation layer 304.
In summary, in the method for fabricating the flash memory structure of the present invention, an interconnection layer is formed on a semiconductor layer, a first passivation layer is formed on the interconnection layer to cover a top metal interconnection layer, an alloying annealing step is performed at a temperature higher than 400 ℃ to alloy the top metal interconnection layer, and a second passivation layer, a third passivation layer and a fourth passivation layer are sequentially formed on the first passivation layer, wherein the fourth passivation layer includes a silicon nitride layer, and the material of the first passivation layer is different from that of the fourth passivation layer. According to the invention, the alloying annealing step is advanced before the silicon nitride deposition, a high-temperature process is not required behind the silicon nitride deposition process flow of the passivation layer, and H + ions cannot be decomposed from hydrogen rich in the silicon nitride film, so that the possibility that electrons in the tunneling dielectric layer and even in the floating gate are sucked out due to high electric field intensity is eliminated. DRB test results show that the DRB performance of the flash memory structure is obviously improved and meets the reliability requirement. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims (10)

1. A method for manufacturing a flash memory structure is characterized by comprising the following steps:
forming an interconnection layer on a semiconductor layer, wherein a storage unit is arranged in the semiconductor layer, the interconnection layer comprises at least one dielectric layer and a plurality of metal connecting line layers which are stacked, adjacent metal connecting line layers are connected through a metal plug, and the top surface of the interconnection layer is exposed out of the top metal connecting line layer;
forming a first passivation layer on the interconnection layer to cover the top metal wiring layer;
an alloying annealing step at a temperature above 400 ℃;
and sequentially forming a second passivation layer, a third passivation layer and a fourth passivation layer on the first passivation layer, wherein the fourth passivation layer comprises a silicon nitride layer, and the material of the first passivation layer is different from that of the fourth passivation layer.
2. The method of claim 1, wherein: the annealing temperature range adopted in the alloying annealing step is 400-500 ℃, and the annealing time is 10-60 minutes.
3. The method of claim 1, wherein: the first passivation layer comprises a silicon-rich oxide layer, the second passivation layer comprises a high density plasma chemical vapor deposition silicon oxide layer, and the third passivation layer comprises a plasma-assisted undoped silicon glass layer.
4. The method of claim 1, wherein: the fourth passivation layer has a thickness in a range of 5000 angstroms to 7000 angstroms.
5. The method of claim 1, wherein: after the third passivation layer is formed and before the fourth passivation layer is formed, a step of chemically and mechanically polishing the third passivation layer is further included.
6. The method of claim 1, wherein: after the fourth passivation layer is formed, a passivation layer patterning step is further performed to form an opening which sequentially penetrates through the fourth passivation layer, the third passivation layer, the second passivation layer and the first passivation layer from top to bottom, and a preset area of the top metal connecting line layer is exposed at the bottom of the opening.
7. The method of claim 6, wherein: the step of forming a bonding pad on the fourth passivation layer is further included, and the bonding pad is electrically connected with the top metal connecting line layer through the opening.
8. The method of claim 1, wherein: the memory cell includes a P-channel control gate transistor and a P-channel select gate transistor connected in series.
9. The method of claim 8, wherein: the control grid transistor and the selection grid transistor respectively comprise a tunneling dielectric layer, a floating grid layer, an isolation layer and a logic layer which are sequentially stacked from bottom to top.
10. A flash memory structure, comprising:
a semiconductor layer having a memory cell therein;
the interconnection layer is positioned on the semiconductor layer and electrically connected with the storage unit, the interconnection layer comprises at least one dielectric layer and a plurality of metal connecting line layers which are stacked, adjacent metal connecting line layers are connected through a metal plug, and the top surface of the interconnection layer is exposed out of the top metal connecting line layer;
the passivation layer is positioned on the interconnection layer and comprises a first passivation layer, a second passivation layer, a third passivation layer and a fourth passivation layer which are sequentially stacked from bottom to top, wherein the fourth passivation layer comprises a silicon nitride layer, and the material of the first passivation layer is different from that of the fourth passivation layer;
the flash memory structure is manufactured by the method for manufacturing a flash memory structure according to any one of claims 1 to 9.
CN202210659132.XA 2022-06-13 2022-06-13 Flash memory structure and manufacturing method thereof Active CN114758955B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210659132.XA CN114758955B (en) 2022-06-13 2022-06-13 Flash memory structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210659132.XA CN114758955B (en) 2022-06-13 2022-06-13 Flash memory structure and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN114758955A true CN114758955A (en) 2022-07-15
CN114758955B CN114758955B (en) 2022-09-02

Family

ID=82336386

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210659132.XA Active CN114758955B (en) 2022-06-13 2022-06-13 Flash memory structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN114758955B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116209268A (en) * 2023-05-04 2023-06-02 粤芯半导体技术股份有限公司 Semiconductor Flash structure and preparation method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040094793A1 (en) * 2002-11-15 2004-05-20 Mitsuhiro Noguchi Semiconductor memory device
US20040140510A1 (en) * 2002-11-06 2004-07-22 Kabushiki Kaisha Toshiba Semiconductor memory device having a gate insulation film and a manufacturing method thereof
US20090035906A1 (en) * 2007-08-02 2009-02-05 Samsung Electronics Co., Ltd. Method of manufacturing a non-volatile semiconductor device
CN101983423A (en) * 2008-03-31 2011-03-02 富士通半导体股份有限公司 Semiconductor device
US20180130665A1 (en) * 2016-11-07 2018-05-10 Samsung Electronics Co., Ltd. Method of fabricating a semiconductor device
CN110034122A (en) * 2017-11-29 2019-07-19 台湾积体电路制造股份有限公司 Bonding pad structure and its manufacturing method in semiconductor devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040140510A1 (en) * 2002-11-06 2004-07-22 Kabushiki Kaisha Toshiba Semiconductor memory device having a gate insulation film and a manufacturing method thereof
US20040094793A1 (en) * 2002-11-15 2004-05-20 Mitsuhiro Noguchi Semiconductor memory device
US20090035906A1 (en) * 2007-08-02 2009-02-05 Samsung Electronics Co., Ltd. Method of manufacturing a non-volatile semiconductor device
CN101983423A (en) * 2008-03-31 2011-03-02 富士通半导体股份有限公司 Semiconductor device
US20180130665A1 (en) * 2016-11-07 2018-05-10 Samsung Electronics Co., Ltd. Method of fabricating a semiconductor device
CN110034122A (en) * 2017-11-29 2019-07-19 台湾积体电路制造股份有限公司 Bonding pad structure and its manufacturing method in semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116209268A (en) * 2023-05-04 2023-06-02 粤芯半导体技术股份有限公司 Semiconductor Flash structure and preparation method thereof

Also Published As

Publication number Publication date
CN114758955B (en) 2022-09-02

Similar Documents

Publication Publication Date Title
US11195857B2 (en) Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
US11201107B2 (en) Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
US11195781B2 (en) Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
US11355486B2 (en) Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
US11508711B2 (en) Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
US9412752B1 (en) Reference line and bit line structure for 3D memory
US8486791B2 (en) Mufti-layer single crystal 3D stackable memory
CN109192734B (en) 3D memory device
US11676954B2 (en) Bonded three-dimensional memory devices with backside source power supply mesh and methods of making the same
US7312498B2 (en) Nonvolatile semiconductor memory cell and method of manufacturing the same
JP2002280463A (en) Semiconductor device and its fabricating method
JP2006060138A (en) Semiconductor integrated circuit device
CN110993607B (en) Memory device with barrier structure and preparation method thereof
US6975019B2 (en) Semiconductor memory device having a multi-layered interlayer insulation consisting of deuterium and nitride
CN114758955B (en) Flash memory structure and manufacturing method thereof
CN105990359A (en) Separating gate type flash memory device and preparation method thereof
US6794250B2 (en) Vertical split gate flash memory cell and method for fabricating the same
KR100888202B1 (en) Method for manufacturing a semiconductor device
JP2866390B2 (en) Method for manufacturing semiconductor integrated circuit device
US20060263989A1 (en) Semiconductor device and fabrication method therefor
JP2007005527A (en) Semiconductor device
US20220085061A1 (en) Semiconductor device and method of manufacturing same
US7038304B2 (en) Semiconductor memory device and manufacturing method thereof
US20230139782A1 (en) Three-dimensional memory device and fabrication method for enhanced reliability
JP4625857B2 (en) Semiconductor memory device and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: 510700 No. 28, Fenghuang fifth road, Huangpu District, Guangzhou, Guangdong

Patentee after: Yuexin Semiconductor Technology Co.,Ltd.

Address before: 510700 No. 28, Fenghuang fifth road, Huangpu District, Guangzhou, Guangdong

Patentee before: Guangzhou Yuexin Semiconductor Technology Co.,Ltd.