JP2007005527A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide technology capable of improving reliability of a semiconductor device including a semiconductor element having an insulation gate transistor. <P>SOLUTION: The semiconductor device includes a semiconductor substrate 1, a memory cell MC formed on a principal plane of the substrate 1 and having the insulation gate transistor, an insulation film 14 formed on the memory cell MC, a metallic wire 21 electrically connected with the memory cell MC and formed on the insulation film 14, and an insulation film 22 formed to cover the insulation film 14 and the metallic wire 21. The insulation film 14 is an oxynitride silicon film with a content of nitride in a range of 1-15 atom%. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device including a semiconductor element having an insulated gate transistor.

  A flash memory, which is one of semiconductor devices, is excellent in portability and impact resistance, and can be electrically erased collectively. In recent years, a storage device for small portable information devices such as portable personal computers and digital still cameras. As demand grows rapidly.

  In the AND type flash memory, the assist gate has an isolation function between the memory cells, that is, a function of preventing interference between the memory cells. Therefore, it is not necessary to form an element isolation region in the memory array region. Since a high integration can be achieved by reducing the interval between adjacent memory cells, it is suitable for increasing the capacity.

  In Patent Document 1, in a semiconductor device having an insulating film formed in an upper layer of a semiconductor element, in order to suppress a change in element characteristics over time, an oxide film in which Si (silicon) is excessive is formed as the insulating film, A technique for capturing hydrogen in Si dangling bonds in the oxide film is disclosed.

In Patent Document 2, in a flash memory having a floating gate (floating gate, insulating gate), a silicon oxide film added with nitrogen or Al (aluminum) is added to the upper layer of the memory element in order to improve data retention characteristics. A technique for depositing a silicon oxide film is disclosed.
JP-A-6-132542 JP 2003-297756 A

  The inventor is examining a flash memory including an electrically rewritable nonvolatile memory element, which is one of semiconductor devices. FIG. 7 is a cross-sectional view of an essential part schematically showing a semiconductor device examined by the present inventors. FIG. 8 is a cross-sectional view of an essential part schematically showing the semiconductor device examined by the present inventor along line XX in FIG.

  The flash memory, which is a semiconductor device studied by the present inventors, is an AND type flash memory having a capacity of 4 Gb (gigabit), for example. The memory cell MC of the flash memory is formed on the main surface of a semiconductor substrate (hereinafter simply referred to as a substrate) 1 made of p-type silicon (Si) single crystal. An n-type buried layer 2 is formed inside the substrate 1, and a p-type well 3 is formed above the n-type buried layer 2. The n-type buried layer 2 is formed to electrically separate the p-type well 3 and the substrate 1 of each memory mat and supply a predetermined potential to the p-type well 3 of each memory mat. In the p-type well 3 in the memory mat region, a plurality of memory cells MC are arranged in a matrix along the x direction shown in FIGS. 7 and 8 and the y direction perpendicular thereto.

  The memory cell MC includes a gate insulating film 4 formed on the surface of the p-type well 3, an assist gate 5 formed on the gate insulating film 4, and a floating gate formed on the substrate 1 between adjacent assist gates 5. 7, an insulating film 9 made of, for example, an ONO film (silicon oxide film / silicon nitride film / silicon oxide film) formed on the floating gate 7, and a control gate 10 formed on the insulating film 9. It is constituted by a field effect transistor of the shape. An insulating film 8 made of, for example, a silicon oxide film is formed between the assist gate 5 and the floating gate 7.

  For example, the gate insulating film 4 is made of a silicon oxide film or a silicon oxynitride film having a thickness of about 9 nm. The assist gate 5 is made of an n-type polycrystalline silicon film having a thickness of about 9 nm and a width (gate length) of about 40 nm, and the assist gates 5 of the plurality of memory cells MC adjacent in the y direction are mutually connected. Connected and integrated. The pitch between the assist gates 5 adjacent in the x direction is about 180 nm.

Further, the thickness of the control gate 10 is about 250 nm at the thickest portion (upper part of the insulating film 9). The control gates 10 of the plurality of memory cells MC adjacent to each other in the x direction of the memory mat area are connected to each other to form one word line extending in the x direction. The control gate 10 can also be composed of a polycide film in which a silicide film such as tungsten silicide (WSi _x ) is stacked on an n-type polycrystalline silicon film.

  The insulating film 9 is composed of, for example, a three-layer insulating film in which a silicon oxide film having a thickness of about 6 nm, a silicon nitride film having a thickness of about 10 nm, and a silicon oxide film having a thickness of about 6 nm are stacked in this order. Yes.

  An insulating film 11 made of, for example, silicon oxide is formed on the control gate 10 so as to cover the control gate 10. On the insulating film 11, a metal wiring 21 such as Al (aluminum) is formed. The metal wiring 21 is electrically connected to the assist gate 5 of each memory cell MC through a plug 13 formed in the contact hole 12.

An insulating film 22 made of, for example, a silicon oxide film is formed so as to fill the space between adjacent metal wirings 21 and cover the insulating film 11 and the metal wiring 21. The insulating film 22 made of this silicon oxide film is formed by, for example, HDP-CVD (High Density Plasma-Chemical Vapor Deposition) using TEOS (Tetra-Ethyl-Ortho-Silicate: Si (OC ₂ H ₅ ) ₄ ) gas. For example, it is formed at a film forming temperature of about 300 ° C. to 400 ° C. by a plasma CVD method.

  In addition, an insulating film 23 is formed on the insulating film 22 in order to flatten the steps of the insulating film 22 caused by the metal wiring 21. The insulating film 23 is formed at a temperature of, for example, about 300 ° C. to 400 ° C. by, for example, a P-CVD (Plasma-Chemical Vapor Deposition) method using TEOS gas in the same manner as the insulating film 22 is formed. Formed at temperature.

An n ⁺ type diffusion layer 15 is formed in the p type well 3 at both ends in the y direction of the memory mat region. Here, in FIG. 8, one n ⁺ -type diffusion layer 15 of both end portions in the y direction of the memory mat region is formed below one end portion of the assist gate 5. Reference numeral 16 denotes an n-type inversion layer formed on the surface (channel region) of the p-type well 3 below when a positive voltage is applied to the assist gate 5.

  Here, in the semiconductor device studied by the present inventors, the field effect transistor constituting the memory cell MC does not have a source and a drain when not operating. However, when a positive voltage is applied to the assist gate 5 during the operation of the memory cell MC, the n-type inversion layer 16 formed on the surface (channel region) of the p-type well 3 below the assist gate 5 becomes a source or drain. Function as. The inversion layer 16 is formed along the assist gate 5 extending in the y direction and functions as a bit line. That is, the inversion layer 16 constitutes a local source line and a local data line that connect the source region and the drain region of the memory cell MC.

  Thus, since the inversion layer 16 formed below the assist gate 5 is used as a bit line during the operation of the memory cell MC, it is not necessary to secure a bit line formation region in the memory mat region. High integration can be achieved by reducing the interval between MCs.

  Although not shown, in the flash memory according to the present embodiment, an element isolation region is formed around the memory mat region, that is, between adjacent memory mat regions. This element isolation region is constituted by a known element isolation groove called STI (Shallow Trench Isolation) or SGI (Shallow Groove Isolation) in which a silicon oxide film is buried inside a groove formed in the substrate 1. A plurality of memory mat areas configured as described above are formed on the substrate 1, and a memory array of an AND flash memory having a capacity of 4 Gb (gigabit) is configured by the plurality of memory mat areas. Yes. Peripheral circuits (column decoder, row decoder, column latch circuit, well control circuit, booster circuit, booster clock circuit, voltage clamp circuit, etc.) for driving the memory cells MC in each memory mat area are formed around the memory array. However, their illustration is omitted.

  When data is written to the selected memory cell, a positive high voltage is applied to the word line and a positive low voltage is applied to the assist gate. At this time, a positive voltage is applied to the local data line, and the source region and the substrate are held at 0V. As a result, a channel is formed in the substrate under the assist gate, and hot electrons generated in the channel at the end of the floating gate on the source region side are injected into the floating gate.

  When erasing data, a negative high voltage is applied to the word line, and the assist gate, the source region, the drain region, and the substrate are each held at 0V. As a result, a Fowler-Nordheim tunnel current flows from the floating gate to the substrate, and electrons accumulated in the floating gate are released.

  A problem that the charge retention characteristic (retention characteristic) is deteriorated when, for example, 100,000 to 1,000,000 continuous write / erase operations are performed on the flash memory which is the semiconductor device studied by the present inventors. Occurred.

One possible cause of the deterioration of the charge retention characteristic is that the threshold voltage Vth of the memory cell MC fluctuates (shifts). That is, the threshold voltage Vth of the memory cell MC varies because hydrogen (H ₂ or H ⁺ ) contained in the insulating film 22 and the insulating film 23 passes through the insulating film 11, the insulating film 9, or the insulating film 8. It can be considered that the threshold voltage Vth fluctuates due to diffusion to the memory cell MC and is trapped by defects in the gate insulating film 4 in the memory cell MC.

Therefore, when forming the insulating film 22 and the insulating film 23, it is possible to adjust the film-forming conditions by P-CVD method or HDP-CVD method so that hydrogen may not be contained. Further, in order to prevent diffusion of hydrogen (H ₂ or H ⁺ ) contained in the insulating film 22 and the insulating film 23 to the memory cell MC, the upper layer of the memory cell MC is an insulating layer containing many defects such as Si dangling bonds. It is considered effective to cover with a film to prevent hydrogen (H ₂ or H ⁺ ) entering the memory cell MC and to suppress the fluctuation of the threshold voltage Vth.

Here, as described in Patent Document 1, a silicon oxide film (Si-excess oxide film) containing Si in excess of the stoichiometric composition (O / Si = 2.0) is used as the insulating film 22. When used, the effect of suppressing fluctuation of the threshold Vth of the floating gate could not be obtained. Further, in the Si-excess oxide film formed by the HDP-CVD method using the SiH ₄ gas and the O ₂ gas, the threshold Vth of the memory cell MC is not suppressed, but the threshold Vth fluctuation is worsened. did.

  Further, as described in Patent Document 2, when a silicon oxide film to which nitrogen is added to capture hydrogen is used as the insulating film 22, it is considered effective for suppressing hydrogen diffusion. . However, when the amount of nitrogen added is large, the characteristics of the silicon nitride film appear, and it is considered that the silicon oxide film has problems such as a decrease in coverage and an increase in capacitance between lines due to an increase in dielectric constant. On the other hand, if the amount of nitrogen added is small, the characteristics of the silicon oxide film appear, and it is considered that hydrogen diffuses into the memory cell MC as described above.

  An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device including a semiconductor element having an insulated gate transistor.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to the present invention includes a semiconductor substrate, a semiconductor element formed on the main surface of the semiconductor substrate and having an insulated gate transistor, a first insulating film formed on the semiconductor element, and the semiconductor element and the electric device. And a metal wiring formed on the first insulating film and a second insulating film formed so as to cover the first insulating film and the metal wiring. The first insulating film is a silicon oxynitride film having a nitrogen content in the range of 1 atom% to 15 atom%.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The reliability of a semiconductor device including a semiconductor element having an insulated gate transistor can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
In Embodiment 1 of the present invention, a flash memory (semiconductor device) including an electrically rewritable nonvolatile memory element (a semiconductor element having an insulated gate transistor) will be described with reference to FIGS.

  FIG. 1 is a main part sectional view schematically showing the semiconductor device according to the first embodiment. FIG. 2 is a main part sectional view schematically showing the semiconductor device according to the first embodiment taken along line XX of FIG. The structure of the flash memory according to the first embodiment will be described below.

  As shown in FIGS. 1 and 2, the flash memory is an AND flash memory having a capacity of 4 Gb (gigabit), for example. The memory cell MC of the flash memory is formed on the main surface of a semiconductor substrate (hereinafter simply referred to as a substrate) 1 made of p-type silicon (Si) single crystal. An n-type buried layer 2 is formed inside the substrate 1, and a p-type well 3 is formed above the n-type buried layer 2. The n-type buried layer 2 is formed to electrically separate the p-type well 3 and the substrate 1 of each memory mat and supply a predetermined potential to the p-type well 3 of each memory mat. In the p-type well 3 in the memory mat region, a plurality of memory cells MC are arranged in a matrix along the x direction shown in FIGS. 1 and 2 and the y direction perpendicular thereto.

Each of the memory cells MC is formed on the substrate 1 between the gate insulating film 4 formed on the surface of the p-type well 3, the assist gate 5 formed on the gate insulating film 4, and the adjacent assist gate 5. It has a floating gate 7, an insulating film 9 made of, for example, an ONO film (silicon oxide film / silicon nitride film / silicon oxide film) formed on the floating gate 7, and a control gate 10 formed on the insulating film 9. It is composed of a gate insulation type transistor. Further, an insulating film (not shown) made of, for example, a silicon nitride (SiN) film is formed on the assist gate 5. An insulating film 8 made of, for example, a silicon oxide (SiO ₂ ) film is formed between the assist gate 5 and the floating gate 7.

  An insulating film 11 made of, for example, silicon oxide is formed on the control gate 10 so as to cover the control gate 10. On this insulating film 11, for example, an insulating film 14 made of a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed.

Here, the insulating film 14 is a silicon oxynitride film formed so that the nitrogen content is in the range of 1 atom% to 15 atom%, and the refractive index of the insulating film 14 is 1.45 to 1 Within the range of .70. The insulating film 14 made of this silicon oxynitride film uses SiH ₄ gas or TEOS (Tetra-Ethyl-Ortho-Silicate: Si (OC ₂ H ₅ ) ₄ ) gas and a gas mainly containing N ₂ O. It is formed by the P-CVD (Plasma-Chemical Vapor Deposition) method or HDP-CVD (High Density Plasma-Chemical Vapor Deposition) method, and has Si dangling bonds. For example, when hydrogen is diffused in the insulating film 14, hydrogen is captured by Si dangling bonds. In this embodiment, the case where the thickness of the silicon oxynitride film is approximately 200 nm is described. However, when the thickness of the silicon oxynitride film is 100 nm or more, hydrogen is effectively captured.

A metal wiring 21 is formed on the insulating film 14. The metal wiring 21 is electrically connected to the assist gate 5 of each memory cell MC through a plug 13 formed in the contact hole 12. Here, the metal wiring 21, titanium nitride (TiN), titanium tungsten (TiW), tungsten (W), and a barrier metal such as tungsten silicide _{(WSi 2), Al-Si} , Al-Si-Cu, Al A wiring having a structure combined with an aluminum alloy film such as Cu is used.

An insulating film 22 made of, for example, a silicon oxide film is formed so as to bury between adjacent metal wirings 21 and cover the insulating film 14 and the metal wiring 21. The insulating film 22 made of the silicon oxide film is formed, for example, at 250 ° C. to 450 ° C. by a P-CVD method or an HDP-CVD method using silane (SiH ₄ ) and nitrous oxide (N ₂ O) as main component gases. The film is formed at a film forming temperature of about ° C.

In addition, an insulating film 23 is formed on the insulating film 22 in order to flatten the steps of the insulating film 22 caused by the metal wiring 21. The insulating film 23 is formed, for example, at 250 ° C. to 250 ° C. by a P-CVD method using silane (SiH ₄ ) and nitrous oxide (N ₂ O) as main component gases, as in the case of forming the insulating film 22. It is formed at a film forming temperature of about 450 ° C.

An n ⁺ type diffusion layer 15 is formed in the p type well 3 at both ends in the y direction of the memory mat region. In FIG. 2, one n ⁺ -type diffusion layer 15 of both end portions in the y direction of the memory mat region is formed below one end portion of the assist gate 5. Reference numeral 16 denotes an n-type inversion layer formed on the surface (channel region) of the p-type well 3 below when a positive voltage is applied to the assist gate 5.

  Here, in the flash memory according to the first embodiment, the field effect transistor constituting the memory cell MC has no source and drain when not in operation. However, when a positive voltage is applied to the assist gate 5 during the operation of the memory cell MC, the n-type inversion layer 16 formed on the surface (channel region) of the p-type well 3 below the assist gate 5 becomes a source or drain. Function as. The inversion layer 16 is formed along the assist gate 5 extending in the y direction and functions as a bit line. That is, a local source line and a local data line connecting the source region and the drain region of the memory cell MC are configured.

  Thus, since the inversion layer 16 formed below the assist gate 5 is used as a bit line during the operation of the memory cell MC, it is not necessary to secure a bit line formation region in the memory mat region. High integration can be achieved by reducing the interval between MCs.

  Although not shown, in the flash memory according to the present embodiment, an element isolation region is formed around the memory mat region, that is, between adjacent memory mat regions. This element isolation region is constituted by a known element isolation groove called STI (Shallow Trench Isolation) or SGI (Shallow Groove Isolation) in which a silicon oxide film is buried inside a groove formed in the substrate 1. A plurality of memory mat areas configured as described above are formed on the substrate 1, and a memory array of an AND flash memory having a capacity of 4 Gb (gigabit) is configured by the plurality of memory mat areas. Yes. Peripheral circuits (column decoder, row decoder, column latch circuit, well control circuit, booster circuit, booster clock circuit, voltage clamp circuit, etc.) for driving the memory cells MC in each memory mat area are formed around the memory array. However, their illustration is omitted.

  When data is written to the selected memory cell, a positive high voltage is applied to the word line and a positive low voltage is applied to the assist gate. At this time, a positive voltage is applied to the local data line, and the source region and the substrate are held at 0V. As a result, a channel is formed in the substrate under the assist gate, and hot electrons generated in the channel at the end of the floating gate on the source region side are injected into the floating gate.

  When erasing data, a negative high voltage is applied to the word line, and the assist gate, source region, drain region, and substrate are each held at 0V. As a result, a Fowler-Nordheim tunnel current flows from the floating gate to the substrate, and electrons accumulated in the floating gate are released.

When such a flash memory is continuously written / erased 100,000 times to 1 million times, for example, the charge retention characteristic (retention characteristic) can be maintained. This is presumably because deterioration with time of the threshold voltage Vth during writing / erasing of the memory cell MC could be suppressed. That is, hydrogen (H ₂ or H ⁺ ) is contained by forming a silicon oxynitride film having a nitrogen content in the range of 1 atm% to 15 atm% in the insulating film 14 in the memory cell MC and the metal wiring layer portion. Hydrogen entering from the insulating film 22 and the insulating film 23 can be captured and fluctuations in the threshold voltage Vth can be suppressed.

  In addition, since the charge retention characteristic (retention characteristic) can be maintained, the reliability of the flash memory which is a semiconductor device including a semiconductor element having an insulated gate transistor can be improved.

  As described above, the insulating film 14 (first insulating film) made of, for example, a silicon oxynitride film having a nitrogen content in the range of 1 atom% to 15 atom% on the memory cell MC made of a nonvolatile memory element (semiconductor element). To capture hydrogen entering from the upper layer of the first insulating film, for example, the insulating film 22 (second insulating film) made of a silicon oxide film containing hydrogen, and to diffuse the hydrogen into the memory cell MC. Can be prevented. Therefore, it is possible to suppress the deterioration with time of the threshold value Vth at the time of writing / erasing the memory cell MC, and it is possible to improve the lifetime of the flash memory (semiconductor device) including the nonvolatile memory element.

Here, the reason why the insulating film 14 made of a silicon oxynitride film having a nitrogen content in the range of 1 atom% to 15 atom% captures hydrogen is that the local O—Si— formed in the silicon oxynitride film. This is probably because the Si dangling bond of the N network is the easiest to capture and release hydrogen. For example, Si dangling bonds composed of a network of O—Si—O or N—Si—Ni are easy to be released into the film because they have low Si—H bond energy even if they are terminated by capturing hydrogen. Easy to diffuse. Further, the SiH ₄ (or TEOS) / O ₂ -based silicon oxide film or SiH ₄ / NH ₃ -based silicon nitride film formed by the P-CVD method has a large amount of hydrogen and a large amount of degassing. It is supported from that.

  3 and 4 are main part cross-sectional views schematically showing the semiconductor device during the manufacturing process according to the first embodiment of the present invention. 3 and 4 are main part cross-sectional views schematically showing the semiconductor device in the same direction as FIG. A method for manufacturing the flash memory according to the first embodiment will be described below. Since the point of the present invention is after the formation of the memory cell MC composed of a nonvolatile memory element that is a semiconductor element, the description will be made after the memory cell MC is formed.

  As shown in FIG. 3, a plurality of memory cells MC, which are nonvolatile memory elements, which are semiconductor elements having an insulated gate transistor, are formed on the main surface of the substrate 1 using a known technique. Next, an insulating film 11 made of, for example, a silicon oxide film is formed so as to fill between adjacent memory cells MC. As the insulating film 11 made of this silicon oxide film, for example, a PSG (Phospho Silicate Glass) or BPSG (Boro Phospho Silicate Glass) film to which phosphorus (P) or boron (B) is added is used by an atmospheric pressure CVD method or a low pressure CVD method. After the deposition, a heat treatment of, for example, about 800 ° C. to 900 ° C. is performed to form a flat insulating film.

  Subsequently, as shown in FIG. 4, after forming an insulating film 14 made of, for example, a silicon oxynitride film on the insulating film 11, a contact hole 12 exposing one end portion of the assist gate 5 of each memory cell MC is formed. To do.

Here, the insulating film 14 is a silicon oxynitride film formed so that the nitrogen content is in the range of 1 atom% to 15 atom%, and the refractive index of the insulating film 14 is 1.45 to 1 Within the range of .70. The insulating film 14 made of the silicon oxynitride film is formed by a P-CVD method or an HDP-CVD method using SiH ₄ gas or TEOS gas and a gas containing N ₂ O as a main component, and Si dangling bonds Have

  Note that the silicon oxide film and the silicon nitride film or the silicon oxynitride film are alternately deposited to form the insulating film 14 made of a silicon oxynitride film having a nitrogen content in the range of 1 atom% to 15 atom%. good.

  Next, for example, tungsten (W) is buried in the contact hole 12 to form a plug 13, and then a metal film is formed on the plug 13 and the insulating film 14, and a metal electrically connected to the assist gate 5 by patterning. A wiring 21 is formed.

The metal wires 21, titanium nitride (TiN), titanium tungsten (TiW), tungsten (W), and a barrier metal such as tungsten silicide _{(WSi 2), Al-Si} , Al-Si-Cu, Al-Cu , etc. A wiring having a structure combined with an aluminum alloy film is used. Further, the pitch between the adjacent metal wirings 21 is narrowed as the memory cell MC is miniaturized.

Next, in order to reduce defects (interface states) in the Si—SiO ₂ interface and the gate insulating film 4, normally, hydrogen (H ₂ ) and an inert gas such as nitrogen (N ₂ ) or argon (Ar) In the mixed gas atmosphere, for example, low temperature heat treatment is performed at 400 ° C. to 450 ° C. for about 10 minutes to 60 minutes. At this time, hydrogen in the atmosphere diffuses to the vicinity of the memory cell MC, and defects in this portion are reduced by terminating defects in the Si—SiO ₂ interface and the gate insulating film 4 with hydrogen.

  Subsequently, after forming an insulating film 22 made of, for example, a silicon oxide film so as to cover the metal wiring 21 and the insulating film 14, an insulating film 23 made of, for example, a silicon oxide film is formed on the insulating film 22, and FIG. The semiconductor device according to the first embodiment of the present invention shown in FIG.

  The insulating film 22 made of the silicon oxide film is formed by, for example, HDP-CVD (High Density Plasma-Chemical Vapor Deposition) so as to be embedded between the metal wirings 21 having a narrow pitch. For example, it is formed at a film forming temperature of about 300 ° C. to 400 ° C. The HDP-CVD method can form a film at a low temperature and can prevent the metal wiring 21 from being thermally damaged when the insulating film 22 is formed. In addition, the HDP-CVD method can easily adjust the composition ratio of oxygen (O) and silicon (Si) when forming a silicon oxide film, and the addition amount can be increased when an additive is added to the silicon oxide film. It can be adjusted easily.

  The insulating film 23 made of the silicon oxide film is formed at a film formation temperature of, for example, about 300 ° C. to 400 ° C., for example, by P-CVD using TEOS gas.

  Thus, it is considered that the insulating film 22 and the insulating film 23 made of the silicon oxide film formed by the P-CVD method or the HDP-CVD method contain hydrogen. As described above, in the semiconductor device studied by the present inventors, it was considered that this hydrogen diffuses to the memory cell MC and causes the threshold value Vth to fluctuate. However, in the semiconductor device according to the first embodiment of the present invention, a silicon oxynitride film having a nitrogen content in the range of 1 atom% to 15 atom% is formed between the memory cell MC and the insulating film 22 and the insulating film 23. Since the insulating film 14 is formed, the hydrogen can be prevented from being captured by the insulating film 14 and diffusing up to the memory cell MC.

(Embodiment 2)
In the first embodiment, the case where a nonvolatile memory element is applied as the semiconductor element having an insulated gate transistor has been described. In the second embodiment, a case where a MOS (Metal Oxide Semiconductor) transistor is applied is described. 5 will be described.

  FIG. 5 is a fragmentary cross-sectional view schematically showing a semiconductor device including the MOS transistor Q according to the second embodiment of the present invention.

  As shown in FIG. 5, a MOS transistor Q, which is a semiconductor element having an insulated gate transistor, is formed on the main surface of a semiconductor substrate (hereinafter simply referred to as a substrate) 1 made of p-type silicon (Si) single crystal. Yes.

  The MOS transistor Q includes a gate insulating film 31 made of, for example, a silicon oxide film formed on the main surface of the substrate 1, a gate electrode 32 made of, for example, a polysilicon film, formed on the gate insulating film 31, and a gate. It has a silicide film 33 formed on the electrode 32 and a semiconductor layer 34 formed in the vicinity of the main surface of the substrate 1 and serving as a source region or a drain region. A cap portion 35 made of, for example, a silicon nitride film is formed on the silicide film 33, and a side wall 36 is formed on the side wall of the gate electrode 32.

  Further, a well-known element isolation groove 37 called STI (Shallow Trench Isolation) in which a silicon oxide film is embedded in a groove formed in the substrate 1 is formed.

  Further, similarly to the semiconductor device of the first embodiment (see FIG. 2), an insulating film 11 made of, for example, silicon oxide is formed so as to cover the MOS transistor Q. On this insulating film 11, for example, an insulating film 14 made of a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed.

Here, the insulating film 14 is a silicon oxynitride film formed so that the nitrogen content is in the range of 1 atom% to 15 atom%, and the refractive index of the insulating film 14 is 1.45 to 1 Within the range of .70. The insulating film 14 made of the silicon oxynitride film is formed by a plasma CVD method or a high density plasma CVD method using SiH ₄ gas or TEOS gas and a gas containing N ₂ O as a main component, and Si dangling bonds. Have For example, when hydrogen is diffused in the insulating film 14, hydrogen is captured by Si dangling bonds.

A metal wiring 21 is formed on the insulating film 14. The metal wiring 21 is electrically connected to the semiconductor layer 34 in the source region or drain region of the MOS transistor Q through the plug 13 formed in the contact hole 12. Here, the metal wiring 21, titanium nitride (TiN), titanium tungsten (TiW), tungsten (W), and a barrier metal such as tungsten silicide _{(WSi 2), Al-Si} , Al-Si-Cu, Al A wiring having a structure combined with an aluminum alloy film such as Cu is used.

An insulating film 22 made of, for example, a silicon oxide film is formed so as to bury between adjacent metal wirings 21 and cover the insulating film 14 and the metal wiring 21. The insulating film 22 made of the silicon oxide film is formed, for example, at 250 ° C. to 450 ° C. by a P-CVD method or an HDP-CVD method using silane (SiH ₄ ) and nitrous oxide (N ₂ O) as main component gases. The film is formed at a film forming temperature of about ° C.

In addition, an insulating film 23 is formed on the insulating film 22 in order to flatten the steps of the insulating film 22 caused by the metal wiring 21. The insulating film 23 is formed, for example, at 250 ° C. to 250 ° C. by a P-CVD method using silane (SiH ₄ ) and nitrous oxide (N ₂ O) as main component gases, as in the case of forming the insulating film 22. It is formed at a film forming temperature of about 450 ° C.

  Thus, by providing the MOS transistor Q (semiconductor element) with the insulating film 14 (first insulating film) made of a silicon oxynitride film having a nitrogen content in the range of 1 atom% to 15 atom%, for example, the first insulation is achieved. Hydrogen entering from the upper layer of the film, for example, the insulating film 22 (second insulating film) made of a silicon oxide film containing hydrogen can be captured, and diffusion of hydrogen into the memory cell MC can be prevented.

(Embodiment 3)
In the second embodiment, the case where the insulating film 11 made of a silicon oxide film and the insulating film 14 made of a silicon oxynitride film are formed on the MOS transistor Q as shown in the semiconductor device of FIG. In the third embodiment, the case where the insulating film 11 is formed of a silicon oxynitride film will be described with reference to FIG. The second embodiment is the same as the second embodiment except that a silicon oxynitride film is used as the insulating film 11.

  FIG. 6 is a cross-sectional view schematically showing a main part of a semiconductor device including the MOS transistor Q according to the second embodiment of the present invention.

As shown in FIG. 6, the insulating film 11 is a silicon oxynitride film formed so that the nitrogen content is in the range of 1 atom% to 15 atom%, and the refractive index of the insulating film 11 is 1 Within the range of .45 to 1.70. The insulating film 11 made of this silicon oxynitride film uses SiH ₄ gas or TEOS (Tetra-Ethyl-Ortho-Silicate: Si (OC ₂ H ₅ ) ₄ ) gas and a gas mainly containing N ₂ O. Formed by the conventional plasma CVD method or high-density plasma CVD method, and has Si dangling bonds. For example, when hydrogen is diffused in the insulating film 11, hydrogen is captured by Si dangling bonds.

  Thus, by providing the MOS transistor Q (semiconductor element) with the insulating film 11 (first insulating film) made of, for example, a silicon oxynitride film having a nitrogen content in the range of 1 atom% to 15 atom%, the first insulation is achieved. Hydrogen entering from the upper layer of the film, for example, the insulating film 22 (second insulating film) made of a silicon oxide film containing hydrogen can be captured, and diffusion of hydrogen into the memory cell MC can be prevented.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above embodiment, the case where a nonvolatile memory element or a MOS transistor is applied as the semiconductor element formed on the main surface of the semiconductor substrate has been described. However, the present invention can be applied to a semiconductor element having an insulated gate transistor. For example, an IGBT (Insulated Gate Bipolar Transistor), SRAM (Static Random Access Memory) element, DRAM (Dynamic Random Access Memory) element, EPROM (Erasable Programmable Read Only Memory), CMOS (Complementary Metal Oxide Semiconductor) logic circuit element, Also, it can be applied to a mixed LSI (Large Scale Integration).

  The present invention is widely used in the manufacturing industry for manufacturing semiconductor devices.

1 is a main part sectional view schematically showing a semiconductor device in a first embodiment of the present invention; FIG. 2 is a main part sectional view schematically showing the semiconductor device according to the first embodiment, taken along line XX in FIG. 1; It is principal part sectional drawing which shows typically the semiconductor device in the manufacturing process in Embodiment 1 of this invention. FIG. 4 is a main part cross-sectional view schematically showing the semiconductor device in the manufacturing process following FIG. 3; It is principal part sectional drawing which shows typically the semiconductor device in Embodiment 2 of this invention. It is principal part sectional drawing which shows typically the semiconductor device in Embodiment 3 of this invention. It is principal part sectional drawing which shows typically the semiconductor device which this inventor examined. FIG. 8 is a main part cross-sectional view schematically showing the semiconductor device examined by the inventors of the XX line in FIG. 7;

Explanation of symbols

1 semiconductor substrate 2 n-type buried layer 3 p-type well 4 gate insulating film 5 assist gate 7 floating gate 8 insulating film 9 insulating film 10 control gate 11 insulating film 12 contact hole 13 plug 14 insulating film 15 n ⁺ type diffusion layer 16 inversion Layer 21 Metal wiring 22 Insulating film 23 Insulating film 31 Gate insulating film 32 Gate electrode 33 Silicide film 34 Semiconductor layer 35 Cap portion 36 Side wall 37 Element isolation trench MC Memory cell Q MOS transistor

Claims (4)

A semiconductor substrate;
A semiconductor element formed on the main surface of the semiconductor substrate and having an insulated gate transistor;
A first insulating film formed on the semiconductor element;
A metal wiring electrically connected to the semiconductor element and formed on the first insulating film;
A semiconductor device having a second insulating film formed to cover the first insulating film and the metal wiring,
The semiconductor device according to claim 1, wherein the first insulating film is a silicon oxynitride film having a nitrogen content in a range of 1 atom% to 15 atom%. The semiconductor device according to claim 1,
A refractive index of the first insulating film is in a range of 1.45 to 1.70;
A semiconductor device, wherein the first insulating film has a thickness of 100 nm or more. The semiconductor device according to claim 1,
The first insulating film is
Formed by a plasma CVD method or a high density plasma CVD method using a SiH ₄ gas or a TEOS gas and a gas mainly containing N ₂ O;
A semiconductor device comprising a Si dangling bond that captures hydrogen contained in the second insulating film. The semiconductor device according to claim 1,
The semiconductor device, wherein the semiconductor element is an electrically rewritable nonvolatile memory element.

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