JP4625857B2 - Semiconductor memory device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device having an element isolation region and a transistor and a manufacturing method thereof, and more particularly to a semiconductor device having a contact formed in the vicinity of the element isolation region and the transistor and a manufacturing method thereof.

Conventionally, as a semiconductor memory, for example, an EEPROM that electrically writes and erases data is used.
OM (Electrically Erasable Programmable Re)
ad-Only Memory) is known. In this EEPROM, memory cells are arranged at intersections between row lines and column lines that intersect each other, thereby forming a memory cell array. In general, a MOS transistor having a stacked gate structure in which a floating gate and a control gate are stacked is used for the memory cell.

A NAND type EEPROM as shown in FIG. 17 is known as a method suitable for a large capacity memory among the EEPROMs. Here, FIG. 15 is a view showing a cross section on the “IJ” line of FIG. 17, and FIG. 16 is a view showing a cross section on the “KL” line of FIG.

As shown in FIG. 15, in the NAND type EEPROM memory cell array, a plurality of memory cell transistors are connected in series, and a drain side select gate transistor 5 is provided on one side thereof.
3. The source side select gate transistor 54 is connected to the other side. A well 51 is provided in a part on the semiconductor substrate 50, and a striped element region 55 is formed therein.
Each element region 55 is separated by an element isolation region 56. On the element region 55, a plurality of cell transistors having a stacked gate structure are arranged in a matrix.

Each memory cell includes a gate electrode portion 52 provided on a gate insulating film 57 on the element region 55.
The gate electrode portion 52 is formed by stacking a floating gate electrode 58 serving as a charge storage layer, an inter-gate insulating film 59, a control gate electrode 60, and a gate mask material 70. Further, the control gate electrode 60 is shared with other gate electrodes in the row line direction,
A word line 61 is formed.

The source and drain of each memory cell are connected in series with each other through a diffusion layer region 62 provided on the element region. A plurality of memory cells are connected in series to form one NAND cell (
Memory cell unit) is formed.

A drain side select gate transistor 53 and a source side select gate transistor 54 are connected to both ends of each NAND cell in the bit line direction. Each select gate transistor has a gate electrode provided on the gate insulating film 57, and is connected to the NAND cell via a diffusion layer region 62. The select gate transistor can supply a potential to the floating gate electrode, functions like a general MOSFET, and has a stacked gate structure similar to that of a memory cell transistor.

A bit line contact diffusion layer 62 is provided in the element region 55 of the drain side select gate transistor opposite to the NAND cell. This bit line contact diffusion layer 6
2 is connected to a bit line contact 63. The bit line contact 63 is connected to the bit line 64.

A post oxide film 65 is formed on the surface of each gate 52, 53, 54. Thereafter, a silicon nitride film 67 is formed on the surface of the oxide film 65, on the diffusion layer 62, on the drain contact diffusion layer 62, and on the source diffusion layer 66 on the side opposite to the memory cell of the source side selection gate 54. . An interlayer insulating film 68 is formed on the surface of the silicon nitride film 67, and the upper surface thereof is flattened.

Here, the bit line contact 63 is formed through the gate insulating film 57, the silicon nitride film 67, and the interlayer insulating film 68, and the bit line 64 is formed on the interlayer insulating film 68. The bit lines are provided separately between NAND cells adjacent in the column direction.

A source diffusion layer 66 formed on the opposite side of the source side select gate transistor from the NAND cell is a source line. The source line has a contact connected to a portion where one end of the floating gate is extended, and is provided in an upper layer than the gate electrode. The source lines are connected by NAND cells adjacent in the column direction.

Next, in the cross section shown in FIG. 16, a plurality of element isolation regions 56 are formed so as to divide the upper surface of the element region 55 provided in the well 51 on the semiconductor substrate 50. A bit line contact 63 is connected to the entire surface of the element region 55 sandwiched between the element isolation regions 56. A silicon nitride film 67 is formed on the element isolation region 56, and an interlayer insulating film 68 is formed thereon. A bit line contact 68 is formed through the interlayer insulating film 68 and the silicon nitride film 67. A bit line wiring 64 is formed on the bit line contact 68.

Next, a method of manufacturing the conventional semiconductor device shown in FIGS. 15 to 17 will be described with reference to FIGS.

First, as shown in FIG. 18, an element isolation region (on a semiconductor substrate 50 made of silicon)
A device region 55 surrounded by an unillustrated) is formed, and a gate insulating film 57, a floating gate electrode material 58, and a floating gate / control gate insulating film 59 are formed thereon, and the control gate electrode 6 is formed thereon.
0, Gate mask material 70 is deposited. Subsequently, the gate is patterned by photolithography and etched to form a memory cell gate 52 and select gates 53 and 54.

  Next, post-oxidation is performed to form a post-oxide film 65 around the gate electrode having a laminated structure.

  Next, impurities for forming the source / drain diffusion layer are formed by ion implantation.

Next, as shown in FIG. 19, for example, a silicon nitride film 67 having a thickness of about 40 nm is deposited. At this time, the silicon nitride film 67 is formed so as to cover the side wall of the gate electrode.

Further, an interlayer insulating film 68 is deposited, and CMP (Chemical Mechanical) is formed.
The interlayer insulating film 68 is flowed by applying a polishing method or heat treatment, and the interlayer insulating film 68 is made to flow.
And an interlayer insulating film 68 is embedded between the gate electrodes.

Next, as shown in FIG. 20, a contact hole 71 for making contact with the bit line contact diffusion layer 53 adjacent to the drain side select gate 53 is formed in the interlayer insulating film 68, the silicon nitride film 67, and the gate oxide film 57. Form.

Next, a metal wiring is formed after the metal or low-resistance semiconductor is buried in the contact hole 71, thereby completing the semiconductor device as shown in FIG.

As described above, in the conventional semiconductor device, after forming the gate electrode, the silicon nitride film 67 covering the entire surface is formed. The reason why the silicon nitride film 67 is necessary will be described below.

As shown in FIGS. 16 and 17, the bit line contact 63 is designed so that there is almost no margin with respect to the element region 55. That is, the bit line contact 63 is provided to fill the element region 55 to the full width. The bit line contact 63 is larger than the width of the element region 55.
There is a case where the width of is large. This is to reduce the area of the cell array as much as possible.

In such a semiconductor device, it is necessary to prevent the bit line contact from penetrating into the element isolation region even when the contact formation position is on the element isolation region due to misalignment of the mask. . This is because if the bit line contact penetrates the element isolation region, it may cause a junction leakage current in that portion or a decrease in the element isolation breakdown voltage.

In the case of a semiconductor device without a silicon nitride film, the insulating film in the element isolation region 56 is simultaneously etched by etching the interlayer insulating film 68 when opening the bit line contact as shown in FIG. There is a possibility of passing through the separation region 56. In this case, the bit line contact 68 is formed so as to enter the element isolation region 56 by the length of the misalignment M shown in FIG. The portion formed by the bit line contact 68 entering the element isolation region 56 is electrically connected to the element region 55 and is connected except for the source / drain diffusion layer 62, and the transistor characteristics are impaired. End up.

In general, the etching at the time of opening the contact hole 71 is performed to some extent so as to be opened even if there is a process variation, etc. In general, the interlayer insulating film and the insulating film in the element isolation region are formed of a silicon oxide film. Therefore, it is difficult to selectively etch only the interlayer insulating film. Such a state is likely to occur when the width of the element region is close to the width of the bit line contact.

In order to prevent such a phenomenon, the silicon nitride film 67 is used in the conventional semiconductor device as described above. By using this, in the miniaturized semiconductor device, the etching at the time of opening the contact has the selectivity of the silicon oxide film and the silicon nitride film, thereby causing the misalignment M as shown in FIG. However, the etching can be stopped once on the silicon nitride film 67.

After opening a contact hole reaching the silicon nitride film 67 in this way, the etching conditions are switched to etch the silicon nitride film 67, and the conditions are switched to etch the silicon oxide film on the substrate, thereby providing a source / drain. A contact hole 71 on the diffusion layer is completely opened.

By opening the bit line contact hole 71 for making contact with the diffusion layer in this way, it is possible to prevent the element isolation region 56 from being greatly etched. Thus, the silicon nitride film 67 functions as an etching stopper, thereby preventing the contact hole 71 from penetrating the element isolation region 56.

  The conventional semiconductor device as described above has the following problems.

In a conventional semiconductor memory device using a silicon nitride film, a large amount of hydrogen is contained in the silicon nitride film, and when this hydrogen is taken into the silicon oxide film, an Si—H bond is formed at the interface with the silicon substrate. Such structural defects are likely to occur. The Si—H bond has a weaker bond energy than the Si—O bond.

Here, in a nonvolatile semiconductor memory device or the like, during a memory write / erase operation, a strong electric field is applied between the control gate and the channel, a tunnel current is passed through the gate insulating film, and charges are injected into the floating gate. The removal operation is performed. In such an operation, when a tunnel current flows in the vicinity of the gate insulating film, electrical stress is applied.

If there is a film containing a large amount of hydrogen in the vicinity of the gate insulating film, hydrogen is taken into the silicon oxide film and structural defects such as Si—H bonds are likely to occur at the interface with the silicon substrate.

When this structural defect is cut by electrical stress, it acts as a trap for electric charges. When this trap occurs especially in the silicon oxide film that is the gate insulating film or the post-oxide film near the gate insulating film, the transistor This causes deterioration of electrical characteristics such as fluctuations in the threshold voltage and decrease in the breakdown voltage of the silicon oxide film.

In addition, when charges are trapped in the trap of the oxide film that covers the surface of the source / drain diffusion layer, the diffusion layer near the substrate surface is depleted, resulting in an increase in the parasitic resistance of the source / drain, and the transistor on-current May be reduced.

It is generally known that there are many traps for charges in the silicon nitride film. In particular, when charges are trapped in the traps in the silicon nitride film that covers the surface of the source / drain diffusion layer, the diffusion layer near the substrate surface is depleted, resulting in increased parasitic resistance of the source / drain, and turning on the transistor. The current may be reduced.

Further, when electric charges are trapped in the silicon nitride film near the gate insulating film, it causes deterioration of electrical characteristics such as fluctuation of the threshold voltage of the transistor and lowering of the breakdown voltage of the silicon oxide film.

Such a problem becomes particularly prominent when the gate length is smaller than about 0.2 μm. In other words, this becomes conspicuous when the ratio of the silicon oxide film, the post-oxide film, and the silicon nitride film in which traps in the vicinity of the gate insulating film occupy the entire gate is large.

As described above, a silicon nitride film is necessary for etching a contact hole. On the other hand, since the adverse effect of the silicon nitride film is seen on the electrical characteristics, it is possible to simultaneously improve the yield and reliability of the semiconductor device. It was difficult.

  An object of the present invention is to solve the above-described problems of the prior art.

In particular, an object of the present invention is to provide a highly reliable and high yield semiconductor device and a method for manufacturing the same.

A semiconductor substrate and a control gate electrode provided via a first gate insulating film formed on the semiconductor substrate and formed via a charge storage layer and an inter-gate insulating film formed on the charge storage layer. A memory cell transistor group including a plurality of memory cell gates, and a selection gate transistor including a selection gate provided via a second gate insulating film formed on the semiconductor substrate adjacent to the plurality of memory cell gates A first diffusion layer provided in a semiconductor substrate below a side surface opposite to the side adjacent to the memory cell gate of the selection gate, between the plurality of memory cell gates, and between the memory cell gate and the selection gate, A first insulating film formed on the first diffusion layer and not containing nitrogen as a main component, and a second insulating film formed on the first insulating film. An interlayer insulating film formed on the second insulating film and having a different main component from the second insulating film, and through the interlayer insulating film, the second insulating film, and the first insulating film, the first diffusion layer And a density of hydrogen contained in the first insulating film is smaller than a density of hydrogen contained in the second insulating film, and the first insulating film is formed in the memory cell. The thickness between the gates is characterized by being formed thicker than the thickness of the portion of the first diffusion layer in contact with the contact electrode.

According to the present invention, while improving the etching process margin for opening the contact hole, it is possible to prevent the deterioration of the electrical characteristics such as the fluctuation of the threshold voltage of the transistor and the decrease of the breakdown voltage in the gate insulating film. A highly reliable semiconductor device with high yield and a manufacturing method thereof can be provided.

Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Accordingly, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, the part from which the relationship and ratio of a mutual dimension differ also in between drawings is contained.

[First Embodiment]
This embodiment will be described with reference to FIGS. As shown below, this embodiment is NAND
Description will be made by applying to a flash memory. FIG. 3 shows a plan view of the present embodiment. 3 corresponds to FIG. 1, and a cross section on the “CD” line corresponds to FIG.

As shown in FIG. 3, eight word lines 1 are arranged in parallel to each other in the left-right direction in the drawing. A drain side select gate 2 and a source side select gate 3 are formed in parallel to each other with the word line 1 interposed therebetween.

A plurality of bit line wirings 4 are formed orthogonal to the word line 1, the drain side selection gate 2, and the source side selection gate 3.

  Element regions 5 are respectively formed below the bit line wiring 4.

An element isolation region 6 that separates the element regions 5 from each other is formed in parallel to the element region 5.

One bit line 5, eight word lines 1, drain side select gate 2, source side select gate 3 and diffusion layer 18 in element region 5 between each gate constitute one memory cell array. Constitute.

Here, a bit line contact 23 is formed in the element region adjacent to the drain side select gate.

One memory cell array is adjacent to another memory cell array via the bit line contact 23 in the direction of the bit line wiring 5. Further, the source line selection gate side is adjacent to another memory cell array in the direction of the bit line wiring 5 with the element region 5 parallel to the word line 1 interposed therebetween.

In the cross section shown in FIG. 1, eight memory cells in one memory cell array include memory cell gates provided on the gate insulating film 12 on the element region 5 in the well 11 provided on the semiconductor substrate 10. An electrode 13 is provided. Each memory cell gate electrode 13 includes a floating gate electrode 14 serving as a charge storage layer, an intergate insulating film 15 formed on the floating gate 14, a control gate electrode 16 formed on the intergate insulating film 15, and this control gate. A gate mask material 17 is formed on the electrode 16. Among the memory cell gate electrodes 13, the control gate electrode 16 is shared with the other memory cell gate electrodes in the row line direction which is the left-right direction shown in FIG.

The source and drain of each memory cell are connected in series with each other through a diffusion layer region 18 provided on the element region. A plurality of memory cells are connected in series to form a NAND cell (memory cell unit) which is one memory cell array.

Further, a drain side select gate 19 is formed on the gate insulating film 12 at the left end of the eight memory cells. The drain side select gate 19 has a stacked structure similar to that of the memory cell gate 13, but the width of each layer is formed larger than that of the memory cell gate. In the element region 5 on the side opposite to the memory cell of the drain side select gate, the bit line contact diffusion layer 2
0 is formed.

Further, a source side selection gate 21 is formed on the gate insulating film 12 at the right end of the eight memory cells. The source side select gate 21 has a stacked structure similar to that of the memory cell gate 13, but the width of each layer is formed larger than that of the memory cell gate and is the same width as the drain side select gate.

In FIG. 1, the source line select gate 21 has a source line 22 on the side opposite to the memory cell gate 13 side of the source / drain diffusion layer 18 and extends perpendicularly to the surface of the drawing.
The source line 22 is connected between NAND cells adjacent in the row direction, which is the left-right direction shown in FIG.

Each memory cell gate 13 and the diffusion layer 18 provided in the element region at both ends thereof constitute a memory cell transistor.

Further, the drain-side selection gate and the diffusion layer 1 provided in the element region 5 on the memory cell side
8 and the bit line contact diffusion layer 20 constitute a drain side select transistor.

Further, the diffusion layer 18 provided in the source side select gate and the element region 5 on the memory cell side.
And the source line 22 form a source side select transistor.

In FIG. 3, the element region 5 sandwiched between the source line selection gates 3 and orthogonal to the bit line wiring 4 corresponds to the source line 22.

In this way, the memory cell transistors are connected in series without contact with each other. Each select gate transistor is connected to the NAND cell via the diffusion layer 18. As described above, the drain side select gate transistor 19 and the source side select gate transistor 21 are connected to both ends of each NAND cell in the bit line direction.

The selection transistor can supply a potential to the floating gate electrode and functions in the same manner as a general MOSFET.

A bit line contact electrode 23 is provided in the bit line contact diffusion layer 20 on the side opposite to the NAND cell of the drain side select transistor.

Here, the surfaces of the gates 13, 19, and 21 are covered with a post-oxide film 24. Thereafter, a first insulating film 25 is provided on the oxide film 24 and the gate oxide film 12. First insulating film 25
The thickness is, for example, about 0.1 μm or more and does not contain nitrogen as a main component. The first insulating film 25 is provided so as to be embedded between the gate electrodes 13 of the memory cell transistor. The first insulating film 25 is suitable to have a low hydrogen content and a small number of traps for charges. For example, a silicon oxide film, an oxynitride film, an oxidized silicon nitride film, or the like can be used.

Here, “embedding” does not only mean that it is completely filled, but even if it contains voids such as voids and nests inside, its function and effect will not change. means.

Here, the distance between the gate electrodes is about 0.2 μm, for example, and the gate width is about 0.2 μm.
The height is about 0.6 μm.

The distance between the gate electrodes is small between the memory cell gates 13 and large between the select gates 19 sandwiching the bit line contact 23. Since the interval between the gate electrodes of the memory cell gates 13 is strongly related to the area of the entire cell array, the interval is reduced to reduce the area. On the other hand, since the bit line contact is formed between the select gates of the adjacent memory cell arrays, the interval is wide.

A second insulating film 26 is provided on the first insulating film 25. The thickness of the second insulating film 26 is, for example, about 0.02 to 0.06 μm. Since the second insulating film 26 is mainly composed of a nitride film, it becomes a hydrogen supply source, so it is desirable that it be as thin as possible. . The second insulating film 26 is the first
The hydrogen content is higher than that of the insulating film 25 and there are more traps for charges.

An interlayer insulating film 27 is provided on the second insulating film 26. Here, the thickness of the interlayer insulating film is about 0.1 μm to 0.3 μm. The interlayer insulating film 27 can be formed of BPSG (silicon oxide film containing boron).

A bit line contact 23 is provided through the interlayer insulating film 27, the second insulating film 26, the first insulating film 25 and the gate oxide film 12, and is connected to the bit line contact diffusion layer 20.

A bit line 28 is formed on the interlayer insulating film 27. The bit lines are provided separately between NAND cells adjacent in the column direction.

Here, the NAND cell is formed by sandwiching eight transistors between two control gates. However, the number of transistors in the NAND cell is not limited to eight, and any number from eight to thirty-two can be formed.

Further, when the distance between the memory cell gates is about 0.2 μm or less, the effect of this embodiment is remarkable.

Here, the well is P-type and the source / drain diffusion layer is N-type, but the well may be N-type and the source / drain diffusion layer may be P-type.

In the present embodiment, the second insulating film 2 serving as an etching stopper when the contact hole is opened.
6, the first insulating film 25 is provided, and the distance between the memory cell gates 13 is relatively small. Therefore, the first insulating film 25 completely fills the space between the memory cell gates 13. ing. Further, since the distance between the select gates 19 and 21 is larger than the distance between the memory cell gates 13, the first insulating film 25 is not completely buried.

The first insulating film 25 is formed with the same thickness on the gate electrodes 13, 19, and 21 and on the bit line contact diffusion layer 20. However, in some cases, the thickness formed with respect to the side surface of the gate electrode is formed thinner than the first insulating film 25 formed on the gate electrode or the semiconductor substrate, or conversely thick. There is a case.

Next, in the cross section shown in FIG. 2, a plurality of element isolation regions 6 are formed so as to divide the upper surface of the element region 5 provided in the well 11 on the semiconductor substrate 10. A bit line contact 23 is connected to the entire surface of the element region 5 sandwiched between the element isolation regions 6. A first insulating film 25 is formed on the element isolation region 6, and a second insulating film 26 is formed thereon. An interlayer insulating film 27 is formed on the second insulating film 26. A bit line contact 23 is formed through the interlayer insulating film 27, the second insulating film 26, and the first insulating film 25. A bit line wiring 28 is formed on the bit line contact 23.

Here, although the upper surface of the element isolation region 6 is formed at a position higher than the upper surface of the element region 5, it may be formed at the same position as the upper surface of the element region 5.

Although STI (Shallow Trench Isolation) is used as an element isolation method, LOCOS (Local Oxidation of Silicon) is used.
It is also possible to use other element isolation methods.

In FIG. 2, the first insulating film 25 on the element isolation region 6 is formed as thin as possible because the effect of the etching stopper when the contact misalignment occurs is large.
desirable.

In the semiconductor device of the present embodiment, the first insulating film 25 is provided below the second insulating film 26 so that the hydrogen in the second insulating film 26 and the charges trapped in the second insulating film 26 are transistor elements. The influence on the electrical characteristics can be reduced. Furthermore, even if the distance between the memory cell gate electrodes is narrowed, it is possible to provide a highly integrated semiconductor device in which there is no connection form of erroneous contacts to the element isolation region.

That is, according to the semiconductor device of the present embodiment, while improving the etching process margin for opening the contact hole, the deterioration of the electrical characteristics such as the fluctuation of the threshold voltage of the transistor and the decrease of the breakdown voltage in the gate insulating film are prevented. Therefore, a highly reliable semiconductor device with high yield and a method for manufacturing the semiconductor device can be provided.

In particular, in the memory cell transistor portion, the space between the gate electrodes is filled with the first insulating film 25,
The second insulating film 26 does not exist in the vicinity of the gate oxide film 12 of the transistor.

Therefore, the characteristic deterioration of the memory cell transistor can be prevented, and the reliability of the semiconductor device can be improved.

In particular, in a nonvolatile semiconductor memory device, the interval between select gates of adjacent memory cell arrays is wider than the interval between word lines in the same memory cell array, and the entire memory cell array is formed by stacking an oxide film and a nitride film. Covered by a membrane. Here, the space between the word lines is filled only with the first insulating film 25, and both the first insulating film 25 and the second insulating film 26 are inserted between the select gates.

Here, since there is no nitride film having a high hydrogen content between the word lines, it is possible to prevent the trapping of electrons in the nitride film and fluctuation of cell characteristics. Furthermore, at the time of etching when forming the contact electrode between the select gates, since the nitride film in the second insulating film 6 on the first insulating film 25 functions as a stopper, high reliability and high yield can be obtained.

Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 1 and 4 to 9.

First, an element region 5 surrounded by an element isolation region (not shown) is formed on a semiconductor substrate 10 made of silicon, and a gate insulating film 12 is formed on the element region 5 as shown in FIG. . Next, a floating gate electrode material 14 is deposited on the gate insulating film 12. Further, a floating gate / control gate insulating film 15 is formed, and a control gate electrode material 16 is deposited thereon.

Further, a gate mask material 17 is deposited as a mask for gate etching. Subsequently, the gate is patterned by photolithography, and the gate mask material 17 is etched. Subsequently, the control gate electrode material 16, the floating gate / control gate insulating film 15, and the floating gate electrode material 14 are etched in a self-aligned manner with respect to the gate mask material 17 to form the memory cell gate 13 and the selection gates 19 and 21. To do.

Next, as shown in FIG. 5, post-oxidation is performed to recover damage during gate processing, so that a post-oxide film 24 is formed around the gate electrode having a laminated structure.

Next, as shown in FIG. 6, impurities for forming the source / drain diffusion layer 18 and the bit line contact diffusion layer 20 are ion-implanted. The ion implantation of the diffusion layer may be performed after the post-oxidation as described above or may be performed before. Further, it may be after the first insulating film is formed in a later process.

Next, as shown in FIG. 6, the first insulating film 25 is formed on the exposed portion. First insulating film 2
5 is formed with a film thickness that completely embeds between the gate electrodes 13 of the memory cell transistor and does not completely embed between the select gates 19 and 21. This first insulating film 25
In the region between and between the eight memory cell gate electrodes 13 sandwiched between the drain side control gate 19 and the source side control gate 21, the upper surface thereof is flattened. Further, the surface of the first insulating film 25 in the bit line contact formation scheduled region is also planarized. Even if there is a gap in the first insulating film 25, it can be fluidized and removed by applying heat in a later step to oxidize.

Next, as shown in FIG. 7, a second insulating film 26 is formed on the first insulating film 25. Further, an interlayer insulating film 27 is deposited on the second insulating film 26, and the surface of the interlayer insulating film 27 is planarized by applying a CMP method or heat treatment to cause the interlayer insulating film to flow. , 21 is embedded with an interlayer insulating film 27.

Here, after the interlayer insulating film 27 is formed, when the space between the select gate electrodes 19 and 21 is embedded, the interlayer insulating film 27 may not be completely embedded only by depositing. In that case, after the interlayer insulating film 27 is deposited, the interlayer insulating film 27 can be fluidized and embedded by applying heat treatment. When this thermal process is performed in an oxygen atmosphere, the fluidity of the interlayer insulating film may be improved.

Even if there is a void in the interlayer insulating film 27, it can be fluidized and removed by applying heat in a later step to oxidize. Note that the diffusion coefficient of the impurity diffusion layer serving as the source / drain increases due to the thermal process.

As shown in FIG. 8, planarization can also be performed by polishing the interlayer insulating film 27 using CMP which is selective to the second insulating film 26. Thus, by stopping the polishing on the second insulating film 26 and subsequently depositing the interlayer insulating film again, it is possible to form an interlayer insulating film having the same shape as in FIG. Here, the interlayer insulating film to be deposited again may be the same as the previously deposited material or may be changed. According to this method, the planarization by the CMP method is stopped on the second insulating film 26, so that the controllability of the film thickness of the interlayer insulating film can be improved, and the thickness of the interlayer insulating film can be formed accurately. .

Next, after planarizing the interlayer insulating film 27 as described above, a contact hole 30 for making contact with the source / drain diffusion layer 20 of the memory cell portion is formed as shown in FIG. The contact hole 30 is etched by first etching the interlayer insulating film 27 that is selective to the second insulating film 26. Next, the second insulating film 26, the first insulating film 25, and the gate oxide film 12 are sequentially etched to expose the bit line contact diffusion layer 20.

Next, as shown in FIG. 1, a bit line contact 23 is formed by embedding a metal such as aluminum or tungsten or a low-resistance semiconductor in the contact hole 30. After forming the bit line contact 23, a metal line is formed on the interlayer insulating film 27, thereby forming a bit line line 28 connected to the bit line contact 23.

Note that air gaps may be formed in the interlayer insulating film 27 or in the first insulating film 25 between the memory cell gates 13.

Here, as the second insulating film 26, a film having etching resistance against etching of the interlayer insulating film 27 when the contact hole 30 is opened is used. For example, when a silicon oxide film is used as the interlayer insulating film 27, a silicon nitride film or the like is used as the second insulating film 26.

In the present embodiment, as shown in FIGS. 2 and 3, the bit line contact 23 is designed so that there is almost no margin with respect to the element region 5.

That is, as shown in FIG. 3, the bit line contact 23 is formed to have the same width as the element region 5. In some cases, the bit line contact 23 may be formed larger than the width of the element region 5. This is to reduce the area of the cell array as much as possible.

In such a semiconductor device, even when the bit line contact 23 is formed on the element isolation region 6 due to misalignment of the mask, the bit line contact 23 penetrates into the element isolation region 6. There must be no. This is because if the bit line contact 23 penetrates the element isolation region 6, it may cause a junction leakage current in that portion or cause a decrease in element isolation breakdown voltage.

In the present embodiment, since the second insulating film 26 has resistance to the etching of the interlayer insulating film 27, the etching for forming the contact hole can be temporarily stopped on the second insulating film 26.

After opening the contact hole 30 reaching the second insulating film 26 in this way, the etching conditions are switched to etch the second insulating film 26, and the conditions are further switched to etch the first insulating film 25 and the gate oxide film 12. By doing so, the bit line contact diffusion layer 2
The contact hole 30 above 0 is completely opened.

Further, when a silicon nitride film is used as the second insulating film 26, it can also serve to prevent diffusion of boron, phosphorus, carbon, and the like contained in the interlayer insulating film into the element region. When such impurities diffuse into the element region, it causes fluctuations and variations in element characteristics. However, since the diffusion coefficient in the silicon nitride film is extremely small, the diffusion can be blocked by the silicon nitride film. .

Further, when there is an oxidation process after the formation of the second insulating film 26, there is a phenomenon that when oxygen diffuses into the element region 5, the diffusion of impurities is accelerated and the impurity distribution is lost. By using it for the insulating film, oxygen can be prevented from diffusing into the element region 5, so that the accelerated diffusion in the element region can be prevented and the impurity distribution can be easily designed.

Further, in the vicinity of the bit line contact 23, the space between the select gates 19 is not completely filled with the first insulating film 25, so that the film thickness of the first insulating film is smaller than that between the memory cell transistors. Yes. Therefore, when the first insulating film 25 is etched in order to open the bit line contact hole 30, even if the element isolation region is etched at the same time, the film thickness of the first insulating film 25 is small, so that the element isolation region The etching amount can be suppressed to be small.

That is, when the contact is opened, the interlayer insulating film 27 is first selectively etched, so that the etching is stopped on the second insulating film 26. Next, the second insulating film 26 is selectively etched. Therefore, the first insulating film 25 is etched regardless of the thickness of the interlayer insulating film 27.

According to the manufacturing method of the semiconductor device of this embodiment, the bit line contact can be formed with high controllability and good controllability, and the adverse effect of hydrogen on the transistor characteristics can be prevented.

[Second Embodiment]
This embodiment will be described with reference to FIGS. FIG. 10 is a plan view showing the semiconductor device of this embodiment. 11 is a view showing a cross section “EF” of FIG. 10, and FIG.
It is a figure which shows 0 "GH" cross section.

This embodiment is different from the first embodiment in the form of drawing the bit line and the source line to the wiring. Since the form in the other part is the same as that of the first embodiment, the description is omitted.

In the first embodiment, the bit line is connected to the wiring from the source / drain diffusion layer through the bit line contact, and the source line is connected to the element region adjacent to each other and connected by the source / drain diffusion layer. Was configured.

In the present embodiment, as shown in FIG. 11, the bit line is formed of the bit line contact diffusion layer 2.
From 0, the bit line contact 23 is connected to the bit line connecting portion 35 by the first layer wiring, and further, the wiring is connected to the bit line 37 by the second layer wiring through the inter-wiring contact 36.

On the other hand, the source line is connected from the source line contact diffusion layer 34 to the source line 39 of the first layer wiring via the source line contact 38, and these are connected to each other between adjacent memory cell arrays. The source line 39, the bit line connecting portion 35 and the inter-wiring contact 36 are
The bit line 37 is formed on the inter-wiring insulating film 40.

In the cross section shown in FIG. 12, the element region 5 provided in the well 11 on the semiconductor substrate 10.
A plurality of element isolation regions 6 are formed so as to divide the upper surface of the element. A bit line contact 23 is connected to the entire surface of the element region 5 sandwiched between the element isolation regions 6.

A first insulating film 25 is formed on the element isolation region 6, and a second insulating film 26 is formed thereon. An interlayer insulating film 27 is formed on the second insulating film 26. A bit line contact 23 is formed through the interlayer insulating film 27, the second insulating film 26, and the first insulating film 25. The bit line contact 23 is connected to a bit line connection portion 35 and further connected to a bit line 37 formed by a second layer wiring via an inter-wiring contact 36.

The bit line connection portion 35 and the interwiring contact 36 are covered with an interwiring insulating film 40.

In general, the sheet resistance of the wiring is smaller than the sheet resistance of the diffusion layer. Therefore, in this embodiment, the electrical resistance of the source line can be made lower than in the first embodiment, and the operation speed can be increased. Is possible.

Note that the source line contact is formed as in this embodiment mode, but the bit line contact may not be formed. In this case, like the source line in the first embodiment,
The bit line is configured by connecting element regions adjacent to each other and connecting with source / drain diffusion layers. In this case, the resistance of the source line can be lowered.

[Third Embodiment]
FIG. 13 shows a cross-sectional structure of the present embodiment. This cross-sectional view corresponds to a cross section on the “AB” line in FIG. 3. However, unlike the first embodiment, the memory cell gate electrode 13
The post-oxide film is not provided on the side surfaces of the drain side select gate 19 and the source side select gate 21. That is, in this embodiment, the first oxidation is performed without performing post-oxidation after the gate electrode is processed.
An insulating film 25 is formed. In this case, the first insulating film 25 functions as an oxide film instead of the post-oxide film.

  Other structures than the above are formed in the same manner as in the first embodiment.

Even if it is such a structure, the effect similar to 1st Embodiment can be acquired. The feature that the post-oxide film is not provided on the side surface of each gate electrode, which is the feature of this embodiment, can be similarly applied to the second embodiment.

[Fourth Embodiment]
FIG. 13 shows a cross-sectional structure showing a fourth embodiment of the present invention. This cross-sectional view corresponds to a cross section on the “AB” line in FIG. 3. However, unlike the first embodiment, the first insulating film 25 is formed on the bit line contact diffusion layer 20 and the source diffusion layer 22 as a gently curved surface. Therefore, the second insulating film 26 on the first insulating film 25 is also formed on the first insulating film 25 in a shape corresponding to the shape of the first insulating film 25. Further, the bottom surface of the interlayer insulating film 27 formed on the second insulating film 26 has a shape corresponding to the second insulating film 26, and the other structure is the same as that of the first embodiment.

The manufacturing method of the present embodiment is the same as that of the first embodiment in the step shown in FIG.
After the insulating film 25 is deposited, for example, a heat treatment of about 800 ° C. to 900 ° C. is performed to cause the first insulating film 25 to flow. The first insulating film 25 is buried between the memory cell gate electrode 13 and the source side selection gate electrode 21, and the height between the selection gate electrodes 19, 21 is higher than the height of the selection gate electrodes 19, 21. The first insulating film 25 is formed low.

  Thereafter, a second insulating film 26 is formed on the first insulating film 25.

Thus, by adding a step of flowing the first insulating film 25 after deposition,
Narrower gate electrodes can be filled with the first insulating film 25, and the device can be miniaturized.

In other words, when the gap between the gate electrodes is narrow, there is a case where a depression-like depression or a large gap is formed only by depositing an insulating film and is not buried. Here, by performing heat treatment, the insulating film may be fluidized to fill the gap.

In addition, in the case where the height of the gate electrode is remarkably high compared to the distance between the gate electrodes, a concave recess or a large gap is easily generated in the first insulating film between the gate electrodes.
In the present embodiment, the gap in the first insulating film generated in this way can be filled.

In this embodiment, the film thickness of the first insulating film 25 on the gate electrode 13 of the memory cell transistor and the film thickness of the first insulating film 25 on the bit line contact diffusion layer 20 are different. An effect similar to that of the embodiment can be obtained.

Note that the present embodiment can also be applied to a configuration in which a source line contact is provided as in the second embodiment.

The first insulating film 25 may be formed by, for example, a method of forming a shape as in the present embodiment at the time of deposition, other than the method of flowing by heat treatment after deposition.

In each embodiment, between the memory cell gate electrodes 13, the memory cell gate electrode 1
There may be a cavity in the first insulating film 25 filling the gate electrode between the memory cell gate electrode 13 and the source side select gate electrode 21 between the gate electrode 3 and the drain side select gate electrode 19. Even if there is a cavity, if the upper surface of the film is closed, the second insulating film 26 is not buried between the gate electrodes of the memory cell transistor, so the effect of the present invention does not change.

Further, the post oxide film 24 may be formed by thermal oxidation as shown in the first embodiment, or may be formed by depositing an oxide film or the like. Further, the post-oxide film may not be provided as in the third embodiment.

  Each embodiment can be implemented in combination as appropriate in addition to the above.

Each embodiment has been described by taking a NAND type EEPROM memory cell array as an example. However, the present invention can be similarly applied to AND type and DiNOR type memory cell arrays and semiconductor devices having transistors that require high integration. It is.

That is, any structure in which a plurality of gates are connected in series and there is no contact between the gates is applicable.

In particular, it is suitable for a nonvolatile semiconductor memory device that has a contact with no margin for the element region and is applied with a strong electrical stress that causes a tunnel current to flow through the gate oxide film.

FIG. 4 is a cross-sectional view along “AB” in FIG. 3, which is a plan view showing the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a sectional view on “CD” in FIG. 3, which is a plan view showing the semiconductor device according to the first embodiment of the present invention. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. Sectional drawing which shows 1 process of the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. Sectional drawing which shows 1 process of the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. Sectional drawing which shows 1 process of the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. Sectional drawing which shows 1 process of the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. Sectional drawing which shows 1 process of the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. Sectional drawing which shows 1 process of the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. The top view which shows the semiconductor device of the 2nd Embodiment of this invention. FIG. 11 is a cross-sectional view taken along the line “EF” in FIG. 10, which is a plan view showing a semiconductor device according to a second embodiment of the present invention. FIG. 11 is a cross-sectional view taken along the line “GH” in FIG. 10, which is a plan view showing a semiconductor device according to a second embodiment of the present invention. Sectional drawing which shows the semiconductor device of the 3rd Embodiment of this invention. Sectional drawing which shows the semiconductor device of the 4th Embodiment of this invention. FIG. 18 is a cross-sectional view taken along the line “I-J” in FIG. 17, which is a plan view showing a conventional semiconductor device. FIG. 18 is a plan view showing a conventional semiconductor device, which is a cross-sectional view taken along the line “KL” in FIG. 17. The top view which shows the conventional semiconductor device. Sectional drawing which shows 1 process of the manufacturing method of the conventional semiconductor device. Sectional drawing which shows 1 process of the manufacturing method of the conventional semiconductor device. Sectional drawing which shows 1 process of the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the problem of the etching of the contact hole in the manufacturing method of the conventional semiconductor device. Sectional drawing at the time of the etching of the contact hole in the manufacturing method of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Word line, 2 ... Drain side selection gate, 3 ... Source side selection gate, 4, 37 ... Bit line wiring, 5 ... Element region, 6 ... Element isolation region, 10 ... Semiconductor substrate, 11 ... Well, 12 ...
Gate insulating film, 13 ... Memory cell gate, 14 ... Floating gate, 15 ... Floating gate / control gate insulating film, 16 ... Control gate, 17 ... Gate mask material, 18 ... Source / drain diffusion layer, 20 ... Bit line contact Diffusion layer, 22, 39 ... Source line, 23 ... Bit line contact, 24 ... Post oxide film, 25 ... First insulating film, 26 ... Second insulating film, 27, 40 ... Interlayer insulating film,
30 ... contact hole, 34 ... source line contact diffusion layer, 35 ... bit line connection part, 3
6 ... Wiring contact, 38 ... Source line contact

Claims (10)

A semiconductor substrate;
A plurality of memories provided via a first gate insulating film formed on the semiconductor substrate and having a charge storage layer and a control gate electrode formed via an inter-gate insulating film formed on the charge storage layer A memory cell transistor group comprising cell gates;
A select gate transistor comprising a select gate provided via a second gate insulating film formed on the semiconductor substrate adjacent to the plurality of memory cell gates;
A first diffusion layer provided in a semiconductor substrate below the side surface opposite to the side adjacent to the memory cell gate of the selection gate;
A first insulating film which is embedded between the plurality of memory cell gates and between the memory cell gates and the selection gates and is formed on the first diffusion layer and does not contain nitrogen as a main component;
A second insulating film formed on the first insulating film;
An interlayer insulating film formed on the second insulating film and having a different main component from the second insulating film;
A contact electrode passing through the interlayer insulating film, the second insulating film, and the first insulating film and connected to the first diffusion layer;
The density of hydrogen contained in the first insulating film is smaller than the density of hydrogen contained in the second insulating film,
The semiconductor device according to claim 1, wherein the thickness of the first insulating film between the memory cell gates is greater than the thickness of the portion of the first diffusion layer in contact with the contact electrode. A semiconductor substrate;
A plurality of memories provided via a first gate insulating film formed on the semiconductor substrate and having a charge storage layer and a control gate electrode formed via an inter-gate insulating film formed on the charge storage layer A memory cell transistor group comprising cell gates;
A select gate transistor comprising a select gate provided via a second gate insulating film formed on the semiconductor substrate adjacent to the plurality of memory cell gates;
A first diffusion layer provided in a semiconductor substrate below the side surface opposite to the side adjacent to the memory cell gate of the selection gate;
A first insulating film formed between the plurality of memory cell gates and between the memory cell gates and the select gates and formed on the first diffusion layer and containing no nitrogen as a main component;
A second insulating film formed on the first insulating film;
An interlayer insulating film formed on the second insulating film and having a different main component from the second insulating film;
A contact electrode passing through the interlayer insulating film, the second insulating film, and the first insulating film and connected to the first diffusion layer;
A density of traps for charges existing in the first insulating film is smaller than a density of traps for charges existing in the second insulating film;
The semiconductor device according to claim 1, wherein a thickness of the first insulating film between the memory cell gates is larger than a thickness of a portion of the first diffusion layer in contact with the contact electrode. The horizontal thickness of the first insulating film adhering to the side surface of the selection gate on the first diffusion layer is formed to be larger than half of the distance between the memory cell gates. The semiconductor device according to claim 1 or 2. A semiconductor substrate;
A memory cell gate provided via a first gate insulating film formed on the semiconductor substrate and having a charge storage layer and a control gate electrode formed via an inter-gate insulating film formed on the charge storage layer Are arranged on the semiconductor substrate in contact with the first diffusion layer, a first diffusion layer provided in the semiconductor substrate across the first memory cell transistor group. A first memory cell array including a first selection transistor having a selection gate formed through the second gate insulating film;
A second memory cell transistor group in which a plurality of the memory cell gates provided via the first gate insulating film formed on the semiconductor substrate are disposed; and the second memory cell transistor group sandwiching the second memory cell transistor group, And a second selection transistor having a selection gate formed on the semiconductor substrate through the second gate insulating film and in contact with the second diffusion layer. Two memory cell arrays;
A third diffusion layer formed in the semiconductor substrate between the first memory cell array and the second memory cell array;
The space between the memory cell gates is embedded on the semiconductor substrate between the first memory cell array and the second memory cell array, and the thickness between the memory cell gates is the first memory cell array and the second memory cell array. A first insulating film which is formed thicker than the intermediate thickness and does not contain nitrogen as a main component;
A second insulating film provided on the first insulating film;
An interlayer insulating film formed on the second insulating film and having a different main component from the second insulating film;
The interlayer insulating film, the second insulating film, and the first insulating film, the first memory cell array, and a contact electrode connected to the third diffusion layer between the second cell arrays,
The density of hydrogen contained in the first insulating film is smaller than the density of hydrogen contained in the second insulating film. A semiconductor substrate;
A memory cell gate provided via a first gate insulating film formed on the semiconductor substrate and having a charge storage layer and a control gate electrode formed via an inter-gate insulating film formed on the charge storage layer Are arranged on the semiconductor substrate in contact with the first diffusion layer, a first diffusion layer provided in the semiconductor substrate across the first memory cell transistor group. A first memory cell array including a first selection transistor having a selection gate formed through the second gate insulating film;
A second memory cell transistor group in which a plurality of the memory cell gates provided via the first gate insulating film formed on the semiconductor substrate are disposed; and the second memory cell transistor group sandwiching the second memory cell transistor group, And a second selection transistor having a selection gate formed on the semiconductor substrate through the second gate insulating film and in contact with the second diffusion layer. Two memory cell arrays;
A third diffusion layer formed in the semiconductor substrate between the first memory cell array and the second memory cell array;
The space between the memory cell gates is embedded on the semiconductor substrate between the first memory cell array and the second memory cell array, and the thickness between the memory cell gates is the first memory cell array and the second memory cell array. A first insulating film which is formed thicker than the intermediate thickness and does not contain nitrogen as a main component;
A second insulating film provided on the first insulating film;
An interlayer insulating film formed on the second insulating film and having a different main component from the second insulating film;
The interlayer insulating film, the second insulating film, and the first insulating film, the first memory cell array, and a contact electrode connected to the third diffusion layer between the second cell arrays,
A semiconductor device, wherein a density of traps for charges existing in the first insulating film is smaller than a density of traps for charges existing in the second insulating film. 5. The interval between the memory cell gates in the first memory cell array and the second memory cell array is smaller than the interval between the selection gate of the first selection transistor and the selection gate of the second selection transistor. Or the semiconductor device according to 5; 7. The semiconductor device according to claim 1, wherein the first insulating film is made of a material selected from a silicon oxide film, a silicon oxynitride film, and an oxidized silicon nitride film. . The semiconductor device according to claim 1, wherein the second insulating film is a silicon nitride film. Forming a gate insulating film on the semiconductor substrate;
A first memory cell in which a plurality of memory cell gates having a charge storage layer formed through the gate insulating film and a control gate electrode formed through an intergate insulating film formed on the charge storage layer are arranged A gate group, a first selection gate pair formed on the gate insulating film across the first memory cell gate group, and a second memory cell gate in which a plurality of the memory cell gates are arranged via the gate insulating film Forming a group, a second select gate pair formed on the gate insulating film across the second memory cell gate group;
Forming a plurality of diffusion layers in the semiconductor substrate using the first memory cell gate group, the first select gate pair, the second memory cell gate group, and the second select gate pair as a mask;
Forming a first insulating film not containing nitrogen as a main component on the entire surface of the semiconductor substrate, embedding the gates of the first memory cell gate group and the second memory cell gate group, and the first selection; The gate pair and the second select gate pair have a portion having a first film thickness that is thinner than between the gates of the first memory cell gate group and the second memory cell gate group on the adjacent diffusion layer. Forming the first insulating film;
Forming a second insulating film having a density of hydrogen contained on the first insulating film larger than that of the first insulating film;
Forming an interlayer insulating film having a high etching selectivity with respect to the second insulating film on the second insulating film;
The interlayer insulating film on the diffusion layer in the portion where the first insulating film has the first film thickness;
Etching the insulating film and the first insulating film to form a contact opening;
A method of manufacturing a semiconductor device, comprising: embedding a conductive material in the contact opening and connecting the first selection gate pair and the second selection gate pair to the adjacent diffusion layer. Forming a gate insulating film on the semiconductor substrate;
A first memory cell in which a plurality of memory cell gates having a charge storage layer formed through the gate insulating film and a control gate electrode formed through an intergate insulating film formed on the charge storage layer are arranged A gate group, a first selection gate pair formed on the gate insulating film across the first memory cell gate group, and a second memory cell gate in which a plurality of the memory cell gates are arranged via the gate insulating film Forming a group, a second select gate pair formed on the gate insulating film across the second memory cell gate group;
Forming a plurality of diffusion layers in the semiconductor substrate using the first memory cell gate group, the first select gate pair, the second memory cell gate group, and the second select gate pair as a mask;
Forming a first insulating film not containing nitrogen as a main component on the entire surface of the semiconductor substrate, embedding the gates of the first memory cell gate group and the second memory cell gate group, and the first selection; The gate pair and the second select gate pair have a portion having a first film thickness that is thinner than between the gates of the first memory cell gate group and the second memory cell gate group on the adjacent diffusion layer. Forming the first insulating film;
Forming a second insulating film on the first insulating film having a trap density with respect to an existing charge larger than that of the first insulating film;
Forming an interlayer insulating film having a high etching selectivity with respect to the second insulating film on the second insulating film;
The interlayer insulating film on the diffusion layer in the portion where the first insulating film has the first film thickness;
Etching the insulating film and the first insulating film to form a contact opening;
A method of manufacturing a semiconductor device, comprising: embedding a conductive material in the contact opening and connecting the first selection gate pair and the second selection gate pair to the adjacent diffusion layer.

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