JP4130494B2 - Nonvolatile semiconductor memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory.
[0002]
[Prior art]
Conventionally, as one of nonvolatile semiconductor memories, for example, a NAND flash EEPROM having a memory cell array portion as shown in FIG. 46 is known.
[0003]
The memory cell array portion of the NAND flash EEPROM is composed of a plurality of NAND cell units. Each NAND cell unit includes a NAND string composed of a plurality of (for example, 16) memory cells connected in series, a source-side select gate transistor connected between one end of the NAND string and the source line SL, and a NAND string And a drain side select gate transistor connected between the other end of bit line BLi and bit line BLi.
[0004]
The memory cell array part is composed of a plurality of blocks BLKj. The control gate electrodes (word lines) CG0 to CG15, the source side select gate electrode SGS and the drain side select gate electrode SGD extend in the row direction, and the bit line BLi extends in the column direction. A plurality of memory cells M0 to Mi connected to one word line constitute a unit called page PAGE.
[0005]
Normally, data for one page is read out by one read operation. The data for one page is latched by the latch circuit and then serially output to the outside of the memory chip.
[0006]
FIG. 47 schematically shows a planar pattern of the memory cell array portion of the NAND flash EEPROM. FIG. 48 shows the area XD in FIG. 47 in an enlarged manner, and FIG. 49 shows the area XS in FIG. 47 in an enlarged manner. FIG. 50 is a cross-sectional view of the memory cell array portion of the NAND flash EEPROM.
[0007]
A field oxide film 11 is formed on the silicon substrate 10. In the element region surrounded by the field oxide film 11, for example, a NAND cell unit composed of 16 memory cells and 2 select gate transistors is arranged.
[0008]
Each memory cell includes a floating gate electrode FG, control gate electrodes (word lines) CG0 to CG15, and an N-type diffusion layer 12. The source side select gate transistor is composed of select gate electrodes SGS (upper), SGS (lower) and N-type diffusion layers 12a and 12. The drain side select gate transistor is composed of select gate electrodes SGD (upper) and SGD (lower) and N-type diffusion layers 12b and 12.
[0009]
The control gate electrodes CG0 to CG15, the source side select gate electrodes SGS (upper), SGS (lower) and the drain side select gate electrodes SGD (upper), SGD (lower) extend in the row direction, and the bit line BLi extends in the column direction. Is growing. The bit line BLi is connected to the diffusion layer 12b through the wiring B. The source line SL is connected to the diffusion layer 12a.
[0010]
The source side and drain side select gate transistors are provided for selecting memory cells to be written and erased during data writing and erasing, respectively. For this reason, unlike the memory cell, the source side and drain side select gate transistors are configured to perform a switching operation at a certain threshold value.
[0011]
Therefore, in the source-side and drain-side select gate transistors, the control signal is directly applied to the first-layer select gate electrodes SGS (lower) and SGD (lower). Specifically, part of the second-layer select gate electrodes SGS (upper) and SGD (upper) are removed, and the removed portions include first-layer select gate electrodes SGS (lower), A contact region for the SGD (bottom) is formed. Contact holes SS and SD are formed on the contact region.
[0012]
The hatched portions in FIGS. 48 and 49 indicate portions where the first-layer select gate electrodes SGS (lower) and SGD (lower) are present.
[0013]
One contact region (contact hole SS, SD) is provided every time the select gate electrode straddles several hundred bit lines in consideration of the resistance of the select gate electrode. For example, the contact region for the first-layer select gate electrode SGS (lower) of the source-side select gate transistor is provided in common to the two first-layer select gate electrodes SGS (lower) adjacent in the column direction. The contact region for the first-layer select gate electrode SGD (lower) of the drain-side select gate transistor is separately provided on two first-layer select gate electrodes SGD (lower) adjacent in the column direction. Yes.
[0014]
With respect to the drain side select gate transistors, contact regions for two first-layer select gate electrodes SGD (lower) adjacent in the column direction may be alternately arranged so as not to face each other as shown in FIG. Alternatively, as shown in FIG. 51, they may be arranged to face each other.
[0015]
Next, a method for manufacturing a memory cell array portion of a conventional NAND flash EEPROM will be described.
[0016]
First, as shown in FIGS. 52 to 57, a field oxide film (hatched portion) 11 is formed on the silicon substrate 10 by using the LOCOS method. A gate oxide film 13 is formed in the element region between the field oxide films 11 by thermal oxidation. For example, an n-type impurity (for example, phosphorus) is about 2 × 10 6 on the field oxide film 11 and the gate oxide film 13 by using the CVD method. ²⁰ cm ^-3 A polysilicon film 14 is formed.
[0017]
In addition, a slit-like opening OP extending in the column direction is formed in the polysilicon film 14. The width of the opening OP (width in the row direction) is narrower than the width of the field oxide film 11 (width in the row direction).
[0018]
An insulating film 15 is formed on the polysilicon film 14. The insulating film 15 is composed of, for example, a silicon oxide film having a thickness of about 5 nm, a silicon nitride film having a thickness of about 8 nm, and a silicon oxide film having a thickness of about 5 nm (referred to as “ONO film”).
[0019]
Further, for example, about 3.6 × 10 6 is formed on the insulating film 15 by the CVD method. ²⁰ cm ^-3 A polysilicon film 16 containing n-type impurities (for example, phosphorus) is formed. Subsequently, a silicon nitride film (mask material) 17 is formed on the polysilicon film 16 by CVD.
[0020]
A resist pattern 18A is formed on the silicon nitride film 17 by PEP (Photo Etching Process). Then, using the resist pattern 18A as a mask, the silicon nitride film 17 and the polysilicon film 16 are etched by RIE. As a result, the line-like polysilicon film 16 extending in the row direction remains, and the control gate electrodes (word lines) CG0 to CG15 and second-layer select gate electrodes SGS (upper) and SGD (upper) are formed. .
[0021]
At this time, with respect to the select gate electrodes SGS (upper) and SGD (upper), the portion corresponding to the contact region for the first-layer select gate electrode is removed. Thereafter, the resist pattern 18A is removed.
[0022]
Next, as shown in FIGS. 58 to 65, a resist pattern 18B is formed in a portion corresponding to the contact region for the select gate electrode of the first layer by PEP (Photo Etching Process). Using this resist pattern 18B as a mask, the insulating film 15 and the polysilicon film 14 are etched by RIE.
[0023]
At this time, the silicon nitride film 17 existing on the control gate electrodes (word lines) CG0 to CG15 and the second-layer select gate electrodes SGS (upper) and SGD (upper) also functions as a mask for RIE. For this reason, the floating gate electrode FG made of the polysilicon film 14 is formed immediately below the control gate electrodes (word lines) CG0 to CG15, and below the select gate electrodes SGS (upper) and SGD (upper), First-layer select gate electrodes SGS (lower) and SGD (lower) made of the silicon film 14 are formed, and a first-layer select gate electrode SGS (lower) made of the polysilicon film 14 is formed immediately below the resist pattern 18B. Lower), contact regions for SGD (lower) are formed.
[0024]
Thereafter, the resist pattern 18B is removed. The silicon nitride film 17 is not deleted in this example, but may be deleted or not deleted.
[0025]
Next, as shown in FIGS. 66 to 77, the control gate electrodes CG0 to CG15 and the select gate electrodes SGD (upper) and SGS (upper) are used as masks to form n-type impurities (in the silicon substrate 10) by self-alignment. Phosphorus or arsenic) is ion-implanted to form n-type diffusion layers 12, 12a, 12b. The diffusion layer 12a becomes the source of the NAND cell unit, and the diffusion layer 12b becomes the drain of the NAND cell unit.
[0026]
Further, a BPSG film 19 having a thickness of, for example, about 1.45 μm is formed on the entire surface of the silicon substrate 10 so as to completely cover the control gate electrodes CG0 to CG15 and the select gate electrodes SGD (upper) and SGS (upper). To do. Thereafter, the BPSG film 19 is polished by about 0.4 μm by using the CMP method, and the surface of the BPSG film 19 is flattened.
[0027]
Further, a silicon nitride film 20 as an etching stopper is formed on the BPSG film 19 by the CVD method. Subsequently, a TEOS film 21 is formed on the silicon nitride film 20 by a CVD method.
[0028]
Wiring trenches 22A to 22E are formed in the TEOS film 21 using PEP and RIE. During RIE, the silicon nitride film 20 functions as an etching stopper. Further, contact holes 23A and 23C reaching the diffusion layer (drain) 12b and the diffusion layer (source) 12a are formed in the silicon nitride film 20 and the BPSG film 19 using PEP and RIE, and the first layer is selected. Contact holes 23B and 23D reaching the contact regions for the gate electrodes SGD (lower) and SGS (lower) are formed.
[0029]
Thereafter, barrier metals 24, 26, 28, 30, and 32 are formed on the TEOS film 21, on the inner surfaces of the wiring grooves 22A to 22E and the inner surfaces of the contact holes 23A to 23D, respectively. The barrier metals 24, 26, 28, 30, and 32 are made of, for example, titanium nitride and titanium. In addition, tungsten films 25, 27, 29, 31, and 33 that completely fill the wiring trenches 22A to 22E and the contact holes 23A to 23D are formed on the barrier metals 24, 26, 28, 30, and 32. The tungsten films 25, 27, 29, 31, and 33 are polished by the CMP method and remain only in the wiring grooves 22A to 22E and the contact holes 23A to 23D.
[0030]
Next, as shown in FIGS. 78 to 87, a TEOS film 34 is formed on the TEOS film 21 by the CVD method. Subsequently, a silicon nitride film 35 as an etching stopper is formed on the TEOS film 34 by the CVD method. Further, a TEOS film 36 is formed on the silicon nitride film 35 by the CVD method.
[0031]
Wiring trenches 37A and 70A are formed in the TEOS film 36 using PEP and RIE. During RIE, the silicon nitride film 35 functions as an etching stopper. Further, contact holes 37B and 70B are formed in the silicon nitride film 35 and the TEOS film 34 using PEP and RIE.
[0032]
Thereafter, barrier metals 38 and 71 are formed on the TEOS film 36 on the inner surfaces of the wiring grooves 37A and 70A and the inner surfaces of the contact holes 37B and 70B, respectively. The barrier metals 38 and 71 are made of, for example, titanium nitride and titanium. In addition, metal films (such as aluminum) 39 and 72 that completely fill the wiring grooves 37A and 70A and the contact holes 37B and 70B are formed on the barrier metals 38 and 71, respectively.
[0033]
The metal films 39 and 72 are polished by the CMP method and remain only in the wiring grooves 37A and 70A and the contact holes 37B and 70B. As a result, bit lines BL and other wirings are formed. A passivation film made of a silicon nitride film is formed on the bit lines and other wirings.
[0034]
The NAND flash EEPROM is completed through the above manufacturing process.
[0035]
[Problems to be solved by the invention]
As described above, the select gate transistors on the source side and the drain side in the NAND cell unit have the select gate electrodes SGS (lower) and SGD (lower) of the first layer and the select gate electrode SGS (lower) of the second layer, respectively. Top), SGD (top). Further, a part of the second-layer select gate electrodes SGS (upper) and SGD (upper) is removed, and the portions are contact regions for the first-layer select gate electrodes SGS (lower) and SGD (lower). It has become.
[0036]
That is, what actually functions as the select gate electrode of the select gate transistor is the first-layer select gate electrodes SGS (lower) and SGD (lower), and the contact region is the first-layer select gate electrode. In consideration of the resistance of SGS (lower) and SGD (lower), a plurality of locations (one for every several hundred bit lines) are set.
[0037]
The size of the contact region is determined in consideration of misalignment of contact holes formed in the photolithography process on the contact region. In general, when a contact hole misalignment margin is included in the size of the contact hole, the length of the contact region in the column direction is larger than the gate length g of the select gate electrodes SGS (lower) and SGD (lower).
[0038]
88 and 89 show two examples regarding the arrangement of the contact region with respect to the first-layer select gate electrode on the drain side. Here, the minimum width that can be processed in the photolithography process is n (for example, the interval between the control gate electrodes is set to n).
[0039]
In the case of the example in FIG. 88, the length of the portion where the contact region protrudes from the gate region (line region other than the contact region) of the select gate electrode SGD (lower) is h, and the first layer adjacent in the column direction If the distance between the contact regions of the first select gate electrode SGD (lower) is k, k = n, and the distance between the gate regions of the first select gate electrode SGD (lower) adjacent in the column direction. Becomes k + 2h.
[0040]
In the example of FIG. 89, the length of the portion of the contact region protruding from the gate region of the select gate electrode SGD (lower) is h, and the first layer select gate electrode SGD (lower) adjacent in the column direction is When the minimum interval is m, n <m, and the interval between the gate regions of the first-layer select gate electrode SGD (lower) adjacent in the column direction is m + h.
[0041]
Note that m is larger than n because the misalignment of the second-layer select gate electrode SGD (upper), the contact region of the first-layer select gate electrode SGD (lower), and the select adjacent thereto. This is because misalignment of the gate electrode SGD (upper) must be taken into consideration.
[0042]
In any example, the interval between select gate electrodes (portions other than the contact region) adjacent in the column direction is larger than the minimum width n that can be processed in the photolithography process. This hinders an increase in the storage capacity of the memory cell array part (when the area is fixed) and a reduction in the area of the memory cell array part (when the storage capacity is fixed).
[0043]
As shown in FIGS. 90 and 91, if a misalignment of the resist occurs in the photolithography process during patterning of the contact region of the first-layer select gate electrode SGD (lower), the first-layer select A connection portion (indicated by a thick line) between the contact region of the gate electrode SGD (lower) and the gate region is narrowed, and the resistance of the first-layer select gate electrode SGD (lower) is increased.
[0044]
The present invention has been made to solve the above-described drawbacks, and an object of the present invention is to reduce the interval between the gate regions (line-shaped portions) of the select gate electrode of the select gate transistor regardless of the size of the contact region. It is to come up with a pattern that can.
[0045]
Another object of the present invention is not to increase the resistance of the first-layer select gate electrode even if a resist misalignment occurs in the photolithography process during patterning of the contact region for the first-layer select gate electrode. To come up with a pattern like this.
[0046]
[Means for Solving the Problems]
The nonvolatile semiconductor memory according to the present invention includes a plurality of memory cells connected in series along a predetermined direction on a semiconductor substrate, and a pair of select gate transistors connected to both ends of each of the memory cells. First and second NAND cell units disposed adjacent to each other in a direction, wherein the first and second NAND cell units share a drain diffusion layer or a source diffusion layer, and the first NAND cell unit includes The first select gate electrode of the select gate transistor on the drain diffusion layer side or the source diffusion layer side and the second select gate electrode of the select gate transistor in the second NAND cell unit adjacent to the first select gate electrode are respectively Provided on the semiconductor substrate via a gate insulating film, A first conductive layer extending in a crossing direction intersecting the first conductive layer, and a second conductive layer on the first conductive layer, wherein the first conductive layer of the first and second select gate electrodes is the first conductive layer. A plurality of contact regions for one conductive layer, and the second conductive layer of the first and second select gate electrodes is removed on the plurality of contact regions, and the first conductive layer of the first select gate electrode And the contact region of the second select gate electrode with respect to the first conductive layer are arranged so as not to face each other, and the width of the contact region of the first select gate electrode with respect to the first conductive layer in the predetermined direction is: The contact width of the second select gate electrode with respect to the first conductive layer is wider than the width of the first select gate electrode except the contact region in the predetermined direction. A width of the region in the predetermined direction is wider than a width of the second select gate electrode except the contact region in the predetermined direction, and a portion of the first select gate electrode facing the contact region with respect to the first conductive layer The first and second conductive layers of the second select gate electrode are removed, and the first and second first gate electrodes of the first select gate electrode at portions of the second select gate electrode facing the contact region with respect to the first conductive layer are removed. The conductive layer is removed, and the first conductive layer of the first select gate electrode is an upper layer than the second conductive layer via the contact region of the first conductive layer, and the NAND cell unit on the first select gate electrode side The first conductive layer of the second select gate electrode is connected to a first wiring disposed on the memory cell in the memory cell, The first conductive layer And a second wiring disposed on the memory cell in the NAND cell unit on the second select gate electrode side above the second conductive layer through the contact region.
[0058]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the nonvolatile semiconductor memory of the present invention will be described in detail with reference to the drawings.
[0059]
FIG. 1 schematically shows a planar pattern of a memory cell array portion of a NAND flash EEPROM according to the first embodiment of the present invention. FIG. 2 shows the area XD in FIG. 1 in an enlarged manner, and FIG. 3 shows the area XS in FIG. 1 in an enlarged manner. FIG. 4 is a cross-sectional view of the memory cell array portion of the NAND flash EEPROM of FIG.
[0060]
5 shows a plane pattern of the first wiring layer formed on the NAND cell unit, and FIG. 6 shows a plane pattern of the second wiring layer formed on the first wiring layer in FIG. Is shown.
[0061]
An element isolation film 49 having an STI (Shallow Trench Isolation) structure is formed in the silicon substrate 10. In the element region surrounded by the element isolation film 49, for example, a NAND cell unit including 16 memory cells and two select gate transistors is arranged.
[0062]
Each memory cell has a floating gate electrode FG, control gate electrodes (word lines) CG0 to CG15, and an N-type diffusion layer 61. The floating gate electrode FG is composed of polysilicon films 45 and 50, and the control gate electrodes (word lines) CG0 to CG15 are composed of polysilicon films 55 and 56 and a tungsten silicide film 57.
[0063]
The source side select gate transistor has select gate electrodes SGS (upper) and SGS (lower) and N-type diffusion layers 61 and 61a. The select gate electrode SGS (lower) is composed of polysilicon films 45 and 50, and the select gate electrode SGS (upper) is composed of polysilicon films 55 and 56 and a tungsten silicide film 57.
[0064]
The drain side select gate transistor also includes select gate electrodes SGD (upper) and SGD (lower) and N-type diffusion layers 61 and 61b. The select gate electrode SGS (lower) is composed of polysilicon films 45 and 50, and the select gate electrode SGS (upper) is composed of polysilicon films 55 and 56 and a tungsten silicide film 57.
[0065]
The control gate electrodes (word lines) CG0 to CG15, the source side select gate electrodes SGS (upper), SGS (lower) and the drain side select gate electrodes SGD (upper), SGD (lower) extend in the row direction, and the bit line BL0 ~ BLk extends in the column direction.
[0066]
For example, the bit lines BL0 to BLk are formed of a laminated film of a barrier metal 68 made of titanium and titanium nitride and a metal film (for example, an aluminum film) 69. The bit lines BL0 to BLk are connected to a diffusion layer (drain) 61b of the NAND cell unit through a wiring made of a tungsten film 66 (66B) formed immediately below the bit lines BL0 to BLk. A barrier metal 65 (65B) made of, for example, titanium and titanium nitride is formed between the tungsten film 66 and the diffusion layer 61b.
[0067]
The dummy bit line DUMMY is provided in order to make the capacitance between the bit lines BL0 to BLk uniform, and is not actually used.
[0068]
The source line SL is connected to the diffusion layer (source) 61a of the NAND cell unit. The source line SL is composed of, for example, a laminated film of a barrier metal 65 (65B) and a tungsten film 66 (66A) made of titanium and titanium nitride.
[0069]
The source side and drain side select gate transistors are provided for selecting memory cells to be written and erased during data writing and erasing, respectively. For this reason, unlike the memory cell, the source side and drain side select gate transistors are configured to perform a switching operation at a certain threshold value.
[0070]
Therefore, in the source-side and drain-side select gate transistors, the control signal is directly applied to the first-layer select gate electrodes SGS (lower) and SGD (lower). Specifically, part of the second-layer select gate electrodes SGS (upper) and SGD (upper) are removed, and the removed portions include first-layer select gate electrodes SGS (lower), A contact region for the SGD (bottom) is formed. Contact holes SS and SD are formed on the contact region.
[0071]
The hatched portions in FIGS. 2 and 3 indicate portions where the first-layer select gate electrodes SGS (lower) and SGD (lower) are present.
[0072]
One contact region (contact hole SS, SD) is provided every time the select gate electrode straddles several hundred bit lines in consideration of the resistance of the select gate electrode. For example, the contact region for the first-layer select gate electrode SGS (lower) of the source-side select gate transistor is provided in common to the two first-layer select gate electrodes SGS (lower) adjacent in the column direction. The contact region for the first-layer select gate electrode SGD (lower) of the drain-side select gate transistor is separately provided on two first-layer select gate electrodes SGD (lower) adjacent in the column direction. Yes.
[0073]
Regarding the drain-side select gate transistor, the contact regions for the two first-layer select gate electrodes SGD (lower) adjacent in the column direction do not face each other (that is, the contact regions of both select gate electrodes SGD (lower)) Are arranged alternately so that they do not touch.
[0074]
Here, the important point regarding the drain side select gate transistor is that of the two select gate electrodes SGD (lower) adjacent to each other in the column direction, the other of the portions facing the contact region for one select gate electrode SGD (lower) The select gate electrodes SGD (upper) and SGD (lower) are removed. Thereby, even if the interval between the select gate electrodes SGD (lower) is narrowed, the contact region for one select gate electrode SGD (lower) is in contact with the other select gate electrodes SGD (upper) and SGD (lower). There is no.
[0075]
That is, according to this example, one select gate electrode SGD (upper), SGD (lower) is cut at a portion facing the contact region with respect to the other select gate electrode SGD (lower).
[0076]
Therefore, the cut select gate electrodes SGD (lower) are electrically connected by the upper wiring SDL1 or the wiring SDL2. The wirings SDL1 and SDL2 are formed in the same layer as the layer where the source line SL is formed, and are composed of, for example, a barrier metal 65 (65C) made of titanium and titanium nitride and a tungsten film 66 (66C).
[0077]
On the other hand, the contact region for the two select gate electrodes SGS (lower) adjacent in the column direction of the source side select gate transistor is commonly connected to the wiring SSL via the wirings 66D and 95 (contact holes SS1 and SS2). Yes.
[0078]
The wirings 66D and SSL are formed in the same layer as the layer where the source line SL is formed, and are composed of, for example, a barrier metal 65 (65D, 65E) made of titanium and titanium nitride and a tungsten film 66 (66D, 66E). . The wiring 95 is formed in the same layer as the layer in which the bit lines BL0 to BLk are formed, and includes a barrier metal 68 made of titanium and titanium nitride and a metal film (for example, an aluminum film) 69, for example.
[0079]
FIG. 7 schematically shows a planar pattern of the memory cell array portion of the NAND flash EEPROM according to the second embodiment of the present invention. 8 shows the area XD in FIG. 7 in an enlarged manner, and FIG. 9 shows the area XS in FIG. 7 in an enlarged manner.
[0080]
Further, FIG. 10 shows a plane pattern of the first wiring layer formed on the NAND cell unit, and FIG. 11 shows a plane pattern of the second wiring layer formed on the first wiring layer in FIG. Is shown.
[0081]
Note that the cross section of the memory cell array portion of the NAND flash EEPROM of FIG. 7 is the same as that of FIG.
[0082]
An element isolation film 49 having an STI (Shallow Trench Isolation) structure is formed in the silicon substrate 10. In the element region surrounded by the element isolation film 49, for example, a NAND cell unit including 16 memory cells and two select gate transistors is arranged.
[0083]
Each memory cell has a floating gate electrode FG, control gate electrodes (word lines) CG0 to CG15, and an N-type diffusion layer 61. The floating gate electrode FG is composed of polysilicon films 45 and 50, and the control gate electrodes (word lines) CG0 to CG15 are composed of polysilicon films 55 and 56 and a tungsten silicide film 57.
[0084]
The source side select gate transistor has select gate electrodes SGS (upper) and SGS (lower) and N-type diffusion layers 61 and 61a. The select gate electrode SGS (lower) is composed of polysilicon films 45 and 50, and the select gate electrode SGS (upper) is composed of polysilicon films 55 and 56 and a tungsten silicide film 57.
[0085]
The drain side select gate transistor also includes select gate electrodes SGD (upper) and SGD (lower) and N-type diffusion layers 61 and 61b. The select gate electrode SGS (lower) is composed of polysilicon films 45 and 50, and the select gate electrode SGS (upper) is composed of polysilicon films 55 and 56 and a tungsten silicide film 57.
[0086]
The control gate electrodes (word lines) CG0 to CG15, the source side select gate electrodes SGS (upper), SGS (lower) and the drain side select gate electrodes SGD (upper), SGD (lower) extend in the row direction, and the bit line BL0 ~ BLk extends in the column direction.
[0087]
For example, the bit lines BL0 to BLk are formed of a laminated film of a barrier metal 68 made of titanium and titanium nitride and a metal film (for example, an aluminum film) 69. The bit lines BL0 to BLk are connected to a diffusion layer (drain) 61b of the NAND cell unit through a wiring made of a tungsten film 66 (66B) formed immediately below the bit lines BL0 to BLk. A barrier metal 65 (65B) made of, for example, titanium and titanium nitride is formed between the tungsten film 66 and the diffusion layer 61b.
[0088]
The dummy bit line DUMMY is provided in order to make the capacitance between the bit lines BL0 to BLk uniform, and is not actually used.
[0089]
The source line SL is connected to the diffusion layer (source) 61a of the NAND cell unit. The source line SL is composed of a laminated film of a barrier metal 65 (65A) and a tungsten film 66 (66A) made of, for example, titanium and titanium nitride.
[0090]
The source side and drain side select gate transistors are provided for selecting memory cells to be written and erased during data writing and erasing, respectively. For this reason, unlike the memory cell, the source side and drain side select gate transistors are configured to perform a switching operation at a certain threshold value.
[0091]
Therefore, in the source-side and drain-side select gate transistors, the control signal is directly applied to the first-layer select gate electrodes SGS (lower) and SGD (lower). Specifically, part of the second-layer select gate electrodes SGS (upper) and SGD (upper) are removed, and the removed portions include first-layer select gate electrodes SGS (lower), A contact region for the SGD (bottom) is formed. Contact holes SS and SD are formed on the contact region.
[0092]
The hatched portions in FIGS. 8 and 9 indicate portions where the first-layer select gate electrodes SGS (lower) and SGD (lower) are present.
[0093]
One contact region (contact hole SS, SD) is provided every time the select gate electrode straddles several hundred bit lines in consideration of the resistance of the select gate electrode. Also, the contact region for the first-layer select gate electrode SGS (lower) of the source-side select gate transistor is different from the first embodiment described above in that the two first-layer select adjacent to the column direction are selected. Separately provided on the gate electrode SGS (lower), the contact region for the first-layer select gate electrode SGD (lower) of the drain side select gate transistor is also connected to the two select gate electrodes SGD (lower) adjacent in the column direction. It is provided separately.
[0094]
Regarding the drain-side select gate transistor, the contact regions for the two first-layer select gate electrodes SGD (lower) adjacent in the column direction do not face each other (that is, the contact regions of both select gate electrodes SGD (lower)) Are arranged alternately so that they do not overlap.
[0095]
Similarly, with respect to the source side select gate transistor, the contact regions for the two first-layer select gate electrodes SGS (lower) adjacent in the column direction are also not opposed to each other (that is, both select gate electrodes SGS (lower)). Are arranged alternately so that the contact areas do not overlap.
[0096]
In addition, regarding the drain side select gate transistor, of the two select gate electrodes SGD (lower) adjacent in the column direction, the other select gate electrode SGD ( Top), SGD (bottom) is removed. As a result, even if the distance between the select gate electrodes SGD (lower) becomes narrow, the contact region for one select gate electrode SGD (lower) contacts the other select gate electrodes SGD (upper) and SGD (lower). There is no.
[0097]
Further, regarding the source side select gate transistor, of the two select gate electrodes SGS (lower) adjacent in the column direction, the other select gate electrode SGS ( Top), SGS (bottom) are removed. As a result, even if the distance between the select gate electrodes SGS (lower) is reduced, the contact region for one select gate electrode SGS (lower) is in contact with the other select gate electrodes SGS (upper) and SGS (lower). There is no.
[0098]
Thus, in this example, the source-side and drain-side select gate electrodes are cut at predetermined positions, respectively.
[0099]
The drain-side select gate electrode cut in this way is electrically connected by the upper layer wiring SDL1 or SDL2. The wirings SDL1 and SDL2 are formed in the same layer as the layer where the source line SL is formed, and are composed of, for example, a barrier metal 65 (65C) made of titanium and titanium nitride and a tungsten film 66 (66C).
[0100]
On the other hand, the contact region for the two select gate electrodes SGS (lower) adjacent in the column direction of the source side select gate transistor is commonly connected to the wiring SSL via the wirings 66D and 95 (contact holes SS1 and SS2). Yes.
[0101]
The wirings 66D and SSL are formed in the same layer as the layer where the source line SL is formed, and are composed of, for example, a barrier metal 65 (65D, 65E) made of titanium and titanium nitride and a tungsten film 66 (66D, 66E). . The wiring 95 is formed in the same layer as the layer in which the bit lines BL0 to BLk are formed, and includes a barrier metal 68 made of titanium and titanium nitride and a metal film (for example, an aluminum film) 69, for example.
[0102]
12 and 13 show a memory cell array portion of a NAND flash EEPROM according to the third embodiment of the present invention. This example is a modification of the above-described second embodiment, FIG. 12 is a modification of the planar pattern of the first wiring layer of FIG. 10, and FIG. 13 is the second wiring of FIG. It is a modification of the plane pattern of a layer.
[0103]
The cross section of the memory cell array portion of the NAND flash EEPROM of this example is the same as that in FIG.
[0104]
Of the two select gate electrodes SGS (upper) and SGS (lower) adjacent in the column direction with respect to the source side select gate transistor, one select gate electrode SGS (upper) and SGS (lower) is the other select gate electrode. It is cut at a portion facing the contact region of SGS (bottom).
[0105]
In addition, the cut select gate electrode SGS (lower) is electrically connected by an upper layer wiring SSL1 or SSL2 via a contact region. That is, in this example, unlike the second embodiment described above, two select gate electrodes SGS (upper) and SGS (lower) adjacent in the column direction are connected to different wirings SSL1 and SSL2, respectively.
[0106]
As a result, in this example, it is possible to control on / off of the select gate transistors on the source side and the drain side of the NAND cell unit for each block.
[0107]
The wirings SSL1 and SSL2 are formed in the same layer as the layer where the source line SL is formed, and are composed of, for example, a barrier metal 65 (65E) made of titanium and titanium nitride and a tungsten film 66 (66E).
[0108]
According to the pattern of the memory cell array portion of the NAND flash EEPROM according to the first to third embodiments described above, first, regarding two select gate electrodes adjacent in the column direction, the contact region of both select gate electrodes. Are arranged so as not to face each other. One select gate electrode is cut at a portion facing the contact region of the other select gate electrode.
[0109]
Therefore, the interval between the gate regions (line regions other than the contact region) of the two select gate electrodes adjacent in the column direction can be narrowed regardless of the size of the contact region.
[0110]
Specifically, as shown in FIG. 14, the minimum width that can be processed in the photolithography process is n (for example, the interval between the control gate electrodes is set to n), and the contact region is a select gate electrode SGD ( If the length of the portion protruding from the lower gate region in the column direction is h and the distance between the contact region of the select gate electrode SGD (lower) and the control gate electrode CG0 adjacent thereto is m, it is adjacent in the column direction. In principle, the distance p between the gate regions of the two select gate electrodes can be reduced to the minimum value n regardless of the size of the contact region (however, it is necessary to satisfy n <m).
[0111]
As a result, the size of the memory cell array portion in the column direction can be reduced by 9 to 10% compared to the conventional case, the storage capacity of the memory cell array portion is increased (when the area is fixed), and the area of the memory cell array portion is reduced. (When the storage capacity is fixed).
[0112]
The select gate electrodes (first layer) cut at a plurality of locations are connected to each other by an upper layer wiring through a contact region. If this wiring is made of a low-resistance material, for example, a barrier metal made of titanium and titanium nitride and a tungsten film, it can contribute to lowering the resistance of the select gate electrode.
[0113]
Second, in the portion where the contact region for the first layer select gate electrode is formed, the second layer select gate electrode is removed. In the pattern in the vicinity, the length r in the column direction is larger than the gate length g of the select gate electrode (for example, it is bent at 90 ° in the column direction). Naturally, the first-layer select gate electrode exists immediately below the second-layer select gate electrode.
[0114]
Therefore, for example, as shown in FIG. 15, even when resist misalignment occurs in the photolithography process during the patterning of the contact region of the first-layer select gate electrode, the contact of the first-layer select gate electrode The connection portion (indicated by a thick line) between the region and the gate region is not narrowed, and the resistance value of the first-layer select gate electrode does not increase.
[0115]
Next, a manufacturing method of the memory cell array part of the NAND flash EEPROM described above will be described.
[0116]
First, as shown in FIG. 16, a silicon oxide film 41a having a thickness of about 10 nm is formed on the p-type silicon substrate 40 by, for example, thermal oxidation.
[0117]
Next, as shown in FIG. 17, n-type impurities (for example, phosphorus (P)) are ion-implanted into the silicon substrate 40 using an n-well formation mask to form an n-well region 42. . Here, the formation of the n-well region 42 is realized by, for example, three-stage ion implantation. That is, in the first stage, for example, an acceleration energy of 1.5 [MeV], 4.0 × 10 ¹² cm ^-2 Phosphorus is ion-implanted into the silicon substrate at a dose of 750 [KeV] in the second stage, for example, an acceleration energy of 750 [KeV], 8.0 × 10 ¹² cm ^-2 In the third stage, phosphorus is ion-implanted into the silicon substrate with a dose amount of, for example, 150 [KeV] acceleration energy, 1.0 × 10 6. ¹² cm ^-2 Phosphorus is ion-implanted into the silicon substrate with a dose amount of.
[0118]
Further, a p-well region 43 is formed by ion-implanting a p-type impurity (for example, boron (B)) into the silicon substrate 40 using a p-well formation mask. Here, the formation of the p-well region 43 is realized by, for example, two-stage ion implantation. That is, in the first stage, for example, acceleration energy of 400 [KeV], 4.0 × 10 ¹³ cm ^-2 Boron is ion-implanted into the silicon substrate at a dose of about 200 [KeV] in the second stage, for example, 1.0 × 10 ¹² cm ^-2 Boron is ion-implanted into the silicon substrate at a dose of.
[0119]
In the p-well region 43, a p-field region 44 having a higher impurity concentration than the p-well region 43 is formed. Thereafter, the silicon oxide film 41a is removed.
[0120]
Next, as shown in FIG. 18, thermal oxidation is performed in an oxygen atmosphere at a temperature of about 750 ° C. to form a silicon oxide film 41 having a thickness of about 8 nm on the silicon substrate 40. Further, for example, an n-type impurity (for example, phosphorus) is about 2 × 10 × on the silicon oxide film 41 by using the CVD method. ²⁰ cm ^-3 An n-type polysilicon film 45 having a thickness of about 60 nm is formed.
[0121]
Thereafter, a silicon nitride film 46 having a thickness of about 150 nm is further formed on the polysilicon film 45 by using, for example, a CVD method. Subsequently, a silicon oxide film 47 having a thickness of about 100 nm is formed on the silicon nitride film 46 by using, for example, a CVD method.
[0122]
Next, as shown in FIG. 19, a resist pattern is formed on the silicon oxide film 47 by PEP (photographic etching process). Using this resist pattern as a mask, the silicon oxide film 47 is etched by RIE (reactive ion etching). Further, after the silicon nitride film 46 is etched by the RIE method using the silicon oxide film 47 as a mask, the silicon oxide film 47 is removed.
[0123]
Thereafter, the polysilicon film 45 and the silicon oxide film 41 are sequentially etched by the RIE method using the silicon nitride film 46 as a mask. Further, the silicon substrate 40 is etched using the silicon nitride film 46 as a mask to form a trench 48 with a bottom reaching the p-field region 44 in the silicon substrate 40.
[0124]
Next, as shown in FIG. 20, a TEOS film 49 having a thickness of about 820 nm so as to completely fill the trench 48 is formed on the silicon nitride film 46 by using, for example, a CVD method. Thereafter, the TEOS film 49 is polished by using a CMP (Chemical Mechanical Polishing) method, and the TEOS film 49 is left only in the trench 48 to complete an STI (Shallow Trench Isolation) structure.
[0125]
Since the silicon nitride film 46 functions as an etching stopper at the time of CMP, the surface of the TEOS film 49 substantially coincides with the surface of the silicon nitride film 46 (generally, the surface of the TEOS film 49 is silicon nitride). A little lower than the surface of the membrane 46). Thereafter, the silicon nitride film 46 is removed.
[0126]
Next, as shown in FIG. 21, an n-type impurity (for example, phosphorus) is added to the polysilicon film 45 by about 2 × 10 4 using, for example, a CVD method. ²⁰ cm ^-3 An n-type polysilicon film 50 having a thickness of about 100 nm is formed.
[0127]
Next, as shown in FIG. 22, a silicon nitride film 51 having a thickness of about 200 nm is formed on the polysilicon film 50 by, eg, CVD. Further, the silicon nitride film 51 is patterned to form slits extending in the column direction in the silicon nitride film 51 except for regions where the source side and drain side select gate transistors are formed. The slit width (width in the row direction) is 200 to 300 nm.
[0128]
Further, a silicon nitride film 52 having a thickness of about 80 nm is formed on the silicon nitride film 51 by CVD. When this silicon nitride film 52 is etched by RIE, the silicon nitride film 52 remains only on the side wall of the slit of the silicon nitride film 51.
[0129]
Thereafter, when the polysilicon film 50 is etched by RIE using the silicon nitride films 51 and 52 as a mask, a slit-like opening 53 is formed in the polysilicon film 50 as shown in FIG. Here, since the width of the opening 53 (the width in the row direction) is narrower than the width (the width in the row direction) of the TEOS film 49 that realizes the STI structure, the polysilicon films 45 and 50 serving as floating gates are It has become a wing shape.
[0130]
Thereafter, the silicon nitride films 51 and 52 are removed.
[0131]
Next, as shown in FIG. 24, an insulating film 54 is formed on the polysilicon film 50. The insulating film 54 is composed of, for example, a silicon oxide film having a thickness of about 5 nm, a silicon nitride film having a thickness of about 8 nm, and a silicon oxide film having a thickness of about 5 nm (so-called ONO film). Further, for example, about 3.6 × 10 6 is formed on the insulating film 54 by the CVD method. ²⁰ cm ^-3 A polysilicon film 55 having a thickness of about 200 nm containing n-type impurities (for example, phosphorus) is formed.
[0132]
Next, as shown in FIG. 25, a polysilicon film 56 having a thickness of about 100 nm containing an n-type impurity is formed on the polysilicon film 55 by using, for example, a CVD method. Further, for example, a tungsten silicide (WSi) film 57 having a thickness of about 100 nm is formed on the polysilicon film 56 by using the CVD method. Subsequently, a silicon nitride film 58 having a thickness of about 280 nm is formed on the tungsten silicide film 57 by CVD. Also, a silicon oxide film (TEOS film) 59 having a thickness of about 50 nm is formed on the silicon nitride film 58 by CVD.
[0133]
Thereafter, a resist pattern is formed on the silicon oxide film 59 by PEP (photo etching process), and the silicon oxide film 59 is etched by RIE using the resist pattern as a mask. Further, after the silicon nitride film 58 is etched by RIE using the silicon oxide film 59 as a mask, the silicon oxide film 59 is removed.
[0134]
Next, as shown in FIGS. 26 to 28, the tungsten silicide film 57 and the polysilicon films 56 and 55 are sequentially etched by RIE using the patterned silicon nitride film 58 as a mask. Thereby, the control gate electrodes CG0 to CG15 and the select gate electrodes SGS (upper) and SGD (upper) extending in the row direction are completed.
[0135]
Here, the select gate electrodes SGS (upper) and SGD (upper) are formed in a pattern in which the part where the contact region is arranged is removed and the part is bent at 90 ° in the column direction. Further, in the portion where the contact region is disposed, the adjacent select gate electrodes SGS (upper) and SGD (upper) are also removed.
[0136]
Next, as shown in FIGS. 29 to 33, a resist pattern 90 is formed on the portion where the contact region is to be formed by PEP. Using the resist pattern 90 and the silicon nitride film 58 as a mask, the insulating film 54 and the polysilicon films 50 and 45 are sequentially etched by RIE. Thereby, the floating gate electrode FG extending in the row direction and the select gate electrodes SGS (lower) and SGD (lower) (gate region and contact region) are completed. Thereafter, the resist pattern 90 is removed.
[0137]
Next, as shown in FIG. 34, n-type impurities (phosphorus or arsenic) are ion-implanted into the p-well region 43 by self-alignment using the silicon nitride film 58 (control gate electrode and select gate) as a mask. N-type diffusion layers 61, 61a, 61b are formed. The diffusion layer 61a becomes the source of the NAND cell unit, and the diffusion layer 61b becomes the drain of the NAND cell unit.
[0138]
Further, for example, a silicon nitride film 60 having a thickness of about 60 nm is formed as a spacer on the sidewalls of the control gate electrodes CG0 to CG15, the select gate electrodes SGS and SGD, and the floating gate electrode FG by using the CVD method.
[0139]
Next, as shown in FIG. 35, a BPSG film 62 having a thickness of about 1.45 μm is formed on the silicon nitride film 60. Further, the CMP process is used to polish the BPSG film 62 by about 0.4 μm to flatten the surface of the BPSG film 62.
[0140]
Next, as shown in FIGS. 36 to 42, a silicon nitride film 91 as an etching stopper is formed on the BPSG film 62. Subsequently, a TEOS film 64 is formed on the silicon nitride film 91.
[0141]
Further, a resist pattern is formed by PEP. Using this resist pattern as a mask, the TEOS film 64 is etched by RIE to form a wiring groove in the TEOS film 64. At this time, the silicon nitride film 91 functions as an etching stopper in RIE. Thereafter, the resist pattern is removed.
[0142]
Again, a resist pattern is formed by PEP. Using this resist pattern as a mask, contact holes S and D reaching the diffusion layer (source) 61a and the diffusion layer (drain) 61b are formed in the BPSG film 62, the silicon nitride film 60, and the silicon oxide film 41 by RIE. At the same time, contact holes SS and SD reaching the contact regions of the first-layer select gate electrodes SGS (lower) and SGD (lower) are formed by this RIE. Thereafter, the resist pattern is removed.
[0143]
Thereafter, barrier metals 65A to 65E made of, for example, a laminate of titanium and titanium nitride are formed on the inner surface of the wiring groove and the inner surface of the contact hole. Further, on the TEOS film 64, tungsten films 66A to 66E that completely fill the wiring grooves and contact holes are formed. When the tungsten films 66A to 66E are polished by CMP and left only in the wiring trench and the contact hole, the source wiring SL connected to the source of the NAND cell unit, the wiring 65B connected to the drain of the NAND cell unit, 66B, the wiring SDL connected to the drain side select gate electrode SGD (lower), and the other wirings 65D, 66D, and SSL are formed.
[0144]
Next, as shown in FIGS. 43 to 45, a TEOS film 92 is formed on the TEOS film 64. A silicon nitride film 93 as an etching stopper is formed on the TEOS film 92. Subsequently, a TEOS film 94 is formed on the silicon nitride film 93.
[0145]
Further, a resist pattern is formed by PEP. Using this resist pattern as a mask, the TEOS film 94 is etched by RIE, and wiring grooves for bit lines, dummy bit lines, and the like are formed in the TEOS film 94. At this time, the silicon nitride film 93 functions as an etching stopper in RIE. Thereafter, the resist pattern is removed.
[0146]
Again, a resist pattern is formed by PEP. Using this resist pattern as a mask, contact holes B reaching the wirings 65B and 66B and other contact holes SS1 and SS2 are formed in the silicon nitride film 93 and the TEOS film 92 by RIE. Thereafter, the resist pattern is removed.
[0147]
Thereafter, a barrier metal 68 made of, for example, a laminate of titanium and titanium nitride is formed on the inner surface of the wiring groove and the inner surface of the contact hole. Further, a metal film (for example, an aluminum film) 69 that completely fills the wiring trench and the contact hole is formed on the TEOS film 94. When this metal film 69 is polished by the CMP method and left only in the wiring trench and the contact hole, a wiring 95 for connecting the plurality of bit lines BL and the source side select gate electrode SGS (lower) to the wiring SSL is formed. It is formed.
[0148]
A passivation film made of a silicon nitride film is formed on these wirings.
[0149]
The NAND flash EEPROM is completed through the above manufacturing process.
[0150]
【The invention's effect】
As described above, the nonvolatile semiconductor memory of the present invention has the following effects.
[0151]
First, regarding two select gate electrodes (source side and drain side) adjacent in the column direction, the contact regions of both select gate electrodes are arranged so as not to face each other. One select gate electrode is cut at a portion facing the contact region of the other select gate electrode.
[0152]
Therefore, the interval between the gate regions (line regions other than the contact regions) of the two select gate electrodes adjacent in the column direction can be narrowed regardless of the size of the contact regions, and the storage capacity of the memory cell array portion can be increased. This can contribute to reducing the area of the memory cell array portion.
[0153]
The select gate electrodes (first layer) cut at a plurality of locations are connected to each other by an upper layer wiring through a contact region. If this wiring is made of a low-resistance material, for example, a barrier metal made of titanium and titanium nitride and a tungsten film, it can contribute to lowering the resistance of the select gate electrode.
[0154]
Second, in the portion where the contact region for the first layer select gate electrode is formed, the second layer select gate electrode is removed. In the neighboring pattern, the length r in the column direction is larger than the gate length g of the select gate electrode (for example, it is bent at 90 ° in the column direction). Naturally, the first-layer select gate electrode exists immediately below the second-layer select gate electrode.
[0155]
Therefore, even when resist misalignment occurs in the photolithography process during patterning of the contact region of the first-layer select gate electrode, the connection area between the contact region of the first-layer select gate electrode and the gate region is narrow. The resistance value of the select gate electrode of the first layer does not increase.
[Brief description of the drawings]
FIG. 1 is a diagram showing an outline of a plane pattern of a NAND type EEPROM according to a first embodiment of the present invention.
FIG. 2 is an enlarged view showing a region XD in FIG.
FIG. 3 is an enlarged view showing a region XS in FIG. 1;
4 is a cross-sectional view of the NAND type EEPROM of FIG. 1;
FIG. 5 is a view showing a planar pattern of a first wiring layer of the EEPROM of FIG. 1;
6 is a view showing a planar pattern of a second wiring layer of the EEPROM of FIG. 1; FIG.
FIG. 7 is a diagram showing an outline of a planar pattern of a NAND-type EEPROM according to a second embodiment of the present invention.
8 is an enlarged view showing a region XD in FIG.
9 is an enlarged view showing a region XS in FIG.
10 is a diagram showing a planar pattern of a first wiring layer of the EEPROM of FIG. 7;
11 is a view showing a planar pattern of a second wiring layer of the EEPROM of FIG. 7;
FIG. 12 is a diagram showing a planar pattern of a first wiring layer of an EEPROM according to the third embodiment of the present invention.
FIG. 13 is a diagram showing a planar pattern of a second wiring layer of an EEPROM according to the third embodiment of the present invention.
FIG. 14 is a diagram showing reduction between select gates, which is the first effect of the present invention.
FIG. 15 is a diagram showing a decrease in resistance of a contact region, which is a second effect of the present invention.
FIG. 16 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.
FIG. 17 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.
FIG. 18 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.
FIG. 19 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.
FIG. 20 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.
FIG. 21 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.
FIG. 22 is a sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.
FIG. 23 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.
FIG. 24 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.
FIG. 25 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.
FIG. 26 is a plan view showing one step in a method of manufacturing an EEPROM according to the present invention.
FIG. 27 is a plan view showing one step in a method for manufacturing an EEPROM according to the present invention;
FIG. 28 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.
FIG. 29 is a plan view showing one step in a method of manufacturing an EEPROM according to the present invention.
30 is a plan view showing one step in a method for manufacturing an EEPROM according to the present invention. FIG.
FIG. 31 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.
32 is a sectional view taken along line XXXII-XXXII in FIG. 29. FIG.
33 is a sectional view taken along line XXXIII-XXXIII in FIG.
34 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention. FIG.
FIG. 35 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.
36 is a plan view showing one step in a method for manufacturing an EEPROM according to the present invention. FIG.
FIG. 37 is a plan view showing one step in a method for manufacturing an EEPROM according to the present invention.
FIG. 38 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.
FIG. 39 is a cross-sectional view taken along line XXXIX-XXXIX in FIG. 36;
40 is a sectional view taken along line XL-XL in FIG. 36. FIG.
41 is a sectional view taken along line XLI-XLI in FIG.
42 is a sectional view taken along line XLII-XLII in FIG. 37. FIG.
43 is a plan view showing one step in a method for manufacturing an EEPROM according to the present invention. FIG.
44 is a plan view showing one step in a method for manufacturing an EEPROM according to the present invention. FIG.
FIG. 45 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.
FIG. 46 is a circuit diagram showing a configuration of a memory cell array portion of a NAND type EEPROM;
47 is a diagram showing an outline of a planar pattern of a NAND type EEPROM. FIG.
48 is an enlarged view showing a region XD in FIG. 47. FIG.
49 is an enlarged view showing a region XS in FIG. 47. FIG.
50 is a view showing a cross section of the NAND-type EEPROM shown in FIG. 47;
FIG. 51 is a diagram showing an outline of a planar pattern of a NAND type EEPROM;
52 is a plan view showing one step in a method for manufacturing an EEPROM. FIG.
FIG. 53 is a plan view showing one step in a method for manufacturing an EEPROM.
54 is a sectional view taken along the line LIV-LIV in FIG. 52. FIG.
55 is a sectional view taken along line LV-LV in FIG.
56 is a sectional view taken along line LVI-LVI in FIG. 52;
57 is a cross-sectional view taken along line LVII-LVII in FIG. 52. FIG.
FIG. 58 is a plan view showing one step in a method for manufacturing an EEPROM.
FIG. 59 is a plan view showing one step in a method for manufacturing an EEPROM.
60 is a sectional view taken along line LX-LX in FIG. 58. FIG.
61 is a sectional view taken along line LXI-LXI in FIG. 58. FIG.
62 is a sectional view taken along line LXII-LXII in FIG. 58;
63 is a sectional view taken along line LXIII-LXIII in FIG. 58. FIG.
64 is a sectional view taken along line LXIV-LXIV in FIG.
65 is a sectional view taken along line LXV-LXV in FIG. 59. FIG.
66 is a plan view showing one step in a method for manufacturing an EEPROM. FIG.
67 is a plan view showing one step in a method for manufacturing an EEPROM. FIG.
68 is a sectional view taken along line LXVIII-LXVIII in FIG. 66. FIG.
69 is a sectional view taken along line LXIX-LXIX in FIG. 66;
70 is a sectional view taken along line LXX-LXX in FIG. 66. FIG.
71 is a sectional view taken along line LXXI-LXXI in FIG. 66. FIG.
72 is a cross-sectional view taken along the line LXXII-LXXII in FIG. 66;
73 is a sectional view taken along line LXXIII-LXXIII in FIG. 67. FIG.
74 is a cross-sectional view taken along line LXXIV-LXXIV in FIG. 67;
75 is a cross-sectional view taken along line LXXV-LXXV in FIG. 67;
76 is a sectional view taken along line LXXVI-LXXVI in FIG. 67. FIG.
77 is a sectional view taken along line LXXVII-LXXVII in FIG. 67. FIG.
78 is a plan view showing one step in a method for manufacturing an EEPROM. FIG.
FIG. 79 is a plan view showing one step in a method for manufacturing an EEPROM.
80 is a cross-sectional view taken along line LXXX-LXXX in FIG. 78.
81 is a sectional view taken along line LXXXI-LXXXI in FIG. 78. FIG.
82 is a cross-sectional view taken along line LXXXII-LXXXII in FIG. 78.
83 is a sectional view taken along line LXXXIII-LXXXIII in FIG. 78. FIG.
84 is a sectional view taken along line LXXXIV-LXXXIV in FIG. 79;
85 is a cross-sectional view taken along line LXXXV-LXXXV in FIG. 79;
86 is a sectional view taken along line LXXXVI-LXXXVI in FIG. 79;
87 is a cross-sectional view taken along line LXXXVII-LXXXVII in FIG. 79;
FIG. 88 is a diagram showing a distance between select gates as a first conventional problem.
FIG. 89 is a diagram showing a distance between select gates as a first conventional problem.
FIG. 90 is a diagram showing misalignment of a contact region as a second conventional problem.
FIG. 91 is a view showing misalignment of a contact region as a second conventional problem.
[Explanation of symbols]
10, 40: silicon substrate,
11: element isolation film,
12: n-type diffusion layer,
12a: source diffusion layer,
12b: drain diffusion layer,
13: Gate insulating film,
14: floating gate electrode,
15: Insulating film (ONO film),
16: Polysilicon film,
17: Silicon nitride film (mask material),
18A, 18B: resist pattern,
19: BPSG film,
20, 35, 91, 93: silicon nitride film (etching stopper),
21, 34, 36: TEOS film,
22A-22F, 37A, 70A: wiring groove,
23A-23F, 37B, 70B: contact holes,
24, 26, 28, 30, 32, 38, 65, 68, 71: barrier metal (Ti / TiN),
25, 27, 29, 31, 33: tungsten film,
39, 69, 72: metal film,
42: n-well region,
43: p-well region,
44: p-field region,
45, 50, 55, 56, 63: polysilicon film,
46, 51, 52, 58, 60: silicon nitride film,
47, 59: silicon oxide film,
48: Trench,
49: Element isolation film (STI),
64, 92, 94: TEOS film,
53: slit,
54: Insulating film (ONO film),
57: Tungsten silicide film,
61: n-type diffusion layer,
61a: source diffusion layer,
61b: drain diffusion layer,
62: BPSG film,
66, 67: tungsten film,
95: Wiring,
CG0 to CG15: control gate electrodes,
SGS (bottom): source-side select gate electrode of the first layer,
SGD (bottom): drain-side select gate electrode of the first layer,
SGS (upper): second layer source side select gate electrode,
SGD (upper): drain-side select gate electrode of the second layer,
S, D, SS, SD, B, SS1, SS2: contact hole,
BL0 to BLk, BLi: bit lines
SL: Source line.
SSL, SSL1, SSL2: wiring connected to the source side select gate electrode,
SDL1, SDL2: wirings connected to the drain side select gate electrode.

Claims (5)

A plurality of memory cells connected in series along a predetermined direction on a semiconductor substrate and a pair of select gate transistors connected one by one to both ends thereof are arranged adjacent to each other in the predetermined direction. A non-volatile semiconductor memory having first and second NAND cell units, wherein the first and second NAND cell units share a drain diffusion layer or a source diffusion layer;
The first select gate electrode of the select gate transistor on the drain diffusion layer side or the source diffusion layer side in the first NAND cell unit, and the select gate transistor in the second NAND cell unit adjacent to the first select gate electrode Each of the second select gate electrodes is provided on the semiconductor substrate via a gate insulating film, and extends in a crossing direction intersecting the predetermined direction, and a second conductive layer on the first conductive layer. Composed of a conductive layer,
The first conductive layer of the first and second select gate electrodes has a plurality of contact regions with respect to the first conductive layer, and the second conductive layer of the first and second select gate electrodes is the plurality of contact regions. Removed on the contact area of
The contact region for the first conductive layer of the first select gate electrode and the contact region for the first conductive layer of the second select gate electrode are disposed so as not to face each other,
The width of the contact region of the first select gate electrode with respect to the first conductive layer in the predetermined direction is wider than the width of the portion of the first select gate electrode except the contact region in the predetermined direction. The width in the predetermined direction of the contact region with respect to the first conductive layer of the electrode is wider than the width in the predetermined direction of the portion excluding the contact region of the second select gate electrode,
The first and second conductive layers of the second select gate electrode in a portion opposite to the contact region of the first select gate electrode with respect to the first conductive layer are removed, and the contact of the second select gate electrode with the first conductive layer is removed. The first and second conductive layers of the first select gate electrode in a portion facing the region are removed;
The first conductive layer of the first select gate electrode is above the second conductive layer and above the memory cell in the NAND cell unit on the first select gate electrode side through the contact region of the first conductive layer. The first conductive layer of the second select gate electrode is connected to the first wiring disposed, and the second select gate electrode side is higher than the second conductive layer through the contact region of the first conductive layer. A non-volatile semiconductor memory, wherein the non-volatile semiconductor memory is connected to a second wiring disposed on a memory cell in the NAND cell unit.   2. The nonvolatile semiconductor memory according to claim 1, wherein the first and second select gate electrodes constitute a drain side select gate transistor.   2. The nonvolatile semiconductor memory according to claim 1, wherein the first and second select gate electrodes constitute a source side select gate transistor.   4. The nonvolatile semiconductor memory according to claim 1, wherein an interval between the first and second select gate electrodes is equal to an interval between a plurality of word lines in the NAND cell unit. 5.   5. The contact region of the first select gate electrode with respect to the first conductive layer and the contact region of the second select gate electrode with respect to the first conductive layer are arranged at regular intervals, respectively. The non-volatile semiconductor memory of any one of Claims.

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