CN116169115B - Embedded chip packaging module structure and manufacturing method thereof - Google Patents
Embedded chip packaging module structure and manufacturing method thereof Download PDFInfo
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- CN116169115B CN116169115B CN202211645110.4A CN202211645110A CN116169115B CN 116169115 B CN116169115 B CN 116169115B CN 202211645110 A CN202211645110 A CN 202211645110A CN 116169115 B CN116169115 B CN 116169115B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Abstract
The invention discloses a buried chip packaging module structure and a manufacturing method thereof, wherein the buried chip packaging module structure comprises a packaging carrier plate, a chip embedded in the packaging carrier plate, protruding points connected between the chip and the packaging carrier plate, and a protective layer embedded in the packaging carrier plate and covering the chip; the packaging carrier plate comprises a body and a groove arranged in the middle of the body; the body is exposed to the bottom surface of the groove corresponding to the convex point and is provided with a BGA bonding pad; the bump is electrically connected with the BGA pad, and the embedded chip packaging module structure is designed, so that the problem that the module size is large after packaging is caused by the electrical connection mode of planar chip packaging is solved, interconnection leads are omitted, the occupied area of a carrier plate is small, the mounting density is improved, the size of the whole packaging module is reduced, the required space is saved, and the electronic product light and thin development direction is more met.
Description
Technical Field
The invention belongs to the technical field of chip packaging, and particularly relates to a buried chip packaging module structure and a manufacturing method thereof.
Background
The chip package, i.e. the housing for mounting the semiconductor integrated circuit chip, has the functions of placing, fixing, sealing, protecting the chip and enhancing the electrothermal performance.
Conventional chip packaging techniques belong to the planar type of packaging: after the packaging loading plate is manufactured, the chip is placed on the surface of the chip, the electric conduction between the chip and the packaging loading plate is realized through the electric connection mode of the metal wire, the size of the packaged module is larger and larger along with the increase of the functions of the packaged module, and the development direction of thinning of the electronic product is not satisfied.
Disclosure of Invention
The invention provides the embedded chip packaging module structure and the manufacturing method thereof, and solves the problem of large module size after packaging caused by the electrical connection mode of planar chip packaging by designing the embedded chip packaging module structure, thereby omitting interconnection leads, reducing the occupied area and improving the mounting density, reducing the whole packaging module size, saving the required space and more conforming to the development direction of light and thin electronic products.
The technical scheme provided by the embodiment of the application is as follows:
the embedded chip packaging module structure comprises a packaging carrier plate, a chip embedded in the packaging carrier plate, protruding points connected between the chip and the packaging carrier plate, and a protective layer embedded in the packaging carrier plate and covering the chip;
the packaging carrier plate comprises a body and a groove arranged in the middle of the body;
the body is exposed to the bottom surface of the groove corresponding to the convex point and is provided with a BGA bonding pad;
the bump is electrically connected with the BGA bonding pad.
According to the embedded chip packaging module structure, the whole structure is compact, the required space is saved, the embedded chip packaging module structure is more in line with the development direction of light and thin electronic products, the interconnection leads are omitted through the electric connection between the bumps and the BGA pads, the interconnection electric characteristics are good, the occupied area is small, the chip mounting and the interconnection can be simultaneously carried out, and the process is simple and rapid. By arranging the protective layer, the whole uniformity is good, the mold is not needed for plastic filling, the process is simple and quick, and the cost of equipment and the mold is saved; and wiring can be carried out on the surface of the protective layer, chip packaging is carried out layer by layer, processing is convenient, and the method is suitable for chip module 3D packaging. The sum of the height of the convex points, the thickness of the chip and the height of the protective layer is slightly higher than the depth of the groove, so that the subsequent pressing collapse phenomenon is avoided, and the production quality of the embedded chip packaging module structure is improved.
The manufacturing method of the embedded chip packaging module structure is characterized by comprising the following steps of:
s1, manufacturing a packaging loading plate: firstly, cutting, namely cutting a plate into required sizes by a cutting machine;
drilling holes on the second plate;
the copper is subjected to triple deposition, and a thinner copper layer is adsorbed on the hole wall and the surface of the plate, so that preliminary conduction is realized; wherein the thickness of the copper layer is 3-6 mu m, which is convenient for subsequent etching and effectively etches finer circuits;
fourthly, pattern transfer, wherein the material of the transfer film is selected as a photosensitive material, and the photosensitive material is subjected to polymerization reaction by exposure to complete pattern transfer; or the material of the transfer film is selected to be a non-photosensitive material, and laser ablation is required to complete pattern transfer;
fifthly, electroplating the patterns, and completing primary wiring by using an electroplated copper layering mode;
removing copper, namely removing a copper layer by using microetching solution to finish wiring, and forming a BGA bonding pad; wherein, the microetching liquid can adopt a sulfuric acid hydrogen peroxide system;
seventhly, manufacturing a solder mask, coating solder mask ink, and sequentially performing exposure, development and curing operations to finish manufacturing the solder mask;
eighth surface treatment, surface treatment is carried out by a nickel-palladium-gold or electric nickel-gold or OSP mode;
ninth, sticking a high-temperature resistant adhesive layer on the surface of the BGA bonding pad; through the arrangement, the BGA bonding pad is effectively prevented from being damaged due to high temperature in the subsequent plate laminating process, the heat-resistant performance is improved, and the quality of the BGA bonding pad is ensured;
tenth, pressing the plate, and windowing the area of the plate corresponding to the BGA bonding pad to form a protection groove; the windowing treatment can be performed by adopting a laser drilling or depth-controlled milling mode, and the BGA bonding pad can be effectively protected from damage when the plate is provided with a groove in the later stage through the windowing treatment of the plate;
eleven, drilling, pattern transfer, electroplating and solder resist are sequentially carried out on the plate in the last step, so as to finish wiring;
twelve uncovering, namely uncovering by a laser half-cutting or depth-controlling milling method to form a groove, and manually tearing off the high-temperature resistant adhesive layer until the bottom surface of the groove is exposed out of a BGA bonding pad carried by the chip;
thirteen of the test package carrier boards are tested for functionality through flying needles or electrical test jigs;
s2, manufacturing salient points: manufacturing salient points by means of ball implantation or electroplating;
s3, carrying a chip: connecting the chip connection point with the convex point, and connecting the convex point with the BGA bonding pad at the bottom surface of the groove to realize the electrical interconnection between the chip and the packaging carrier plate; and correspondingly detecting connectivity between the chip and the carrier plate; the bump ball mounting is to perform tin plating on the corresponding BGA bonding pad; bump electroplating is to electroplate copper on the corresponding BGA bonding pad; compacting the chips placed on the convex points in the later stage to ensure that the chip connecting points are fully contacted with the convex points;
s4, laminating a protective layer: the protective layer can be pressed onto the chip in a printing or pressing or spraying mode;
s5, preparing products after packaging: encoding and cutting the package carrier into units; the module functionality of the packaging carrier plate is detected by a testing machine, defective products can be effectively removed, and the product functionality is ensured; and inspecting the product appearance of the package carrier by a high power mirror. The defective products are effectively removed, and outflow of the defective products is avoided.
In the invention, the grooves are designed in the process of manufacturing the packaging loading plate, so that the chips are embedded into the packaging loading plate, the size of the whole packaging module is effectively reduced, and the required space is saved. And through designing the bump to be used for the connection between chip and the encapsulation carrier plate, can save the interconnection lead wire, it is small to reach the electrical connection mode and occupy the encapsulation carrier plate area, improves the installation density. And the chip mounting and interconnection operation can be performed simultaneously, and the operation process is simple and rapid.
By using a mode of vacuum lamination of the protective layer, the method has the advantages of good overall uniformity, no need of mold for plastic filling, simple and quick process and effective saving of equipment and mold cost; and through adopting the protection film surface to carry out wiring again and carrying out the method of chip encapsulation layer by layer, adopt with prior art and use TVS (through silicon via conduction technique) to realize electric connection in the 3D chip stack encapsulation mode and realize switching on between chip and the chip, overcome higher degree of difficulty processing operation to reach the processing more convenient, be suitable for chip module 3D encapsulation more.
Further, in S1, the blanked plate is selected from a copper-clad halogen-free resin plate or a non-copper-clad halogen-free resin plate.
Further, in S1, the length of the cut sheet is 10-720 mm, and the width of the cut sheet is 10-720 mm. The size of the plate can be flexibly designed according to the requirements, and the cutting diversity is met.
Further, in S1, the drilling is performed by a laser drilling method or a mechanical drilling method. The laser drilling processing capability, efficiency and field performance are excellent, the cost is low, and the laser drilling processing device is suitable for processing with the aperture smaller than 0.15 mm; the machining quality of mechanical drilling is good, and the method is suitable for machining through holes; the drilling mode can be flexibly adjusted according to production requirements, the production is convenient, and the lower drilling cost is met.
Further, in S1, the coating for manufacturing the solder mask layer is implemented by printing, spraying or pressing. By the arrangement, the manufacturing quality of the solder mask is ensured.
Further, in S1, the cross-sectional area of the high temperature resistant glue layer is larger than the cross-sectional area of the BGA pad, and the cross-sectional area of the high temperature resistant glue layer is smaller than the cross-sectional area of the groove. Through this setting, can effectively cover BGA pad at the high temperature resistant glue film of assurance, provide protect function, also can prevent effectively that the both ends of high temperature resistant glue film from going deep into panel to more difficult tearing effectively improves the dyestripping convenience.
Further, in S5, the encoding is performed by laser or printing.
Further, in S5, the cutting is performed by using a water knife or a laser or a wire cutting. Through this setting, satisfy multiple cutting mode, the cutting operation of operating personnel of being convenient for.
Further, in S4, the protective layer is a semi-solid halogen-free resin protective layer; the lamination is realized by adopting a sheet vacuum lamination mode, and the printing is realized by adopting a filling corresponding printing mode. The halogen-free resin protective layer is adopted by the protective layer, so that the environment-friendly electronic protective layer is more in line with the environment-friendly concept of green electrons; and by adopting a semi-cured resin form, the full fluidity and filling property are effectively ensured, and the quality of the protective layer is ensured.
The invention has the beneficial effects that:
through design embedded chip packaging module structure, the electrical connection mode of planar chip packaging has been solved and has been led to the big problem of module size after the encapsulation to saved interconnection lead wire, area is little, improves the installation density, thereby reduces whole encapsulation module size, practices thrift the demand space, accords with electronic product light, thin development direction more.
Drawings
FIG. 1 is a schematic diagram of a single-layer chip package according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a multi-layer chip package according to a second embodiment of the present invention;
FIG. 3 is a flow chart of a method for fabricating a chip package module structure according to the present invention;
FIG. 4 is a schematic diagram of a structure of the blanking operation in S1 according to the present invention;
FIG. 5 is a schematic diagram of the drilling operation in S1 according to the present invention;
FIG. 6 is a schematic diagram of the structure of the copper deposition operation in S1 according to the present invention;
FIG. 7 is a schematic diagram of a graphic transfer operation structure in S1 according to the present invention;
FIG. 8 is a schematic view showing the structure of the electroplating operation in S1 according to the present invention;
fig. 9 is a schematic diagram of a film-removing and copper-removing operation structure in S1 according to the present invention;
FIG. 10 is a schematic diagram of the operation structure of the solder mask layer in S1 according to the present invention;
FIG. 11 is a schematic diagram of an operation structure of attaching a high temperature resistant adhesive layer in S1 according to the present invention;
FIG. 12 is a schematic view of the operation structure of the laminated board in S1 according to the present invention;
FIG. 13 is a schematic diagram showing the structure of the drilling, pattern transferring, electroplating and solder mask operation in S1 according to the present invention;
FIG. 14 is a schematic diagram of the operation structure of the groove in S1 according to the present invention;
FIG. 15 is a schematic diagram of the bump manufacturing operation in S2 according to the present invention;
fig. 16 is a schematic diagram of the operation structure of the chip-mounted in S3 according to the present invention;
FIG. 17 is a schematic view of the operation structure of the pressure protection layer of the present invention.
The marks in the figure: the packaging carrier 1, the body 11, the groove 12, the BGA bonding pad 111, the plate 112, the copper layer 113, the solder mask 114, the high temperature resistant adhesive layer 115 and the protection groove 116; a chip 2; a bump 3; and a protective layer 4.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
In order to facilitate an understanding of the present invention by those skilled in the art, the present invention will be described in further detail with reference to specific examples and drawings.
As shown in fig. 1 and fig. 3-17, an embodiment of the present invention provides a buried chip package module structure, which includes a package carrier 1, a chip 2 embedded in the package carrier 1, bumps 3 connected between the chip 2 and the package carrier 1, and a protective layer 4 embedded in the package carrier 1 and covering the chip 2;
the packaging carrier plate 1 comprises a body 11 and a groove 12 arranged in the middle of the body 11;
the body 11 is exposed at the bottom surface of the groove 12 corresponding to the salient point 3 and is provided with a BGA bonding pad 111;
the bump 3 is electrically connected to the BGA pad 111.
Through above-mentioned embedded chip packaging module structure, overall structure is compact, practices thrift the demand space, accords with electronic product light, thin development direction more, and through bump 3 and BGA pad 111 electric connection, saves interconnection lead wire, and interconnection electrical property is good, and is small for the carrier plate area, and chip 2 installation and interconnection can go on simultaneously, simple process, quick. By arranging the protective layer 4, the whole uniformity is good, the mold is not needed for plastic filling, the process is simple and quick, and the cost of equipment and the mold is saved. The sum of the height of the bump 3, the thickness of the chip 2 and the height of the protective layer 4 is slightly higher than the depth of the groove 12, so that the subsequent press-fit collapse phenomenon is avoided, and the production quality of the embedded chip packaging module structure is improved.
The manufacturing method of the single-layer chip packaging module structure comprises the following steps:
s1, manufacturing a packaging carrier plate 1: firstly, cutting, namely cutting a plate 112 into required sizes by a cutting machine;
drilling holes on the plate 112;
the triple copper deposition is carried out, a thinner copper layer 113 is adsorbed on the hole wall and the surface of the plate 112, and preliminary conduction is realized; wherein the thickness of the copper layer is 3-6 mu m, which is convenient for subsequent etching and effectively etches finer circuits;
fourthly, pattern transfer, wherein the material of the transfer film is selected as a photosensitive material, and the photosensitive material is subjected to polymerization reaction by exposure to complete pattern transfer; or the material of the transfer film is selected to be a non-photosensitive material, and laser ablation is required to complete pattern transfer;
fifthly, electroplating the patterns, and completing primary wiring by using an electroplated copper layering mode;
a micro-etching solution is selected to remove the copper layer 113 to finish wiring; wherein, the microetching liquid can adopt a sulfuric acid hydrogen peroxide system;
seventhly, manufacturing a solder mask 114, coating solder mask ink, and sequentially performing exposure, development and curing operations to finish manufacturing the solder mask 114;
eighth surface treatment, surface treatment is carried out by a nickel-palladium-gold or electric nickel-gold or OSP mode;
ninth, a high temperature resistant adhesive layer 115 is stuck on the surface of the BGA bonding pad 111; through the arrangement, the BGA bonding pad is effectively prevented from being damaged due to high temperature in the subsequent plate laminating process, the heat-resistant performance is improved, and the quality of the BGA bonding pad is ensured;
tenth, the plate is pressed and windowed to form a protection slot 116 in the area corresponding to the BGA bonding pad 111; the windowing treatment can be performed by adopting a laser drilling or depth-controlling milling mode, and the BGA bonding pad 111 can be effectively protected from damage when the plate is used for manufacturing the groove in the later period through the windowing treatment of the plate;
eleven, drilling, pattern transfer, electroplating and solder resist are sequentially carried out on the plate in the last step, so as to finish wiring;
twelve covers are uncovered, a groove 12 is formed by a laser half-cutting or depth-controlling milling method, and then the high-temperature resistant adhesive layer 115 is manually torn off until the bottom surface of the groove 12 exposes the BGA bonding pad 111 carried on the chip 2;
thirteen of the test package carrier 1 tests the functionality of the package carrier 1 through a flying probe or an electrical test fixture;
s2, manufacturing a bump 3: manufacturing the salient points 3 by means of ball implantation or electroplating;
s3, chip 2 is mounted: butting the connection point of the chip 2 with the BGA bonding pad 111 at the bottom surface of the groove 12 to realize the electrical interconnection between the chip 2 and the package carrier 1; and correspondingly detecting the connectivity between the chip 2 and the carrier plate; wherein, the bump ball mounting is to perform solder plating on the corresponding BGA bonding pad 111; bump plating is to plate copper on the corresponding BGA pad 111; later stage, compacting the chip 2 placed on the bump 3 to make the connection point of the chip 2 fully contact with the bump 3;
s4, laminating the protective layer 4, namely laminating the protective layer 4 on the chip 2 in a printing or laminating or spraying mode, wherein the integral uniformity is good by using a vacuum laminating protective layer 4 mode, a mould is not required to be used for pouring plastic, the process is simple and quick, and the equipment and mould cost is effectively saved;
s5, preparing products after packaging: encoding and cutting the package carrier 1 into units; the module functionality of the package loading board 1 is detected by a testing machine, defective products can be effectively removed, and the product functionality is ensured; and the product appearance of the package carrier 1 is checked by a high power mirror. The defective products are effectively removed, and outflow of the defective products is avoided.
In the invention, the grooves 12 are designed in the process of manufacturing the package carrier 1, so that the chips 2 are buried in the package carrier 1, the size of the whole package module is effectively reduced, and the required space is saved. And through designing bump 3 to be used for the connection between chip 2 and the encapsulation loading board 1, can save the interconnection lead wire, reach the electrical connection mode and occupy the encapsulation loading board 1 area little, improve the installation density. And the chip 2 mounting and interconnection operations can be performed simultaneously, and the operation process is simple and rapid.
In this embodiment, in S1, the blanked plate 112 is selected to be a copper-clad halogen-free resin plate 112 or a non-copper-clad halogen-free resin plate 112.
In this embodiment, in S1, the length of the cut sheet 112 is 10-720 mm, and the width of the cut sheet 112 is 10-720 mm. The size of the plate 112 can be flexibly designed according to the requirements, and the cutting diversity is met.
In this embodiment, in S1, the drilling is performed by a laser drilling method or a mechanical drilling method. The laser drilling processing capability, efficiency and field performance are excellent, the cost is low, and the laser drilling processing device is suitable for processing with the aperture smaller than 0.15 mm; the machining quality of mechanical drilling is good, and the method is suitable for machining through holes; the drilling mode can be flexibly adjusted according to production requirements, the production is convenient, and the lower drilling cost is met.
In this embodiment, in S1, the application of the solder mask layer 114 is performed by printing, spraying or pressing. With this arrangement, the manufacturing quality of the solder resist layer 114 is ensured.
In this embodiment, in S1, the cross-sectional area of the high temperature resistant adhesive layer is larger than the cross-sectional area of the BGA pad, and the cross-sectional area of the high temperature resistant adhesive layer is smaller than the cross-sectional area of the groove. Through this setting, can effectively cover BGA pad at the high temperature resistant glue film of assurance, provide protect function, also can prevent effectively that the both ends of high temperature resistant glue film from going deep into panel to more difficult tearing effectively improves the dyestripping convenience.
In this embodiment, in S5, the code is laser or printed.
In this embodiment, in S5, the cutting is performed using a water knife or a laser or a wire cutting. Through this setting, satisfy multiple cutting mode, the cutting operation of operating personnel of being convenient for.
In the present embodiment, in S4, the protective layer 4 is a semi-solid halogen-free resin protective layer 4; the lamination is realized by adopting a sheet vacuum lamination mode, and the printing is realized by adopting a filling corresponding printing mode. The protective layer 4 is made of halogen-free resin, so that the environment-friendly concept of green electrons is more satisfied; and by adopting the semi-cured resin form, the sufficient fluidity and filling property are effectively ensured, and the quality of the protective layer 4 is ensured.
Example 2
Unlike embodiment 1, as shown in fig. 2, in the method for manufacturing a multi-layer chip package module structure according to an embodiment of the present invention, wiring is further performed on the surface of the protective layer 4, and then the chip 2 is packaged layer by layer. The processing is convenient, and the chip module 3D packaging is applicable.
The invention has the beneficial effects that:
through design embedded chip packaging module structure, the electrical connection mode of planar chip packaging has been solved and has been led to the big problem of module size after the encapsulation to saved interconnection lead wire, area is little, improves the installation density, thereby reduces whole encapsulation module size, practices thrift the demand space, accords with electronic product light, thin development direction more.
By using the mode of vacuum lamination of the protective layer 4, the integral uniformity is good, the mold is not needed for filling plastic, the process is simple and quick, and the equipment and mold cost is effectively saved; and through adopting the protection film surface to carry out wiring again and carrying out the method of chip encapsulation layer by layer, adopt with prior art and use TVS (through silicon via conduction technique) to realize electric connection in the 3D chip stack encapsulation mode and realize switching on between chip and the chip, overcome higher degree of difficulty processing operation to reach the processing more convenient, be suitable for chip module 3D encapsulation more.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art. It should be noted that technical features not described in detail in the present invention may be implemented by any prior art.
Claims (9)
1. The manufacturing method of the embedded chip packaging module structure is characterized by comprising the following steps of:
s1, manufacturing a packaging loading plate:
firstly, cutting, namely cutting a plate into required sizes by a cutting machine;
secondly, drilling the plate;
thirdly, copper is deposited, a layer of copper is adsorbed on the hole wall and the surface of the plate, and preliminary conduction is realized;
fourthly, pattern transfer, wherein the material of the transfer film is selected from photosensitive materials, and the photosensitive materials are subjected to polymerization reaction by exposure to complete pattern transfer; or the material of the transfer film is selected to be a non-photosensitive material, and laser ablation is required to complete pattern transfer;
fifthly, pattern electroplating, namely completing primary wiring by using an electroplated copper layering mode;
sixthly, copper is removed, a microetching solution is selected to remove the copper layer to finish wiring, and a BGA bonding pad is formed;
seventhly, manufacturing a solder mask layer, coating solder mask ink, and sequentially performing exposure, development and curing operations, so that the manufacturing of the solder mask layer is completed;
eighth, surface treatment is carried out by a nickel-palladium-gold or electric nickel-gold or OSP mode;
ninth, sticking a high-temperature resistant adhesive layer on the surface of the BGA bonding pad;
tenth, pressing the plate, and windowing the area of the plate corresponding to the BGA bonding pad to form a protection groove;
eleven, drilling, pattern transfer, electroplating and solder resist are sequentially carried out on the plate in the last step, so as to finish wiring;
twelve, uncovering, namely uncovering by a laser half-cutting or depth-controlling milling method, so as to form a groove, and manually tearing off the high-temperature resistant adhesive layer until the bottom surface of the groove is exposed out of a BGA bonding pad carried by the chip;
thirteen, detecting the package loading plate, and testing the functionality of the package loading plate through a flying probe or an electrical testing jig;
s2, manufacturing salient points: manufacturing salient points by means of ball implantation or electroplating;
s3, carrying a chip: connecting the chip connection point with the convex point, and connecting the convex point with the BGA bonding pad at the bottom surface of the groove to realize the electrical interconnection between the chip and the packaging carrier plate; and correspondingly detecting connectivity between the chip and the carrier plate;
s4, laminating a protective layer: laminating the protective layer on the chip in a printing or laminating or spraying mode;
s5, preparing products after packaging: encoding and cutting the package carrier into units; detecting module functionality of the packaging carrier plate through a testing machine; and inspecting the product appearance of the package carrier by a high power mirror.
2. The method according to claim 1, wherein in S1, the blanked plate is a copper-clad halogen-free resin plate or a non-copper-clad halogen-free resin plate.
3. The method of claim 1, wherein in S1, the length of the cut sheet is 10-720 mm and the width of the cut sheet is 10-720 mm.
4. The method of claim 1, wherein in S1, the drilling is performed by laser drilling or mechanical drilling.
5. The method according to claim 1, wherein in S1, the coating of the solder mask is performed by printing, spraying, or pressing.
6. The method according to claim 1, wherein in S1, the cross-sectional area of the high temperature resistant adhesive layer is larger than the cross-sectional area of the BGA pad, and the cross-sectional area of the high temperature resistant adhesive layer is smaller than the cross-sectional area of the groove.
7. The method of claim 1, wherein in S5, the encoding is performed by laser or printing.
8. The method according to claim 1, wherein in S5, the cutting is performed by using a water knife, a laser, or a wire saw.
9. The method of manufacturing a buried chip package module structure according to claim 1, wherein in S4, the protective layer is a semi-solid halogen-free resin protective layer; the lamination is realized by adopting a sheet vacuum lamination mode, and the printing is realized by adopting a filling corresponding printing mode.
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