CN116156741B - Printed circuit board and mobile device - Google Patents

Abstract

The application provides a printed circuit board and mobile device, include: the stacked layers are symmetrical on two sides of the core board layer and comprise a plurality of circuit board layers and prepreg layers between the adjacent circuit board layers, and further comprise buried holes penetrating through the core board layers, part of the circuit board layers and part of the prepreg layers, the glue content of the prepreg layers at two ends of the buried holes is first glue content, the glue content of the rest prepreg layers is second glue content, the first glue content is larger than the second glue content, the thickness of the prepreg layers at two ends of the buried holes is larger than that of the rest prepreg layers, and the thickness of the printed circuit board is within 0.6 mm. Through symmetrical stack layers, the stress phase difference during lamination is smaller, the problem of warping is reduced, the glue filling amount at the buried holes is increased, the buried holes can be effectively filled with the prepreg layers, the problem of insufficient buried hole filling is solved, the thickness of the prepreg layers at two ends of the buried holes is increased, the thickness of the rest prepreg layers is reduced, and the requirement of an ultrathin high-density circuit board is met.

Description

Printed circuit board and mobile device

Technical Field

The present application relates to the field of integrated circuit technology, and in particular, to a printed circuit board and a mobile device.

Background

A printed circuit board (Printed Circuit Board, PCB), also called a printed circuit board, is an important electronic component, is a support for electronic components, is a carrier for electrically interconnecting electronic components, and is used in electronic components having integrated circuits such as watches, computers, communication electronic devices, and the like.

With the rapid development and wide application of integrated circuits, the size of electronic devices is becoming smaller and smaller, and the requirements for printed circuit boards are increasing.

At present, the lamination effect of the printed circuit board is poor, and the performance of the printed circuit board is affected.

Disclosure of Invention

The application provides a printed circuit board and mobile device, improves the performance of printed circuit board.

In a first aspect, the present application provides a printed circuit board comprising:

the printed circuit board comprises a core board layer, a stacking layer which is symmetrical on two sides of the core board layer, wherein the stacking layer comprises a plurality of circuit board layers and prepreg layers between adjacent circuit board layers, and the printed circuit board also comprises buried holes which penetrate through the core board layer, part of the circuit board layers and part of the prepreg layers;

the glue content of the prepreg layers at the two ends of the buried hole is a first glue content, the glue content of the rest prepreg layers is a second glue content, and the first glue content is larger than the second glue content;

The thickness of the prepreg layers at the two ends of the buried hole is larger than that of the rest prepreg layers, and the thickness of the printed circuit board is within 0.6 mm.

Optionally, the prepreg layers at two ends of the buried hole are 1037 prepregs, and the rest prepreg layers are 1017 prepregs.

Optionally, the printed circuit board includes ten circuit board layers, the buried hole penetrates through the core board layer, two circuit board layers and one prepreg layer on one side of the core board layer, and two circuit board layers and one prepreg layer on the other side of the core board layer.

Optionally, the ten circuit board layers include:

two device layers, three secondary layers, three wiring layers, one main layer and one power supply layer.

Optionally, the printed circuit board includes a first circuit board layer, a first prepreg layer, a second circuit board layer, a second prepreg layer, a third circuit board layer, a third prepreg layer, a fourth circuit board layer, a fourth prepreg layer, a fifth circuit board layer, a core layer, a sixth circuit board layer, a fifth prepreg layer, a seventh circuit board layer, a sixth prepreg layer, an eighth circuit board layer, a seventh prepreg layer, a ninth circuit board layer, an eighth prepreg layer, and a tenth circuit board layer that are stacked in sequence;

The buried hole penetrates through the fourth circuit board layer, the fourth prepreg layer, the fifth circuit board layer, the core board layer, the sixth circuit board layer, the fifth prepreg layer and the seventh circuit board layer;

the printed circuit board further includes:

a third blind hole formed in the third circuit board layer and the third prepreg layer, a third blind hole formed in the sixth prepreg layer and the eighth circuit board layer, and an alignment structure formed by the third blind hole and the buried hole;

the second blind holes are formed in the second circuit board layer and the second prepreg layer, the second blind holes are formed in the seventh prepreg layer and the ninth circuit board layer, and the second blind holes and the third blind holes form an alignment structure;

the first blind holes are formed in the first circuit board layer and the first prepreg layer, the eighth prepreg layer and the tenth circuit board layer, and the first blind holes and the second blind holes form an alignment structure.

Optionally, the printed circuit board includes:

the device comprises a radio frequency region, a processor region and a microcontroller region which are sequentially arranged in a first direction, wherein the processor region comprises a processor radio frequency region and a processor power supply region which are sequentially arranged in the first direction, and the microcontroller region comprises a microcontroller storage region and a microcontroller power supply region which are sequentially arranged in the first direction;

The microcontroller area and the power supply area are sequentially arranged in a second direction, and the first direction and the second direction are two directions which are perpendicular to each other on a plane;

in a third direction, the printed circuit board comprises the core board layer and stacked layers which are symmetrical on two sides of the core board layer, wherein the third direction is a direction perpendicular to the first direction and the second direction;

the power supply area is connected with the microcontroller power supply area, and the processor area is connected with the microcontroller storage area.

Optionally, in the second direction, the first end of the microcontroller region is higher than the first end of the processor region, the second end of the microcontroller region is lower than the first end of the processor region, the first end of the power supply region is higher than the second end of the processor region, and the second end of the power supply region is lower than the second end of the processor region.

Optionally, in the second direction, the first end of the power supply area is higher than the first end of the processor area, the second end of the power supply area is lower than the first end of the processor area, the first end of the microcontroller area is higher than the second end of the processor area, and the second end of the microcontroller area is lower than the second end of the processor area.

Optionally, the printed circuit board further includes:

the first metal wire set is connected with the radio frequency area and the processor radio frequency area, the second metal wire set is connected with the processor power area and the power supply area, the third metal wire set is connected with the processor power area and the microcontroller power area, the fourth metal wire set is connected with the microcontroller power area and the power supply area, and the fifth metal wire set is connected with the processor area and the microcontroller storage area.

In a second aspect, the present application provides a mobile device comprising the printed circuit board described above.

The printed circuit board provided by the application comprises: the stacked layers are symmetrical on two sides of the core board layer and comprise a plurality of circuit board layers and prepreg layers between the adjacent circuit board layers, the printed circuit board further comprises buried holes penetrating through the core board layers, part of the circuit board layers and part of the prepreg layers, the glue content of the prepreg layers at two ends of the buried holes is first glue content, the glue content of the rest prepreg layers is second glue content, the first glue content is larger than the second glue content, the thickness of the prepreg layers at two ends of the buried holes is larger than the thickness of the rest prepreg layers, and the thickness of the printed circuit board is within 0.6 mm. According to the scheme, the stress phase difference during lamination is smaller through symmetrical stacked layers, the problem of warping degree is solved, and the performance of the printed circuit board is improved. Meanwhile, the glue filling amount of the buried holes is increased, so that the prepreg layer can effectively fill the buried holes, the problem of insufficient buried hole filling is solved, and the performance of the circuit board is further improved. And the thickness of the prepreg layers at the two ends of the buried hole is increased, and the thickness of the rest prepreg layers is reduced, so that the requirement of the ultrathin high-density circuit board can be met.

Drawings

For a clearer description of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural view of a printed circuit board according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a printed circuit board according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of another printed circuit board according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a printed circuit board according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a further printed circuit board according to an embodiment of the present disclosure;

FIG. 6 is a layout of a printed circuit board according to an embodiment of the present application;

FIG. 7 is a layout of another printed circuit board according to an embodiment of the present application;

fig. 8 is a layout diagram of a printed circuit board according to another embodiment of the present application.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The terms "first," "second," and the like in this application are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged where appropriate. For example, a first wiring board layer may also be referred to as a second wiring board layer, and similarly, a second wiring board layer may also be referred to as a first wiring board layer, without departing from the scope herein.

Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise.

It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, steps, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, steps, operations, elements, components, items, categories, and/or groups.

The printed circuit board is a support for electronic components, is a carrier for electrically interconnecting the electronic components, and can realize wiring and electrical connection or electrical insulation between various electronic components such as an integrated circuit, and provides desired electrical characteristics. At present, most of printed circuit boards are multi-layer boards, which can increase the wiring area, for example, one or more double-sided boards can be used as an inner layer, two single-sided boards can be used as an outer layer, the multi-layer printed circuit boards are formed by alternately connecting conductive patterns together through a positioning system and insulating adhesive materials according to design requirements, and the processing flow mainly comprises cutting, inner dry film (grinding board-film pasting-exposing-developing-etching/electroplating-film stripping), browning, laminating, drilling, copper plating, outer dry film, outer pattern electroplating, solder resist, silk screen printing, surface treatment and forming. Wherein lamination is a process of bonding individual layers of wiring into a whole by means of the tackiness of the Pre-pregnant (PP) sheet itself, which is self-contained, thereby pressing the discrete multilayer wiring board and prepreg together into the desired number of layers and thickness.

As electronic products are developed toward lighter, thinner, and smaller sizes, the space left for the electronic products for the circuit board is smaller and smaller, and thus the circuit board tends to be developed toward ultra-thin, multi-stage, and high density. To meet the ultra-thin requirement of high-density circuit boards, the thickness of the circuit board needs to be reduced first, but the lamination effect of the printed circuit board caused by the reduction of the thickness of the circuit board is poor, which affects the performance of the printed circuit board.

The applicant found that the stress exists after the lamination is completed due to the influence of pressure and temperature during the lamination, and if the lamination is uneven, the stress is different, so that the warpage problem is easy to occur, and the performance of the printed circuit board is influenced. Therefore, the printed circuit board provided by the application comprises a core board layer and a stacking layer which is symmetrical on two sides of the core board layer, wherein the stacking layer comprises a plurality of circuit board layers and prepreg layers between adjacent circuit board layers, and the stress phase difference during lamination is smaller through the symmetrical stacking layer, so that the problem of warping degree is solved, and the performance of the printed circuit board is improved. Meanwhile, the applicant finds that the glue content of the prepreg layers during lamination affects the adhesion of the circuit board layers, the glue content is insufficient, the glue filling amount is insufficient easily, and the printed circuit board is easy to generate the problems of board explosion and the like when contacting heat and meeting high temperature. Therefore, the printed circuit board provided by the application, the glue content of the prepreg layer penetrating through the two ends of the buried holes of the core plate layer, the partial circuit board layer and the partial prepreg layer is the first glue content, the glue content of the residual prepreg layer is the second glue content, and the first glue content is larger than the second glue content, so that the glue filling amount of the buried holes is increased, the prepreg layer can be further filled into the buried holes, the problem of insufficient buried hole filling is solved, and the performance of the circuit board is further improved. And the thickness of the rest prepreg layers is reduced while the thicknesses of the prepreg layers at the two ends of the buried hole are increased, so that the thickness of the printed circuit board is within 0.6mm, and the requirement of the ultrathin high-density printed circuit board is met.

The technical scheme of the present application is described in detail below with specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.

Fig. 1 and fig. 2 are schematic structural diagrams of a printed circuit board according to an embodiment of the present application. As shown in fig. 1 and 2, a printed circuit board provided in an embodiment of the present application includes: the core board layer 101 and stacked layers symmetrical on two sides of the core board layer 101, wherein the stacked layers comprise a plurality of circuit board layers and prepreg layers between adjacent circuit board layers, and the printed circuit board further comprises buried holes 300 penetrating through the core board layer 101, part of the circuit board layers and part of the prepreg layers;

the glue content of the prepreg layers at the two ends of the buried hole 300 is a first glue content, the glue content of the rest prepreg layers is a second glue content, and the first glue content is larger than the second glue content;

the thickness of the prepreg layers at both ends of the buried via 300 is greater than that of the remaining prepreg layers, and the thickness of the printed circuit board is within 0.6 mm.

In this embodiment, the core board layer 101 is a copper-clad plate, which may also be called as a substrate or a copper-clad laminate, and includes copper foil, a solid resin material and glass fiber, and is a plate-like material formed by impregnating a reinforcing material with resin, and cladding copper foil on one or both sides, and hot-pressing. The different core plates differ mainly in thickness, for example 1078 core plate (core) refers to a core plate having a thickness of about 63 μm, 1067 core plate refers to a core plate having a thickness of about 53 μm. The core plate layer 101 mainly plays a supporting role.

The circuit board layers are also called Copper plating layers (coppers), and each circuit board layer is electroplated in the process of processing the printed circuit board, wherein the electroplated material is Copper, so that the effects of reducing ground wire impedance and reducing loop area are achieved. The number of layers of the circuit board layer can be 8-12.

The prepreg layer is an adhesive material mainly composed of resin and reinforcing material glass fiber cloth, and different prepregs are mainly different in thickness and glue content, for example, the thickness of 1017 prepreg is about 30 μm, the thickness of theoretical glue content is about 12 μm, the thickness of 1037 prepreg is about 50 μm, and the thickness of theoretical glue content is about 28 μm. The prepreg layer achieves the effect of bonding the circuit board layer.

The buried via 300 includes a via hole penetrating the core board layer 101, a part of the circuit board layer, and a part of the prepreg layer, and a metal filled in the via hole, thereby achieving the function of connecting the circuit board.

In some embodiments, the prepreg layers at two ends of the buried hole 300 are 1037 prepregs, and the rest prepreg layers are 1017 prepregs, and the glue content of the 1037 prepregs is greater than that of the 1017 prepregs, so that the glue filling amount of the buried hole 300 can be increased, and the problem caused by insufficient glue filling of the buried hole 300 can be reduced. And, when the prepreg layers at both ends of the buried hole 300 are 1037 prepregs, the core layer 101 may be 1067 core, so that the thickness of the printed circuit board is within a preset value by increasing the thickness of the prepreg layers and reducing the thickness of the core layer 101, thereby achieving the ultra-thin high density requirement. The preset value may be a value less than or equal to 0.6mm, for example, a thickness of 0.5mm for a printed circuit board. The line width and the line spacing of the ultra-thin high-density circuit board are both about 50 μm. The line width may include a line width of the buried via, a line width of the blind via, etc., and the line distance of the circuit board may include a distance between adjacent blind vias, a distance between the buried via and adjacent blind via, etc.

In some embodiments, as shown in fig. 1 and 2, the printed circuit board includes ten circuit board layers, the stacked layers on both sides of the core board layer 101 include five circuit board layers, respectively, the buried via 300 penetrates through the core board layer 101, two circuit board layers and one prepreg layer on one side of the core board layer 101, and two circuit board layers and one prepreg layer on the other side of the core board layer 101, and then the buried via 300 penetrates through the seven-layer structure, so as to form a ten-layer 3-stage printed circuit board.

The ten wiring board layers are a first wiring board layer 111, a second wiring board layer 112, a third wiring board layer 113, a fourth wiring board layer 114, a fifth wiring board layer 115, a sixth wiring board layer 116, a seventh wiring board layer 117, an eighth wiring board layer 118, a ninth wiring board layer 119, and a tenth wiring board layer 120, respectively. A first prepreg layer 121 is formed between the first and second wire layers 111 and 112, a second prepreg layer 122 is formed between the second and third wire layers 112 and 113, a third prepreg layer 123 is formed between the third and fourth wire layers 113 and 114, a fourth prepreg layer 124 is formed between the fourth and fifth wire layers 114 and 115, a core layer 101 is formed between the fifth and sixth wire layers 115 and 116, a fifth prepreg layer 125 is formed between the sixth and seventh wire layers 116 and 117, a sixth prepreg layer 126 is formed between the seventh and eighth wire layers 117 and 118, a seventh prepreg layer 127 is formed between the eighth and ninth wire layers 118 and 119, and an eighth prepreg layer 128 is formed between the ninth and tenth wire layers 119 and 120. The side of the first circuit board layer 111 far from the first prepreg layer 121 may further form a first solder mask (Soldermsk), the side of the tenth circuit board layer 120 far from the eighth prepreg layer 128 may further form a second solder mask 132, the first solder mask 131 and the second solder mask 132 are used for protecting the circuit board layers, and in practical application, the first solder mask 131 and the second solder mask 132 are green oil layer portions on the printed circuit board.

The first stacked layer on one side of the core sheet layer 101 includes a first wiring sheet layer 111, a first prepreg layer 121, a second wiring sheet layer 112, a second prepreg layer 122, a third wiring sheet layer 113, a third prepreg layer 123, a fourth wiring sheet layer 114, a fourth prepreg layer 124, and a fifth wiring sheet layer 115, which are stacked in this order in a direction approaching the core sheet layer 101. The second stacked layer on the other side of the core sheet layer 101 includes a sixth wiring sheet layer 116, a fifth prepreg layer 125, a seventh wiring sheet layer 117, a sixth prepreg layer 126, an eighth wiring sheet layer 118, a seventh prepreg layer 127, a ninth wiring sheet layer 119, an eighth prepreg layer 128, and a tenth wiring sheet layer 120, which are stacked in this order in a direction away from the core sheet layer 101.

And the first and tenth wiring board layers 111 and 120, the first and eighth prepreg layers 121 and 128, the second and ninth wiring board layers 112 and 119, the second and seventh prepreg layers 122 and 127, the third and eighth wiring board layers 113 and 118, the third and sixth prepreg layers 123 and 126, the fourth and seventh wiring board layers 114 and 117, the fourth and fifth prepreg layers 124 and 125, and the fifth and sixth wiring board layers 115 and 116 are symmetrical with each other, centering on the core board layer 101.

The buried via 300 penetrates the fourth wiring board layer 114, the fourth prepreg layer 124, the fifth wiring board layer 115, the core board layer 101, the sixth wiring board layer 116, the fifth prepreg layer 125, and the seventh wiring board layer 117. The third and sixth prepreg layers 123 and 126 at both ends of the buried via 300 may be 1037 prepregs, and the first, second, fourth, fifth, seventh and eighth prepreg layers 121, 122, 124, 125, 127 and 128 may be 1017 prepregs.

In addition, a third blind hole 303 is formed in the third wiring board layer 113 and the third prepreg layer 123, a third blind hole 303 is formed in the sixth prepreg layer 126 and the eighth wiring board layer 118, and the third blind hole 303 and the buried hole 300 form an alignment structure. The second circuit board layer 112 and the second prepreg layer 122 have a second blind hole 302 formed therein, the seventh prepreg layer 127 and the ninth circuit board layer 119 have a second blind hole 302 formed therein, and the second blind hole 302 and the third blind hole 303 form an alignment structure. The first blind hole 301 is formed in the first circuit board layer 111 and the first prepreg layer 121, the first blind hole 301 is formed in the eighth prepreg layer 128 and the tenth circuit board layer 120, and the first blind hole 301 and the second blind hole 302 form an alignment structure, so that the manufacturing of the ten-layer 3-stage printed circuit board is formed through the three alignment structures. It should be noted that the first blind hole 301, the second blind hole 302, the third blind hole 303, and the buried hole 300 are all filled with a metal material so as to connect the respective wiring board layers together, and it is apparent that in the drawing, the third blind hole 303 in the third wiring board layer 113 and the third prepreg layer 123 is embedded in the fourth wiring board layer 114, the third blind hole 303 in the sixth prepreg layer 126 and the eighth wiring board layer 118 is embedded in the seventh wiring board layer 117, the second blind hole 302 in the second wiring board layer 112 and the second prepreg layer 122 is embedded in the third wiring board layer 113, the second blind hole 302 in the seventh prepreg layer 127 and the ninth wiring board layer 119 is embedded in the eighth wiring board layer 118, the first blind hole 301 in the first wiring board layer 111 and the first prepreg layer 121 is embedded in the first wiring board layer 111, and the first blind hole 301 in the eighth prepreg layer 128 and the tenth wiring board layer 120 is embedded in the ninth wiring board layer 119. Specifically, first lamination is performed, all the laminates (the wiring board layers and the prepreg layers) between the fourth wiring board layer 114 to the seventh wiring board layer 117 are pressed together, and the buried via 300 is formed in the fourth wiring board layer 114 to the seventh wiring board layer 117. Then, the second lamination and the first alignment are performed, the third wiring board layer 113 and the third prepreg layer 123 are pressed together before the second lamination is performed, the third blind holes 303 are formed in the third wiring board layer 113 and the third prepreg layer 123, the sixth prepreg layer 126 and the eighth wiring board layer 118 are pressed together, the third blind holes 303 are formed in the sixth prepreg layer 126 and the eighth wiring board layer 118, and after the alignment is performed through the third blind holes 303 and the buried holes 300, all layers between the third wiring board layer 113 to the eighth wiring board layer 118 are pressed together. Then, the third lamination and the second alignment are performed, the second circuit board layer 112 and the second prepreg layer 122 are pressed together before the third lamination is performed, the second blind holes 302 are formed in the second circuit board layer 112 and the second prepreg layer 122, the seventh prepreg layer 127 and the ninth circuit board layer 119 are pressed together, the second blind holes 302 are formed in the seventh prepreg layer 127 and the ninth circuit board layer 119, and after the alignment is performed through the second blind holes 302 and the third blind holes 303, all layers between the second circuit board layer 112 and the ninth circuit board layer 119 are pressed together. And then, performing fourth lamination and third alignment, forming a first blind hole 301 in the first circuit board layer 111 and the first prepreg layer 121, pressing the eighth prepreg layer 128 and the tenth circuit board layer 120 together, forming a first blind hole 301 in the eighth prepreg layer 128 and the tenth circuit board layer 120, and pressing all layers between the first circuit board layer 111 and the tenth circuit board layer 120 together after aligning through the first blind hole 301 and the second blind hole 302, thereby completing the manufacturing of the tenth 3-stage printed circuit board.

It should be noted that the ten-layer 3-stage printed circuit board manufactured by the scheme has the advantages of short material stock period, wide application range and high production yield. Taking a 10-layer 3-level printed circuit board with the thickness of 0.5mm as an example, the material stock period can be shortened to 35 days from 55 days due to the reduction of 1017 prepregs, and the production yield can be increased to 98% from 75% due to the fact that all original prepregs are 1017 prepregs are converted into 1037 prepregs at two ends of a buried hole.

In order to facilitate visual understanding of the solution of the present application, test data of a ten-layer 3-stage printed circuit board are exemplified below. It should be noted that the shipment of the printed circuit board needs to meet at least 5 test requirements, including pore size, profile, thermal stress, impedance, gold-nickel thickness. Wherein, table 1 is the pore diameter measurement result, table 2 is the shape measurement result, table 3 is the thermal stress test result, table 4 is the impedance test result, and table 5 is the gold-nickel thickness measurement result.

As shown in table 1, the numbers 1-6 respectively represent the numbers of different holes, the standards of different holes are different, the measurement data corresponds to three columns of data, each column of data corresponds to one printed circuit board, and when the measurement data is within the negative tolerance or positive tolerance range allowed by the standard, the printed circuit board passes the aperture test.

TABLE 1

As shown in table 2, the numbers 1 to 10 respectively indicate different size standards, and it should be noted that since the shape of the printed circuit board may not be a regular rectangle, one printed circuit board may include a plurality of lengths, widths, etc., and thus may include a plurality of size standards. The measured data corresponds to three columns of data, each column of data corresponds to a printed circuit board, and when the measured data is within a negative tolerance or a positive tolerance range allowed by a standard, the printed circuit board passes the aperture test.

TABLE 2

As shown in table 3, number 1 indicates a printed circuit board, and the printed circuit board passed the thermal stress test when the printed circuit board was subjected to the thermal stress test, visually without the phenomena of bubbles, delamination, and popping, and when the magnifier was observed without the phenomena of hole cracking and corner breakage.

TABLE 3 Table 3

As shown in table 4, reference numerals 1 to 4 indicate the serial numbers of the printed circuit boards, the impedance standards of the signal lines in the different circuit board layers may be different, the impedance standards of the different signal lines in the same circuit board layer may be different, and the impedance of the radio frequency impedance line in the first circuit board layer is 50 ohm impedance, and the impedance of the USB signal line in the third circuit board layer is 90 ohm impedance, for example. The printed circuit board passes the impedance test when the impedance of the signal line is within a negative tolerance or a positive tolerance allowed by the standard. Both columns of first circuit-board layers in table 4 represent the impedance of different signal lines in the first circuit-board layer.

TABLE 4 Table 4

As shown in Table 5, the numbers 1-5 indicate the numbers of the printed circuit boards, and the circuit board layers are provided with gold plating, nickel plating and the like, and the thicknesses of the circuit boards are required to be measured after the gold plating and the nickel plating, and the printed circuit boards pass the gold-nickel thickness test when Jin Hou and the nickel thickness are within the negative tolerance or the positive tolerance range allowed by the standard.

TABLE 5

In other embodiments, as shown in fig. 3, the buried via 300 penetrates the core layer 101, the four circuit board layers and the three prepreg layers on one side of the core layer 101, and the four circuit board layers and the three prepreg layers on the other side of the core layer 101, so as to form a ten-layer 1-level printed circuit board, and the buried via 300 penetrates the fifteen-layer structure.

Specifically, the buried hole 300 penetrates through all layers between the second circuit board layer 112 and the ninth circuit board layer 119, and the first prepreg layer 121 and the eighth prepreg layer 128 at two ends of the buried hole 300 are 1037 prepregs, and the second prepreg layer 122, the third prepreg layer 123, the fourth prepreg layer 124, the fifth prepreg layer 125, the sixth prepreg layer 126 and the seventh prepreg layer 127 are 1017 prepregs.

In addition, the first blind hole 301 is formed in the first circuit board layer 111 and the first prepreg layer 121, the first blind hole 301 is formed in the eighth prepreg layer 128 and the tenth circuit board layer 120, and the first blind hole 301 and the buried hole 300 form an alignment structure, so that the fabrication of the ten-layer 1-stage printed circuit board is completed through the one alignment structure.

In other embodiments, as shown in fig. 4, the buried via 300 penetrates the core layer 101, the three circuit board layers and the two prepreg layers on one side of the core layer 101, and the three circuit board layers and the two prepreg layers on the other side of the chip layer, so as to form a ten-layer 2-level printed circuit board, and the buried via 300 penetrates the eleven-layer structure.

Specifically, the buried hole 300 penetrates through all layers between the third circuit board layer 113 and the eighth circuit board layer 118, and the second prepreg layer 122 and the seventh prepreg layer 127 at two ends of the buried hole 300 are 1037 prepregs, the first prepreg layer 121, the third prepreg layer 123, the fourth prepreg layer 124, the fifth prepreg layer 125, the sixth prepreg layer 126, and the eighth prepreg layer 128 are 1017 prepregs.

In addition, the second blind hole 302 is formed in the second circuit board layer 112 and the second prepreg layer 122, the second blind hole 302 is formed in the seventh prepreg layer 127 and the ninth circuit board layer 119, the second blind hole 302 and the buried hole 300 form an alignment structure, the first blind hole 301 is formed in the first circuit board layer 111 and the first prepreg layer 121, the first blind hole 301 is formed in the eighth prepreg layer 128 and the tenth circuit board layer 120, and the first blind hole 301 and the second blind hole 302 form an alignment structure, thereby completing the fabrication of the ten-layer 2-stage printed circuit board through the two alignment structures.

In other embodiments, as shown in fig. 5, the buried via 300 penetrates the core layer 101, one circuit board layer on one side of the core layer 101, and one circuit board layer on the other side of the chip layer, so as to form a ten-layer 4-level printed circuit board, where the buried via 300 penetrates the three-layer structure.

Specifically, the buried hole 300 penetrates through the fifth circuit board layer 115, the core board layer 101 and the sixth circuit board layer 116, and the fourth prepreg layer 124 and the fifth prepreg layer 125 at two ends of the buried hole 300 are 1037 prepregs, and the first prepreg layer 121, the second prepreg layer 122, the third prepreg layer 123, and the sixth prepreg layer 126, the seventh prepreg layer 127 and the eighth prepreg layer 128 are 1017 prepregs.

In addition, a fourth blind hole 304 is formed in the fourth circuit board layer 114 and the fourth prepreg layer 124, a fourth blind hole 304 is formed in the fifth prepreg layer 125 and the seventh circuit board layer 117, and the fourth blind hole 304 and the buried hole 300 form an alignment structure. A third blind hole 303 is formed in the third wiring board layer 113 and the third prepreg layer 123, a third blind hole 303 is formed in the sixth prepreg layer 126 and the eighth wiring board layer 118, and a positioning structure is formed by the third blind hole 303 and the fourth blind hole 304. The second circuit board layer 112 and the second prepreg layer 122 have a second blind hole 302 formed therein, the seventh prepreg layer 127 and the ninth circuit board layer 119 have a second blind hole 302 formed therein, and the second blind hole 302 and the third blind hole 303 form an alignment structure. First blind holes 301 are formed in the first circuit board layer 111 and the first prepreg layer 121, first blind holes 301 are formed in the eighth prepreg layer 128 and the tenth circuit board layer 120, and the first blind holes 301 and the second blind holes 302 form an alignment structure, so that manufacturing of the ten-layer 4-level printed circuit board is completed through the four alignment structures.

In some embodiments, a ten layer circuit board of a printed circuit board includes: two device layers, three secondary layers, three wiring layers, one main layer and one power supply layer. Specifically, the first circuit board layer 111 is a device layer, the second circuit board layer 112 is a secondary layer, the third circuit board layer 113 is a routing layer, the fourth circuit board layer 114 is a primary layer, the fifth circuit board layer 115 is a routing layer, the sixth circuit board layer 116 is a secondary layer, the seventh circuit board layer 117 is a power layer, the eighth circuit board layer 118 is a routing layer, the ninth circuit board layer 119 is a secondary layer, and the tenth circuit board layer 120 is a device layer. The first wiring board layer 111 and the tenth wiring board layer 120 are device layers for providing devices, which may be, for example, memory devices, which may be implemented by any type of volatile or nonvolatile memory device or a combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk. The surface layer of the device layer can be provided with a small number of short lines, the inner layer is cut as soon as possible, and the interference of signal lines can be reduced by wiring on the inner layer of the device layer. The second circuit board layer 112, the sixth circuit board layer 116 and the ninth circuit board layer 119 are sub-layers, and the second circuit board layer 112 is used for setting a small amount of fan-out stubs at the BGA (Ball Grid Array Package, ball grid array fan-out) position, and switching to the third circuit board layer 113 as soon as possible, wherein the fan-out stubs are wires from the device pads to adjacent vias. The local set PDN (power delivery network, power distribution network) of the sixth wiring board layer 116 emulates a power line, and the remaining part sets a ground line. The local placement of the ninth wiring board layer 119 connects the stubs and switches to the eighth wiring board layer 118 as soon as possible. The third circuit board layer 113, the fifth circuit board layer 115 and the eighth circuit board layer 118 are routing layers, the third circuit board layer 113 is used for setting a normal signal line and a part of important signal lines, the fifth circuit board layer 115 is used for setting an important signal line, the eighth circuit board layer 118 is used for setting a normal signal line and an important signal line, the important signal line is a signal line with a frequency greater than a preset value, and the preset value can be several or tens of MHz, for example. The fourth circuit board layer 114 is a main ground layer for setting a ground line. And because the fourth wiring board layer 114 and the sixth wiring board layer 116 are ground layers, the important signal lines of the fifth wiring board layer 115 can be three-dimensionally grounded. The seventh wiring board layer 117 is a power layer for setting PDN emulation power and ground lines.

In some embodiments, the power plane and the stratum may increase the near-end capacitance, reducing the risk of PDN emulation failing. And ground holes can be added in the capacitive ground pads and the spare areas of the PDN power supply, so that the ground plane effective connection is increased, and the ESD (electrostatic discharge) risk is reduced.

Fig. 6 shows a layout of a printed circuit board. As shown in fig. 6, the printed circuit board includes a processor region 100, a power supply region 3, a microcontroller region 200, and a radio frequency region 6 sequentially arranged in a first direction, the processor region 100 includes a processor radio frequency region 1 and a processor power supply region 2 sequentially arranged in the first direction, and the microcontroller region 200 includes a microcontroller memory region 4 and a microcontroller power supply region 5 sequentially arranged in the first direction.

In fig. 6, the processor power section 2 is located on the right side of the processor radio frequency section 1, the power supply section 3 is located on the right side of the processor section 100, the microcontroller section 200 is located on the right side of the power supply section 3, the microcontroller power section 5 is located on the right side of the microcontroller storage section 4, and the radio frequency section 6 is located on the right side of the microcontroller section 200.

The processor area 100 is an area where a processor is located, the microcontroller area 200 is an area where a microcontroller is located, the power supply area 3 is an area where a power supply module is located, the radio frequency area 6 is an area where a complete machine radio frequency module is located, the processor radio frequency area 1 is an area where a radio frequency module of the processor is located, the processor power supply area 2 is an area where a power supply module of the processor is located, the microcontroller storage area 4 is an area where a memory module of the microcontroller is located, and the microcontroller power supply area 5 is an area where a power supply module of the microcontroller is located.

The whole machine radio frequency module is used for sending the received signals to the processor through the radio frequency module of the processor, and the radio frequency area 6 is connected with the processor radio frequency area 1. The storage module of the microcontroller is used for storing information, and the processor is used for responding operation by using the information stored in the storage module of the microcontroller, and then the microcontroller storage area 4 is connected with the processor area 100. The power supply module is used for supplying power to the power supply module of the processor and the power supply module of the microcontroller, the power supply area 3 is connected with the processor power supply area 2 and the microcontroller power supply area 5, the power supply module of the processor can supply power to the processor and the microcontroller, the power supply module of the microcontroller can supply power to the microcontroller and the processor, and the processor power supply area 2 is connected with the microcontroller power supply area 5.

The processor may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), etc. The general purpose processor may be a microprocessor, but in the alternative, it may be any conventional processor or the like.

It should be noted that, in the printed circuit board of fig. 6, a lot of radio frequency wires need to be routed between the radio frequency area 6 and the radio frequency area 1 of the processor, including a lot of high-speed wires and important signal wires, and a lot of layers and routing space need to be occupied. The power lines from the processor power supply area 2 to the power supply area 3 and the microcontroller power supply area 5 need to be simulated, and the distance between the processor power supply area 2 and the microcontroller power supply area 5 is far, so that the power line width needs to be increased to pass PDN simulation, and a lot of space is occupied. And the power line between the power supply area 3 and the microcontroller power area 5 is overlapped and crossed with the power line between the processor power area 2 and the microcontroller power area 5, so that the wiring difficulty is increased. The printed circuit board in fig. 2 therefore needs to be designed as a 10-layer printed circuit board of any level, including four levels and more.

In order to further reduce wiring and reduce processing difficulty, the applicant proposes another layout of a printed circuit board, as shown in fig. 7 and 8, the printed circuit board includes a radio frequency area 6, a processor area 100 and a microcontroller area 200 sequentially arranged in a first direction, the microcontroller area 200 and a power supply area 3 sequentially arranged in a second direction, the first direction and the second direction are two directions perpendicular to each other on a plane, the printed circuit board includes a core board layer 101 and stacked layers symmetrical on both sides of the core board layer 101 in a third direction, the third direction is a direction perpendicular to the first direction and the second direction, the processor area 100 includes a processor radio frequency area 1 and a processor power supply area 2 sequentially arranged in the first direction, and the microcontroller area 200 includes a microcontroller memory area 4 and a microcontroller power supply area 5 sequentially arranged in the first direction. The radio frequency area 6 is connected with the processor radio frequency area 1, the processor power area 2 is connected with the power supply area 3 and the microcontroller power area 5, the power supply area 3 is connected with the microcontroller power area 5, and the processor area 100 is connected with the microcontroller storage area 4.

The wiring between the radio frequency area 6 and the processor radio frequency area 1 can not be blocked by the power supply area 3 and the microcontroller area 200, the simulation power line between the processor power supply area 2 and the microcontroller power supply area 5 can not be blocked by the power supply area 3, the wiring between the processor area 100 and the microcontroller storage area 4 can not be blocked by the power supply area 3, and the wiring between any two areas is not crossed, so that the wiring difficulty is reduced, and the wiring occupation space is reduced. Moreover, since the distance between the processor power supply area 2 and the microcontroller power supply area 5 is relatively small, the line width of the emulation power supply line between the two can be properly reduced, so that the space occupied by the emulation power supply line between the two is reduced, and the PDN emulation is relatively easy to pass.

Thus, the printed circuit board of fig. 7 and 8 can reduce wiring difficulty and reduce the number of steps, for example, a 10-layer 3-step printed circuit board.

In some embodiments, as shown in fig. 7, in the second direction, the first end of the microcontroller region 200 is higher than the first end of the processor region 100, the second end of the microcontroller region 200 is lower than the first end of the processor region 100, the first end of the power supply region 3 is higher than the second end of the processor region 100, and the second end of the power supply region 3 is lower than the second end of the processor region 100. The first end is, for example, the upper end in fig. 7 and 8, and the second end is the lower end.

In other embodiments, as shown in fig. 8, in the second direction, the first end of the power supply region 3 is higher than the first end of the processor region 100, the second end of the power supply region 3 is lower than the first end of the processor region 100, the first end of the microcontroller region 200 is higher than the second end of the processor region 100, and the second end of the microcontroller region 200 is lower than the second end of the processor region 100.

In some embodiments, a printed circuit board includes: a first metal wire set connecting the radio frequency area 6 and the processor radio frequency area 1, a second metal wire set connecting the processor power area 2 and the power supply area 3, a third metal wire set connecting the processor power area 2 and the microcontroller power area 5, a fourth metal wire set connecting the microcontroller power area 5 and the power supply area 3, and a fifth metal wire set connecting the processor area 100 and the microcontroller storage area 4.

The printed circuit board provided in the embodiment of the application is described in detail above, including: the stacked layers are symmetrical on two sides of the core board layer and comprise a plurality of circuit board layers and prepreg layers between the adjacent circuit board layers, the printed circuit board further comprises buried holes penetrating through the core board layers, part of the circuit board layers and part of the prepreg layers, the glue content of the prepreg layers at two ends of the buried holes is first glue content, the glue content of the rest prepreg layers is second glue content, the first glue content is larger than the second glue content, the thickness of the prepreg layers at two ends of the buried holes is larger than the thickness of the rest prepreg layers, and the thickness of the printed circuit board is within 0.6 mm. According to the scheme, the stress phase difference during lamination is smaller through symmetrical stacked layers, the problem of warping degree is solved, and the performance of the printed circuit board is improved. Meanwhile, the glue filling amount of the buried holes is increased, so that the prepreg layer can effectively fill the buried holes, the problem of insufficient buried hole filling is solved, and the performance of the circuit board is further improved. And the thickness of the prepreg layers at the two ends of the buried hole is increased, and the thickness of the rest prepreg layers is reduced, so that the requirement of the ultrathin high-density circuit board can be met.

An embodiment of the present application further provides a mobile device, including the above printed circuit board. The printed circuit board can be used for watches or bracelets with the same thickness and the same platform chip.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments may be modified or some or all of the technical features may be replaced with equivalents. Such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims (7)

1. A printed circuit board, comprising:

The printed circuit board comprises a core board layer, a stacking layer which is symmetrical on two sides of the core board layer, wherein the stacking layer comprises a plurality of circuit board layers and prepreg layers between adjacent circuit board layers, and the printed circuit board also comprises buried holes which penetrate through the core board layer, part of the circuit board layers and part of the prepreg layers;

the glue content of the prepreg layers at the two ends of the buried hole is a first glue content, the glue content of the rest prepreg layers is a second glue content, and the first glue content is larger than the second glue content;

the thickness of the prepreg layers at the two ends of the buried hole is larger than that of the rest prepreg layers, and the thickness of the printed circuit board is within 0.6 mm;

the printed circuit board comprises ten circuit board layers, the buried holes penetrate through the core board layer, two circuit board layers and one prepreg layer on one side of the core board layer, and two circuit board layers and one prepreg layer on the other side of the core board layer;

the ten circuit board layers include: two device layers, three secondary layers, three wiring layers, one main layer and one power supply layer;

the printed circuit board comprises a first circuit board layer, a first prepreg layer, a second circuit board layer, a second prepreg layer, a third circuit board layer, a third prepreg layer, a fourth circuit board layer, a fourth prepreg layer, a fifth circuit board layer, a core board layer, a sixth circuit board layer, a fifth prepreg layer, a seventh circuit board layer, a sixth prepreg layer, an eighth circuit board layer, a seventh prepreg layer, a ninth circuit board layer, an eighth prepreg layer and a tenth circuit board layer which are sequentially stacked;

The buried hole penetrates through the fourth circuit board layer, the fourth prepreg layer, the fifth circuit board layer, the core board layer, the sixth circuit board layer, the fifth prepreg layer and the seventh circuit board layer;

the printed circuit board further includes:

a third blind hole formed in the third circuit board layer and the third prepreg layer, a third blind hole formed in the sixth prepreg layer and the eighth circuit board layer, and an alignment structure formed by the third blind hole and the buried hole;

the second blind holes are formed in the second circuit board layer and the second prepreg layer, the second blind holes are formed in the seventh prepreg layer and the ninth circuit board layer, and the second blind holes and the third blind holes form an alignment structure;

the first blind holes are formed in the first circuit board layer and the first prepreg layer, the eighth prepreg layer and the tenth circuit board layer, and the first blind holes and the second blind holes form an alignment structure.

2. The printed circuit board of claim 1, wherein the prepreg layers at both ends of the buried via are 1037 prepregs and the remaining prepreg layers are 1017 prepregs.

3. The printed circuit board of claim 1, wherein the printed circuit board comprises:

the device comprises a radio frequency region, a processor region and a microcontroller region which are sequentially arranged in a first direction, wherein the processor region comprises a processor radio frequency region and a processor power supply region which are sequentially arranged in the first direction, and the microcontroller region comprises a microcontroller storage region and a microcontroller power supply region which are sequentially arranged in the first direction;

the microcontroller area and the power supply area are sequentially arranged in a second direction, and the first direction and the second direction are two directions which are perpendicular to each other on a plane;

in a third direction, the printed circuit board comprises the core board layer and stacked layers which are symmetrical on two sides of the core board layer, wherein the third direction is a direction perpendicular to the first direction and the second direction;

the power supply area is connected with the microcontroller power supply area, and the processor area is connected with the microcontroller storage area.

4. A printed circuit board according to claim 3, wherein in the second direction the first end of the microcontroller section is higher than the first end of the processor section, the second end of the microcontroller section is lower than the first end of the processor section, the first end of the power supply section is higher than the second end of the processor section, and the second end of the power supply section is lower than the second end of the processor section.

5. A printed circuit board according to claim 3, wherein in the second direction the first end of the power supply area is higher than the first end of the processor area, the second end of the power supply area is lower than the first end of the processor area, the first end of the microcontroller area is higher than the second end of the processor area, and the second end of the microcontroller area is lower than the second end of the processor area.

6. The printed circuit board of claim 3, wherein the printed circuit board further comprises:

the first metal wire set is connected with the radio frequency area and the processor radio frequency area, the second metal wire set is connected with the processor power area and the power supply area, the third metal wire set is connected with the processor power area and the microcontroller power area, the fourth metal wire set is connected with the microcontroller power area and the power supply area, and the fifth metal wire set is connected with the processor area and the microcontroller storage area.

7. A mobile device comprising the printed circuit board of any one of claims 1-6.

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