CN116131774A - Power amplifier and radio frequency front-end circuit - Google Patents
Power amplifier and radio frequency front-end circuit Download PDFInfo
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- CN116131774A CN116131774A CN202211726539.6A CN202211726539A CN116131774A CN 116131774 A CN116131774 A CN 116131774A CN 202211726539 A CN202211726539 A CN 202211726539A CN 116131774 A CN116131774 A CN 116131774A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/302—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in bipolar transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
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Abstract
The invention discloses a power amplifier and a radio frequency front-end circuit. The power amplifier comprises a first amplifying transistor and a first bias circuit; the first bias circuit includes a first bias transistor; the first end of the first bias transistor is connected with the bias power supply end so as to receive a first current output by the bias power supply end; the second end of the first bias transistor is suspended or grounded; the third terminal of the first bias transistor is coupled to the input terminal of the first amplifying transistor to output a first bias current to the input terminal of the first amplifying transistor. The second end of the first bias transistor is suspended or grounded, so that the second end of the first bias transistor does not receive interference signals, the accuracy of the first bias current output by the first bias transistor is ensured, and the linearity of a circuit where the power amplifier is positioned is adjusted more sensitively.
Description
Technical Field
The present invention relates to the field of radio frequency communications technologies, and in particular, to a power amplifier and a radio frequency front-end circuit.
Background
The power amplifier is a very critical module in the radio frequency communication system, especially in a wireless receiver, and is mainly used for amplifying a radio frequency signal with low power and then radiating out through an antenna to perform information communication. The existing power amplifier generally comprises an amplifying transistor and a bias circuit, wherein one end of the bias circuit is coupled to the input end of the amplifying transistor and is used for providing bias current for the input end of the amplifying transistor so as to ensure the normal operation of the amplifying transistor, but the linearity of the circuit where the power amplifier is positioned cannot be ensured when the bias circuit provides bias current for the amplifying transistor.
Disclosure of Invention
The embodiment of the invention provides a power amplifier and a radio frequency front-end circuit, which are used for solving the problem of poor linearity of the existing power amplifier.
The embodiment of the invention provides a power amplifier, which comprises a first amplifying transistor and a first bias circuit;
the first bias circuit includes a first bias transistor;
the first end of the first bias transistor is connected with a bias power supply end so as to receive a first current output by the bias power supply end;
the second end of the first bias transistor is suspended or grounded;
the third terminal of the first bias transistor is coupled to the input terminal of the first amplifying transistor to output a first bias current to the input terminal of the first amplifying transistor.
Preferably, the first bias circuit further comprises a first bias resistor, and a third terminal of the first bias transistor is coupled to the input terminal of the first amplifying transistor through the first bias resistor.
Preferably, the first bias current output from the third terminal of the first bias transistor is configured to be related to the first current output from the bias power supply terminal and the output power of the power amplifier.
Preferably, the first bias circuit is configured to improve gain flatness of the first amplifying transistor.
Preferably, when the output power of the power amplifier reaches a saturated state when the first current output by the bias power supply terminal is [0.01ma,0.5ma ], the first bias current output by the third terminal of the first bias transistor is [0.05ma,0.1ma ].
Preferably, when the first current output by the bias power supply terminal is [0.01ma,0.5ma ], and the power of the power amplifier reaches the power rollback [4dB-6dB ] before the saturation state, the first bias current output by the third terminal of the first bias transistor is [ 0.04 ma,0.4ma ].
Preferably, when the first current output by the bias power supply terminal is [0.01mA,0.5mA ], and the power of the power amplifier reaches the power rollback [4dB-6dB ] before the saturation state, the first bias current output by the third terminal of the first bias transistor is [0.001mA,0.1mA ].
Preferably, the power amplifier further comprises a switch circuit, a first end of the switch circuit is connected with a second end of the first bias transistor, a second end of the switch circuit is suspended or grounded, and a third end of the switch circuit is connected with a power supply end.
Preferably, the switching circuit is configured to switch the first end of the switching circuit to be connected with the second end or the third end of the switching circuit according to the operation mode of the power amplifier.
Preferably, the switching circuit is configured to control the first end of the switching circuit to be connected with the second end of the switching circuit when the power mode of the power amplifier is the first power mode; and when the power mode of the power amplifier is a second power mode, controlling the second end of the switching circuit to be connected with the third end of the switching circuit, wherein the second power mode is larger than the first power mode.
Preferably, the switching circuit is configured to control the first end of the switching circuit to be connected with the second end of the switching circuit when the working frequency band of the power amplifier is a first frequency band; and when the working frequency band of the power amplifier is a second frequency band, controlling the second end of the switching circuit to be connected with the third end of the switching circuit, wherein the second frequency band is larger than the first frequency band.
Preferably, the switch circuit comprises a single-pole double-throw switch, the fixed end of the single-pole double-throw switch is connected with the second end of the first bias transistor, the first movable end of the single-pole double-throw switch is suspended or grounded, and the second movable end of the single-pole double-throw switch is connected with the power supply end.
Preferably, the first bias transistor is a bias MOS transistor, a gate of the bias MOS transistor is a first end of the first bias transistor, a drain of the bias MOS transistor is a second end of the first bias transistor, and a source of the bias MOS transistor is a third end of the first bias transistor;
or the first bias transistor is a bias BJT transistor, the substrate of the bias BJT transistor is a first end of the first bias transistor, the collector electrode of the bias BJT transistor is a second end of the first bias transistor, and the emitter of the bias BJT transistor is a third end of the first bias transistor.
Preferably, the power amplifier further comprises a second bias circuit comprising a second bias transistor;
the first end of the second bias transistor is connected with a bias power supply end so as to receive a second current output by the bias power supply end;
the second end of the second bias transistor is suspended or grounded;
the third terminal of the second bias transistor is coupled to the input terminal of the first amplifying transistor to output a second bias current to the input terminal of the first amplifying transistor.
Preferably, the power amplifier further comprises a second amplifying transistor and a third bias circuit,
An input of the second amplifying transistor is coupled to an output of the first amplifying transistor;
the third bias circuit includes a third bias transistor;
the first end of the third bias transistor is connected with a bias power supply end so as to receive third current output by the bias power supply end;
the second end of the third bias transistor is suspended or grounded;
a third terminal of the third bias transistor is coupled to the input terminal of the second amplifying transistor to output a third bias current to the input terminal of the second amplifying transistor.
The embodiment of the invention provides a radio frequency front-end circuit, which comprises the power amplifier.
The power amplifier and the radio frequency front-end circuit are characterized in that a first end of a first bias transistor in the first bias circuit and a bias power supply end are connected with an input end of a first amplifying transistor in a coupling mode, so that the first bias transistor can output a first bias current, and normal operation of the first amplifying transistor is guaranteed; the second end of the first bias transistor is suspended or grounded, so that the magnitude of the first bias current output by the first bias transistor can be adjusted more sensitively, the accuracy of the first bias current output by the first bias transistor is ensured, and the linearity of a circuit in which the power amplifier is positioned is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a power amplifier according to an embodiment of the invention;
FIG. 2 is another schematic circuit diagram of a power amplifier according to an embodiment of the invention;
FIG. 3 is another schematic circuit diagram of a power amplifier according to an embodiment of the invention;
FIG. 4 is another schematic circuit diagram of a power amplifier according to an embodiment of the invention;
FIG. 5 is another schematic circuit diagram of a power amplifier according to an embodiment of the invention;
FIG. 6 is another schematic circuit diagram of a power amplifier according to an embodiment of the invention;
FIG. 7 is a graph showing AMAM formed by a simulation test of a power amplification circuit as a function of output power;
FIG. 8 is a table showing the AMPM formed by the power amplifier circuit in a simulation test as a function of output power;
FIG. 9 is a graph showing the variation of the first bias current output by the first bias transistor with the output power, which is formed by the simulation test of the power amplifying circuit;
FIG. 10 is a graph showing the variation of the output power with the first current received by the first bias transistor formed by the power amplifier circuit performing a simulation test;
FIG. 11 is a graph of supply current of a first amplifying transistor formed by a simulation test of a power amplifying circuit as a function of an input signal;
fig. 12 is a graph of supply current of a second amplifying transistor formed by a simulation test of a power amplifying circuit as a function of an input signal.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for the same elements throughout for clarity.
It will be understood that when an element or layer is referred to as being "on" …, "" adjacent to "…," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" …, "" directly adjacent to "…," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under …," "under …," "below," "under …," "above …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under …" and "under …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for the purpose of providing a thorough understanding of the present invention, detailed structures and steps are presented in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.
The embodiment of the invention provides a power amplifier, as shown in fig. 1 and 2, which comprises a first amplifying transistor Q1 and a first bias circuit 1; the first bias circuit 1 includes a first bias transistor M1; a first end of the first bias transistor M1 is connected with the bias power end Iref to receive a first current output by the bias power end Iref; the second end of the first bias transistor M1 is suspended or grounded; the third terminal of the first bias transistor M1 is coupled to the input terminal of the first amplifying transistor Q1 to output a first bias current to the input terminal of the first amplifying transistor Q1.
The first amplifying transistor Q1 is a transistor for realizing signal amplifying processing in the power amplifier. The first bias circuit 1 is a circuit coupled to an input terminal of the first amplifying transistor Q1 for providing the first amplifying transistor Q1 with a first bias current. The first bias transistor M1 is a transistor for forming a first bias current in the first bias circuit 1.
As an example, the first bias circuit 1 includes a first bias transistor M1. The first end of the first bias transistor M1 is connected to the bias power terminal Iref, specifically, the output end of the bias power terminal Iref, and is capable of receiving the first current output by the bias power terminal Iref. As shown in fig. 1, the second terminal of the first bias transistor M1 may be floating, i.e., the second terminal of the first bias transistor M1 is not connected to the power supply terminal Vbatt or other components, so that the second terminal of the first bias transistor M1 does not receive the power supply voltage. In a specific embodiment, if the first bias circuit 1 is a secondary bias circuit, the second end of the first bias transistor M1 is suspended, so that the magnitude of the first bias current output by the first bias transistor M1 can be sensitively adjusted, and the accuracy of the first bias current output by the first bias transistor M1 is ensured. In a specific embodiment, if the first bias circuit 1 is a main bias circuit, the second end of the first bias transistor M1 is suspended, so that the output power of the power amplifier can be ensured to be close to or reach the saturated power, and the power supply current will not be expanded, thereby improving the durability (ruggeddess) of the power amplifier. As shown in fig. 2, the second terminal of the first bias circuit 1 may also be grounded, i.e. the second terminal of the first bias transistor M1 is grounded, so that the second terminal of the first bias transistor M1 does not receive the supply voltage. In a specific embodiment, if the first bias circuit 1 is a secondary bias circuit, the second ground of the first bias transistor M1 is grounded, so that the magnitude of the first bias current output by the first bias transistor M1 can be sensitively adjusted, and the accuracy of the first bias current output by the first bias transistor M1 is ensured. The third terminal of the first bias transistor M1 is coupled to the input terminal of the first amplifying transistor Q1, and a first bias current may be input to the input terminal of the first amplifying transistor Q1, so that the first amplifying transistor Q1 operates normally based on the first bias current. In a specific embodiment, if the first bias circuit 1 is a main bias circuit, the second ground of the first bias transistor M1 can ensure that the output power of the power amplifier will not expand when approaching or reaching the saturated power, thereby improving the durability (ruggeddess) of the power amplifier. Preferably, the present embodiment mainly uses the first bias circuit as the secondary bias circuit as an exemplary description.
In general, in an ideal linear power amplifier, the phase difference between the input and output should be zero or constant, i.e., the output signal is a signal formed by amplifying the amplitude of the output signal and adding a certain delay. In a practical power amplifier, AMAM distortion and/or AMPM distortion may occur due to the nonlinear effects of the power amplifier. AMAM refers to distortion in the amplitude of an output signal and an input signal, for example, when the input signal swings below a threshold voltage or above a saturation voltage, the output voltage signal is truncated or truncated, i.e., AMAM distortion. AMPM refers to a change in the amplitude of an input signal to a nonlinear power amplifier, resulting in a change in the phase difference between the output and input signals.
Compared with the connection mode that the second end of the first bias transistor M1 is connected with the power supply end Vbatt or other components in the related art, the second end of the first bias transistor M1 is suspended or grounded, so that not only can the durability (ruggeddess) of the power amplifier be improved, but also the first bias current output by the first bias transistor M1 can be reduced, and meanwhile, the first bias current output by the first bias circuit 1 is enabled to be more accurate, thereby avoiding occurrence of AMAM distortion and/or AMPM distortion, and further improving the linearity of a circuit in which the power amplifier is located. In this example, when the second terminal of the first bias transistor M1 is connected to the power supply terminal Vbatt or other components, the power supply terminal Vbatt or other components will output a voltage to the first bias transistor M1, and this voltage will cause the first bias current output by the first bias transistor M1 to increase in advance, so that the AMAM curve and/or the AMPM curve of the power amplifier will expand when approaching or reaching the saturated power, thereby affecting the linearity of the circuit in which the power amplifier is located. In view of this, the second end of the first bias transistor M1 is suspended or grounded, so that an expansion phenomenon of an AMAM curve and/or an AMPM curve of the power amplifier is avoided when the AMAM curve is close to or reaches saturated power, and linearity of a circuit in which the power amplifier is located is optimized and durability (ruggeddess) of the power amplifier is improved.
Compared with the implementation manner of providing the first bias current to the first amplifying transistor Q1 through the bias diode in the related art, the second end of the first bias transistor M1 is suspended or grounded, and the first bias current output by the first bias circuit 1 can be more accurate due to the difference of the performances of the first bias transistor M1 and the bias diode, so that the linearity of the circuit where the power amplifier is located can be more sensitively adjusted, and the durability (ruggeddess) of the power amplifier can be improved.
In order to verify that the first bias circuit 1 provided in this embodiment can ensure the effect of improving the linearity of the circuit in which the power amplifier is located, a simulation test can be performed under the same condition, and in the simulation test process, the power amplifier is designed to work in a specific working frequency band, and the following four working conditions are tested: the first working condition (curve 1) is that the bias power supply end Iref is closed; the second working condition (curve 2) is that the second end of the first bias transistor M1 is not connected to the power supply end Vbatt (i.e. the second end of the first bias transistor M1 is suspended or grounded), and the bias power supply end Iref is turned on, i.e. the scheme provided by the embodiment; the third working condition (curve 3) is that the second end of the first bias transistor M1 is connected with the power supply end Vbatt, and the bias power supply end Iref is turned on, namely, the scheme of the first related technology; the fourth condition (curve 4) is that the bias diode is turned on and the bias power terminal Iref is turned on, i.e. the second related art scheme. In the simulation test process, mapping curves between the output power Pout of the power amplifier and different indexes are required to be acquired respectively.
Fig. 7 is a mapping curve between the output power Pout of the power amplifier and the corresponding AMAM, where the mapping curve may reflect the gain variation of the power amplifier to a certain extent, and further reflect the linearity variation of the circuit in which the power amplifier is located. As can be seen from the curves 2 and 3, when the first bias transistor M1 is provided in the first bias circuit 1 and the first bias current is provided to the first amplifying transistor Q1 through the first bias transistor M1, the AMAM curve formed when the second end of the first bias transistor M1 is not connected to the power supply terminal Vbatt (i.e., the second end of the first bias transistor M1 is suspended or grounded) is flatter than the AMAM curve formed when the second end of the first bias transistor M1 is connected to the power supply terminal Vbatt, and no expansion phenomenon occurs when the second end of the first bias transistor M1 approaches or reaches the saturated power, which indicates that the linearity of the circuit in which the power amplifier is located is better when the second end of the first bias transistor M1 is not connected to the power supply terminal Vbatt (i.e., the second end of the first bias transistor M1 is suspended or grounded). As can be seen from the curves 2 and 4, the AMAM curve formed when the second end of the first bias transistor M1 is not connected to the power supply terminal Vbatt (i.e. the second end of the first bias transistor M1 is suspended or grounded) is flatter than the AMAM curve formed when the bias diode is used to provide the first bias current, which means that the linearity of the circuit in which the power amplifier is located is better when the second end of the first bias transistor M1 is not connected to the power supply terminal Vbatt (i.e. the second end of the first bias transistor M1 is suspended or grounded).
Fig. 8 is a mapping curve between the output power Pout of the power amplifier and its corresponding AMPM, which can reflect the gain variation of the power amplifier to a certain extent, and thus reflect the linearity variation of the circuit in which the power amplifier is located. As can be seen from the curves 2 and 3, when the first bias transistor M1 is provided in the first bias circuit 1 and the first bias current is provided to the first amplifying transistor Q1 through the first bias transistor M1, the AMPM curve formed when the second end of the first bias transistor M1 is not connected to the power supply terminal Vbatt (i.e., the second end of the first bias transistor M1 is suspended or grounded) is flatter than the AMPM curve formed when the second end of the first bias transistor M1 is connected to the power supply terminal Vbatt, and no expansion phenomenon occurs when the second end of the first bias transistor M1 approaches or reaches the saturated power, which indicates that the linearity of the circuit in which the power amplifier is located is better when the second end of the first bias transistor M1 is not connected to the power supply terminal Vbatt (i.e., the second end of the first bias transistor M1 is suspended or grounded). As can be seen from the curves 2 and 4, the AMPM curve formed when the second end of the first bias transistor M1 is not connected to the power supply terminal Vbatt (i.e. the second end of the first bias transistor M1 is suspended or grounded) is far flatter than the AMPM curve formed when the bias diode is used to provide the first bias current, which means that the linearity of the circuit in which the power amplifier is located is better when the second end of the first bias transistor M1 is not connected to the power supply terminal Vbatt (i.e. the second end of the first bias transistor M1 is suspended or grounded). When the phase frequency characteristic of the system is calculated, the phase is extracted by adopting an arctangent function, the computer calculates that the angles of the first quadrant and the second quadrant are [0, pi ], the angles of the third quadrant and the fourth quadrant are [ -pi, 0], but the actual calculation result generates phase jump, and the jump amplitude is 2 pi, namely the phase winding. The function of the unwrap function is to unwrap, so that the phase does not jump at pi, and thus the actual phase change is reflected, and the value of the unwrap function (i.e. the unwrap function value) can be determined as AMPM. In the default situation, when the unwrap function detects that the difference between the front point and the rear point of the data exceeds pi or other thresholds, the jump is considered to exist, and the AMPM exists.
In this embodiment, a first end of the first bias transistor M1 and the bias power supply end Iref in the first bias circuit 1, and a third end of the first bias transistor M1 is coupled to the input end of the first amplifying transistor Q1, so that the first bias transistor M1 can output a first bias current, and the normal operation of the first amplifying transistor Q1 is ensured; the second end of the first bias transistor M1 is suspended or grounded, so that the second end of the first bias transistor M1 does not receive voltage, and therefore the magnitude of the first bias current output by the first bias transistor M1 can be adjusted more sensitively, the accuracy of the first bias current output by the first bias transistor M1 is ensured, the linearity of a circuit where the power amplifier is located is further improved, and the durability (ruggeddess) of the power amplifier is further improved.
In an embodiment, the first bias circuit 1 further includes a first bias resistor R1, and the third terminal of the first bias transistor M1 is coupled to the input terminal of the first amplifying transistor Q1 through the first bias resistor R1.
As an example, the first bias circuit 1 further includes a first bias resistor R1, and the third terminal of the first bias transistor M1 is coupled to the input terminal of the first amplifying transistor Q1 through the first bias resistor R1, that is, one terminal of the first bias resistor R1 is connected to the third terminal of the first bias transistor M1, and the other terminal is coupled to the input terminal of the first amplifying transistor Q1. In this example, according to the performance of the first bias transistor M1, the resistance of the first bias resistor R1 is adjusted, so that the first bias current output by the third terminal of the first bias transistor M1 is within the design specification, so that the input terminal of the first amplifying transistor Q1 can receive the appropriate first bias current, and the first bias current is located at an appropriate static working point, thereby ensuring the normal operation of the first amplifying transistor Q1.
In an embodiment, the first bias current output from the third terminal of the first bias transistor M1 is configured to be related to the first current output from the bias power terminal Iref and the output power Pout of the power amplifier.
As an example, the third terminal of the first bias transistor M1 is coupled to the input terminal of the first amplifying transistor Q1, and the first bias current output by the third terminal of the first bias transistor M1 is provided to the first amplifying transistor Q1, which not only can determine whether the first amplifying transistor Q1 is at a proper static operating point, but also can affect the linearity of the power amplifier as a whole, so that the first bias current output by the third terminal of the first bias transistor M1 needs to be precisely controlled. In this example, since the second end of the first bias transistor M1 is suspended or grounded, the first end of the first bias transistor M1 is connected to the bias power supply end Iref, the third end of the first bias transistor M1 is connected to the first amplifying transistor Q1, and the output end of the first amplifying transistor Q1 is coupled to the input end of the power amplifier, in this case, the first bias current output by the third end of the first bias transistor M1 is related to the first current received by the first end and the output power of the output end of the power amplifier, the first current output by the bias power supply end Iref can be adjusted according to the actual requirement, and the output power Pout of the power amplifier can be controlled, so as to accurately control the first bias current output by the third end of the first bias transistor M1, so that the normal working requirement of the first amplifying transistor Q1 is met, and the linearity of the circuit where the power amplifier is located is ensured.
In an embodiment, the first bias circuit 1 is configured to improve the gain flatness of the first amplifying transistor Q1.
As an example, the first bias circuit 1 is connected to the first amplifying transistor Q1 and is configured to provide an input current required for guaranteeing the operation of the first amplifying transistor Q1, so that not only the first amplifying transistor Q1 can be operated at a proper static operating point to guarantee the normal operation of the first amplifying transistor Q1; the gain flatness of the first amplifying transistor Q1 can also be improved. That is, the input current provided by the first bias circuit 1 to the first amplifying transistor Q1 not only realizes the bias function, but also improves the gain flatness of the first amplifying transistor Q1, thereby guaranteeing the linearity of the circuit.
In one embodiment, when the first current outputted from the bias power terminal Iref is [0.01ma,0.5ma ], and the output power Pout of the power amplifier reaches the saturated state, the first bias current outputted from the third terminal of the first bias transistor M1 is [0.05ma,0.1ma ].
As an example, in order to make the power amplifier generate better linearity, the first current output by the bias power supply terminal Iref to the first terminal of the first bias transistor M1 may be controlled within the range of [0.01ma,0.5ma ], and the second terminal of the first bias transistor M1 is suspended or grounded, so that the first bias current output by the third terminal of the first bias transistor M1 is within the range of [0.05ma,0.1ma ], which may ensure the normal operation of the first amplifying transistor Q1 and the linearity of the circuit in which the power amplifier is located.
Fig. 9 is a mapping relationship between the first bias current output from the third terminal of the first bias transistor M1 and the output power thereof in the saturation region of the power amplifier operation. The first current output at the bias power terminal Iref is 0.2mA, and the simulation test shows that three conditions in fig. 7 and 8, in which the first bias current is generated, are as follows: (1) In the second working condition (curve 2), the second end of the first bias transistor M1 is not connected to the power supply end Vbatt (i.e., the second end of the first bias transistor M1 is suspended or grounded), and when the bias power supply end Iref is turned on, the first bias current output from the third end of the first bias transistor M1 is 0.16mA. (2) Under the third working condition (curve 3), the second end of the first bias transistor M1 is connected to the power supply end Vbatt, and when the bias power supply end Iref is turned on, the first bias current output from the third end of the first bias transistor M1 is 2mA. (3) Under the fourth working condition (curve 4), when the bias diode is conducted and the bias power supply terminal Iref is turned on, the first bias current output by the bias diode is 0.16mA. Therefore, when the first current outputted by the bias power supply terminal Iref is [0.01ma,0.5ma ], and the output power Pout of the power amplifier reaches a saturated state, the first bias current formed by suspending or grounding the second terminal of the first bias transistor M1 is smaller than the first bias current formed by connecting the second terminal of the first bias transistor M1 with the power supply terminal Vbatt, so that the first bias current with more accurate control output can be realized, and the linearity of the circuit in which the power amplifier is positioned is guaranteed.
In one embodiment, when the first current output by the bias power terminal Iref is [0.01ma,0.5ma ], the power back-off before the output power Pout of the power amplifier reaches the saturation state [4dB-6dB ], the first bias current output by the third terminal of the first bias transistor M1 is [ 0.04 ma,0.4ma ].
The power back-off refers to that the input power of the power amplifier is backed back by a specific decibel from a 1dB compression point (namely, the critical point of the linear region and the nonlinear region of the power amplifier), so that the power amplifier works at a level far smaller than the 1dB compression point, and the power amplifier is far away from the saturation region and enters the linear region, thereby improving the third-order intermodulation coefficient of the power amplifier and guaranteeing the linearity of a circuit where the power amplifier is positioned.
As an example, in order to make the power amplifier generate better linearity, the first current output by the bias power supply terminal Iref to the first terminal of the first bias transistor M1 may be controlled within the range of [0.01ma,0.5ma ], when the output power Pout of the power amplifier reaches the power back [4dB-6dB ] before the saturation state (i.e., before the output power Pout of the power amplifier does not reach the saturation state), since the second terminal of the first bias transistor M1 is suspended or grounded, the first bias current output by the third terminal of the first bias transistor M1 may be within the interval range of [0.004ma,0.4ma ], where the interval range of the first bias current is far smaller than the interval range of the first bias current provided by the third terminal of the first bias transistor M1 and the power supply terminal Vbatt or other components, which can realize the accurate control of the first bias current output by the first bias circuit 1, and can ensure the linearity of the circuit where the power amplifier is located.
In one embodiment, when the first current output by the bias power terminal Iref is [0.01ma,0.5ma ], the power back-off before the output power Pout of the power amplifier reaches the saturation state [4dB-6dB ], the first bias current output by the third terminal of the first bias transistor M1 is [0.001ma,0.1ma ].
As an example, in order to make the power amplifier generate better linearity, the first current output by the bias power supply terminal Iref to the first terminal of the first bias transistor M1 may be controlled within the range of [0.01ma,0.5ma ], and when the output power Pout of the power amplifier reaches the power backoff [4dB-6dB ] before the saturation state (i.e., before the output power Pout of the power amplifier does not reach the saturation state), since the second terminal of the first bias transistor M1 is suspended or grounded, the first bias current output by the third terminal of the first bias transistor M1 may be within the range of [0.001ma,0.1ma ], which is not only far smaller than the range of the first bias current provided by the third terminal of the first bias transistor M1 by the power supply terminal Vbatt or other components, but also smaller than the range where the bias diode provides the first bias current, which may realize accurate control of the first bias current output by the first bias circuit 1, which may ensure the normal operation of the first bias transistor Q1, and the linearity of the power amplifier may also be ensured.
Fig. 10 is a mapping relationship between the first current output by the bias power terminal Iref and the output power of the first bias transistor M1 when the power amplifier is in the unsaturated region. From the above simulation test, it can be seen that the three conditions in fig. 7 and 8, in which the first bias current is generated, are as follows: (1) In the second working condition (curve 2), the second end of the first bias transistor M1 is not connected to the power supply terminal Vbatt (i.e., the second end of the first bias transistor M1 is suspended or grounded), and when the bias power supply terminal Iref is turned on, the bias power supply terminal Iref outputs the first current. (2) In the third working condition (curve 3), the second end of the first bias transistor M1 is connected to the power supply terminal Vbatt, and when the bias power supply terminal Iref is turned on, the bias power supply terminal Iref outputs the first current. (3) Under the fourth working condition (curve 4), the bias diode is turned on, and when the bias power terminal Iref is turned on, the bias power terminal Iref outputs the first current. Therefore, when the second end of the first bias transistor M1 is not connected to the power supply terminal Vbatt (i.e., the second end of the first bias transistor M1 is suspended or grounded), the first current output by the bias power supply terminal Iref is not too early increased compared with the first current output by the second end of the first bias transistor M1, which is connected to the power supply terminal Vbatt, bias power supply terminal Iref and the first current output by the bias power supply terminal Iref when the bias diode is connected, so that the phenomenon of gain expansion of the power amplifier is avoided when the power amplifier is not close to the saturation state, the gain flatness of the power amplifier can be improved, and the linearity of the circuit in which the power amplifier is positioned is guaranteed.
In this example, when the power amplifier works in the unsaturated region, that is, when the output power Pout of the power amplifier reaches the saturated state, the first bias current output by the bias diode is adopted, and the magnitude of the first bias current output by the first bias transistor M1 with the second end suspended or grounded is basically the same; when the output power Pout of the power amplifier does not reach a saturated state, the first bias current output by the bias diode is different from the first bias current output by the first bias transistor M1 with the second end floating or grounded, the first bias current output by the bias diode is larger than the first bias current output by the first bias transistor M1 with the second end floating or grounded, so that the current supplied to the input end of the first amplifying transistor Q1 is increased in advance, the AMAM and/or AMPM of the power amplifier are increased, and the linearity of the circuit where the power amplifier is located is further affected, therefore, the first bias circuit 1 formed by the first bias transistor M1 with the second end floating or grounded is adopted, and the first bias current output by the first amplifying transistor Q1 is more accurate, so that the linearity of the circuit where the power amplifier is located is adjusted more sensitively.
In an embodiment, the power amplifier further comprises a switching circuit 2, a first terminal of the switching circuit 2 is connected to the second terminal of the first bias transistor M1, a second terminal of the switching circuit 2 is suspended or grounded, and a third terminal of the switching circuit 2 is connected to the power supply terminal Vbatt.
As an example, as shown in fig. 3 and 4, the power amplifier further includes a switching circuit 2, where a first end of the switching circuit 2 is connected to the second end of the first bias transistor M1, a second end of the switching circuit 2 is suspended or grounded, and a third end of the switching circuit 2 is connected to the power supply terminal Vbatt, so that the first end of the switching circuit 2 is connected to the second end or the third end of the switching circuit 2 according to different requirements of the power amplifier. In this example, the first bias current output from the third terminal of the first bias transistor M1 may affect not only the linearity but also the output power of the power amplifier. For example, when the power amplifier is required to exhibit better linearity, the first terminal of the switch circuit 2 may be controlled to be connected to the second terminal of the switch circuit 2, so that the second terminal of the first bias transistor M1 is suspended or grounded, and at this time, the first bias current provided by the first bias transistor M1 to the first amplifying transistor Q1 is smaller, so that the power amplifier has better linearity. For another example, when the power amplifier needs to have a larger output power without better linearity, the first terminal of the switch circuit 2 may be controlled to be connected to the third terminal of the switch circuit 2, so that the second terminal of the first bias transistor M1 is connected to the power supply terminal Vbatt, and the power supply terminal Vbatt supplies power to the first bias transistor M1, so that the first bias transistor M1 outputs a larger first bias current, and the output power of the power amplifier is further improved.
In an embodiment, the switching circuit 2 is configured to switch the first terminal of the switching circuit 2 to be connected to the second terminal or the third terminal of the switching circuit 2, depending on the operation mode of the power amplifier.
As an example, different requirements of the power amplifier are related to the operation modes of the power amplifier, that is, the power amplifier is required to exhibit different performances due to the different operation modes of the power amplifier. For example, in a certain working mode, the power amplifier needs to have better linearity, at this time, the first end of the switchable switching circuit 2 is connected to the second end of the switching circuit 2, so that the second end of the first bias transistor M1 is suspended or grounded, and the first bias current provided by the first bias transistor M1 to the first amplifying transistor Q1 is smaller, so as to ensure the linearity of the circuit in which the power amplifier is located; in another operation mode, the power amplifier needs to have a larger output power without better linearity, and at this time, the first end of the switchable switching circuit 2 is connected to the third end of the switching circuit 2, so that the second end of the first bias transistor M1 is connected to the power supply terminal Vbatt, and the power supply terminal Vbatt supplies power to the first bias transistor M1, so that the first bias transistor M1 outputs a larger first bias current, and the output power of the power amplifier is further improved. In this example, the requirement of the working mode of the power amplifier is met, and the first end of the switching circuit 2 is connected with the second end or the third end of the switching circuit, so as to meet different requirements of the circuit of the power amplifier with better linearity or larger output power.
In an embodiment, the switching circuit 2 is configured to control the first terminal of the switching circuit 2 to be connected to the second terminal of the switching circuit 2 when the power mode of the power amplifier is the first power mode; when the power mode of the power amplifier is a second power mode, the second terminal of the control switch circuit 2 is connected to the third terminal of the switch circuit 2, wherein the second power mode is larger than the first power mode.
As an example, the operation mode of the power amplifier may be determined according to the output power Pout of the power amplifier, specifically, when the output power Pout of the power amplifier is greater than a first threshold value, the power mode of the power amplifier may be determined to be the first power mode; when the output power Pout of the power amplifier is not greater than the first threshold, the power mode of the power amplifier may be determined to be the second power mode.
In this example, when the power mode of the power amplifier is the first power mode, the power amplifier needs to have better linearity, and at this time, the first end of the switchable switch circuit 2 is connected to the second end of the switch circuit 2, so that the second end of the first bias transistor M1 is suspended or grounded, so as to ensure the linearity of the circuit in which the power amplifier is located. When the power mode of the power amplifier is the second power mode, the power amplifier is required to have larger output power without better linearity, and at this time, the first terminal of the switchable switching circuit 2 is connected to the third terminal of the switching circuit 2, so that the second terminal of the first bias transistor M1 is connected to the power supply terminal Vbatt. In this example, according to whether the power mode of the power amplifier is the first power mode or the second power mode, the first end of the switching circuit 2 is connected to the second end or the third end of the switching circuit 2, so that the power amplifier has better linearity or larger output power, so as to meet the requirements of different power modes, and ensure the overall performance of the circuit in which the power amplifier is located.
In an embodiment, the switching circuit 2 is configured to control the first end of the switching circuit 2 to be connected to the second end of the switching circuit 2 when the operating frequency band of the power amplifier is the first frequency band; when the working frequency band of the power amplifier is a second frequency band, the second end of the control switch circuit 2 is connected with the third end of the switch circuit 2, wherein the second frequency band is larger than the first frequency band.
The first frequency band and the second frequency band refer to two working frequency bands in which the power amplifier can work normally. The first frequency band refers to a smaller frequency band of two working frequency bands in which the power amplifier can work normally. The second frequency band refers to a larger frequency band of two operating frequency bands in which the power amplifier can normally operate.
As an example, since the power amplifier operates in different operating frequency bands, the operating mode of the power amplifier may be determined according to the operating frequency band in which the power amplifier is located. When the working frequency band of the power amplifier is the first frequency band, that is, when the power amplifier is in a smaller frequency band of the two working frequency bands, the power amplifier needs to be ensured to have better linearity, at this time, the first end of the switchable switching circuit 2 is connected with the second end of the switching circuit 2, so that the second end of the first bias transistor M1 is suspended or grounded, and the linearity of the circuit where the power amplifier is located is ensured. When the working frequency band of the power amplifier is the second frequency band, that is, when the power amplifier is in a larger frequency band of the two working frequency bands, the power amplifier needs to be ensured to have larger output power, and the first end of the switching circuit 2 is connected with the third end of the switching circuit 2, so that the second end of the first bias transistor M1 is connected with the power supply end Vbatt, and the power amplifier is ensured to have larger output power. In this example, according to whether the working frequency band of the power amplifier is the first frequency band or the second frequency band, the first end of the switching circuit 2 is respectively connected with the second end or the third end of the switching circuit 2, so that the power amplifier has better linearity or larger output power, so as to meet the requirements of different working frequency bands, and ensure the overall performance of the circuit in which the power amplifier is located.
In one embodiment, the switch circuit 2 includes a single pole double throw switch, the stationary terminal of the single pole double throw switch is connected to the second terminal of the first bias transistor M1, the first terminal of the single pole double throw switch is suspended or grounded, and the second terminal of the single pole double throw switch is connected to the power supply terminal Vbatt.
As an example, the switch circuit 2 may include a single-pole double-throw switch, where the stationary end of the single-pole double-throw switch is connected to the second end of the first bias transistor M1, and the first movable end of the single-pole double-throw switch is suspended or grounded, and the second movable end of the single-pole double-throw switch is connected to the power supply end Vbatt, so that the switching between one stationary end and two movable ends can be achieved through one single-pole double-throw switch, which is simple in structure and convenient to control. In this example, when the power amplifier is required to exhibit better linearity, the fixed end of the single-pole double-throw switch is controlled to be connected with the first movable end of the single-pole double-throw switch, so that the second end of the first bias transistor M1 is suspended or grounded; when the power amplifier is required to have larger output power and better linearity is not required, the fixed end of the single-pole double-throw switch can be controlled to be connected with the second movable end of the single-pole double-throw switch, so that the second end of the first bias transistor M1 is connected with the power supply end Vbatt.
In an embodiment, the first bias transistor M1 is a bias MOS transistor, the gate of the bias MOS transistor is a first end of the first bias transistor M1, the drain of the bias MOS transistor is a second end of the first bias transistor M1, and the source of the bias MOS transistor is a third end of the first bias transistor M1;
alternatively, the first bias transistor M1 is a bias BJT transistor, the substrate of the bias BJT transistor is the first end of the first bias transistor M1, the collector of the bias BJT transistor is the second end of the first bias transistor M1, and the emitter of the bias BJT transistor is the third end of the first bias transistor M1.
As an example, the first bias transistor M1 may be a bias MOS transistor. The grid electrode of the bias MOS transistor is a first end of the first bias transistor M1, the drain electrode of the bias MOS transistor is a second end of the first bias transistor M1, and the source electrode of the bias MOS transistor is a third end of the first bias transistor M1. That is, the gate of the bias MOS transistor is connected to the bias power terminal Iref to receive the first current outputted from the bias power terminal Iref; the drain electrode of the bias MOS tube is suspended or grounded; the source of the bias MOS transistor is coupled to the input terminal of the first amplifying transistor Q1 to output a first bias current to the input terminal of the first amplifying transistor Q1. In this example, the gate of the bias MOS transistor processes the first current output by the bias power supply terminal Iref to form a first bias current, and the first bias current is coupled to the input terminal of the first amplifying transistor Q1 through the source thereof, so that the normal operation of the first amplifying transistor Q1 can be ensured based on the first bias current; because the source electrode of the bias MOS tube is suspended or grounded, the bias MOS tube does not receive the voltage input by the source electrode, so that the magnitude of the first bias current output by the first bias transistor M1 can be adjusted more sensitively, the accuracy of the first bias current output by the bias MOS tube is ensured, and the power amplifier can exhibit better linearity.
As an example, the first bias transistor M1 may be a bias BJT transistor. The substrate of the bias BJT tube is a first end of a first bias transistor M1, the collector of the bias BJT tube is a second end of the first bias transistor M1, the emitter of the bias BJT tube is a third end of the first bias transistor M1, that is, the substrate of the bias BJT tube is connected with a bias power end Iref to receive a first current output by the bias power end Iref; the collector electrode of the bias BJT tube is suspended or grounded; the emitter of the bias BJT is coupled to the input of the first amplifying transistor Q1 to output a first bias current to the input of the first amplifying transistor Q1. In this example, the substrate of the bias BJT processes the first current output by the bias power supply terminal Iref to form a first bias current, and couples the first bias current to the input terminal of the first amplifying transistor Q1 through the emitter thereof, so that the normal operation of the first amplifying transistor Q1 can be ensured based on the first bias current; because the emitter of the bias BJT tube is suspended or grounded, the bias BJT tube does not receive the voltage input by the emitter, the linearity of a circuit where the power amplifier is positioned is further improved, the accuracy of the first bias current output by the bias BJT tube is ensured, and the power amplifier can show better linearity.
In an embodiment, as shown in fig. 5, the power amplifier further includes a second bias circuit 2, and the second bias circuit 2 includes a second bias transistor M2; the first end of the second bias transistor M2 is connected with the bias power supply end Vbatt to receive the second current output by the bias power supply end Vbatt; the second end of the second bias transistor M2 is suspended or grounded; the third terminal of the second bias transistor M2 is coupled to the input terminal of the first amplifying transistor Q1 to output the second bias current to the input terminal of the first amplifying transistor Q1, thereby improving the durability (ruggeddess) of the power amplifier.
The second bias circuit 2 is the same as the circuit structure of the first bias circuit 1, and is not described herein in detail to avoid repetition, and the circuit structure of the second bias circuit 2 is the same as the circuit structure of the first bias circuit 1.
As an example, the second bias circuit 2 is a primary bias circuit, and the first bias circuit 1 is a secondary bias circuit, where the third terminal of the second bias transistor M2 is coupled to the input terminal of the first amplifying transistor Q1 and configured to: when the output power of the power amplifier is smaller than the first power threshold, the second end of the second bias transistor M2 outputs a second bias current to the input end of the first amplifying transistor Q1; when the output power of the power amplifier is not less than the first power threshold, outputting a second bias current to the input end of the first amplifying transistor Q1, and enabling the first bias transistor to output a first bias current to the input end of the first amplifying transistor Q1, so as to improve the durability (ruggeddess) of the power amplifier, and further ensure the overall performance of the whole power amplifier. The first power threshold is a preset power threshold.
It should be further noted that, the mapping curve between the output power Pout of the power amplifier shown in fig. 7 and the corresponding AMAM is specifically a curve in which the input terminal of the first amplifying transistor Q1 is coupled with the second bias circuit 2 and the first bias circuit 1. Fig. 8 is a mapping curve between the output power Pout of the power amplifier and its corresponding AMPM, specifically, a curve in which the input terminal of the first amplifying transistor Q1 is coupled to the second bias circuit 2 and the first bias circuit 1. Fig. 9 shows the magnitude of the first bias current of the first bias transistor M1 in the first bias circuit 1 (sub bias circuit). Fig. 10 shows the magnitude of the first current output from the bias power supply terminal Vbatt in the first bias circuit 1 (secondary bias circuit).
In an embodiment, as shown in fig. 6, the power amplifier further includes a second amplifying transistor Q2 and a third bias circuit 3, an input terminal of the second amplifying transistor Q2 is coupled to an output terminal of the first amplifying transistor Q1; the third bias circuit 3 includes a third bias transistor M3; the first end of the third bias transistor M3 is connected to the bias power supply terminal Vbatt, so as to receive the third current output by the bias power supply terminal Vbatt; the second end of the third bias transistor M3 is suspended or grounded; the third terminal of the third bias transistor M3 is coupled to the input terminal of the second amplifying transistor Q2 to output a third bias current to the input terminal of the second amplifying transistor Q2, so that it can be ensured that the power supply current does not expand when the output power of the second amplifying transistor Q2 approaches or reaches the saturated power, and the durability (ruggeddess) of the power amplifier is further improved.
As an example, the power amplifier further comprises a second amplifying transistor Q2 and a third biasing circuit 3, the input of the second amplifying transistor Q2 being coupled to the output of the first amplifying transistor Q1. The third bias circuit 3 is a bias circuit coupled to the input terminal of the second amplifying transistor Q2, and the circuit structure thereof is the same as that of the first bias circuit 1, and is not repeated here.
In this example, the power amplifier includes two stages of amplifying transistors, i.e., a first amplifying transistor Q1 and a second amplifying transistor Q2, that is, the first amplifying transistor Q1 is a first stage power amplifying transistor and the second amplifying transistor Q2 is a second stage power amplifying transistor. The input end of the first amplifying transistor Q1 is coupled with the second bias circuit 2 (i.e. the primary bias circuit) and the first bias circuit 1 (i.e. the secondary bias circuit), while the input end of the second amplifying transistor Q2 is coupled with the third bias circuit 3 (i.e. the primary bias circuit), in order to verify that the second end of the bias transistor is suspended or grounded, when the second end of the bias transistor is connected with the power supply end Vbatt, the power supply current of the power supply end VCC of the amplifying transistor in the power amplifier is related to the input signal (Pin) thereof, and the simulation test can be performed under the same condition, and the simulation test results are shown in fig. 11 and 12. Fig. 11 is a graph showing a change of a supply current outputted from a supply terminal VCC1 of the first amplifying transistor Q1 with an input signal Pin thereof, fig. 12 is a graph showing a change of a supply current outputted from a supply terminal VCC2 of the second amplifying transistor Q2 with an input signal Pin thereof, a curve 1 is a curve in which a second terminal of the biasing transistor is suspended or grounded, and a curve 2 is a curve in which a second terminal of the biasing transistor is connected to a supply terminal Vbatt.
As can be seen from fig. 11 and 12, when the second bias circuit 2 (i.e., the primary bias circuit) and the first bias circuit 1 (i.e., the secondary bias circuit) are coupled to the input terminal of the first amplifying transistor Q1, and when the second terminals of the bias transistors in the two bias circuits are suspended or grounded, the supply current outputted from the supply terminal VCC1 of the first amplifying transistor Q1 increases with the increase of the input signal Pin, and since the supply current of the first amplifying transistor Q1 itself is smaller, the supply current outputted from the supply terminal VCC1 of the first amplifying transistor Q1 does not destroy the first amplifying transistor Q1 even if the supply current increases with the increase of the input signal Pin. As can be seen from fig. 12, the input terminal of the second amplifying transistor Q2 is coupled with the third bias circuit 3 (i.e., the main bias circuit), and when the second terminal of the third bias transistor M3 in the third bias circuit 3 is connected to the power supply terminal Vbatt, the power supply current outputted from the power supply terminal VCC2 of the second amplifying transistor Q2 will rise all the time with the increase of the input signal Pin thereof, and the second amplifying transistor Q2 is easy to burn out due to the larger power supply current of the second amplifying transistor Q2 itself. When the second end of the third bias transistor M3 in the third bias circuit 3 is suspended or grounded, the supply current output by the supply end VCC2 of the second amplifying transistor Q2 does not rise along with the increase of the input signal Pin thereof, so that the second amplifying transistor Q2 is not easy to burn out, and therefore, when the output power of the second amplifying transistor Q2 approaches or reaches the saturated power, the expansion phenomenon of the supply current can be avoided, and the durability (ruggeddess) of the whole power amplifier is further improved.
The embodiment of the invention provides a radio frequency front-end circuit, which comprises the power amplifier.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.
Claims (16)
1. A power amplifier comprising a first amplifying transistor and a first bias circuit;
the first bias circuit includes a first bias transistor;
the first end of the first bias transistor is connected with a bias power supply end so as to receive a first current output by the bias power supply end;
the second end of the first bias transistor is suspended or grounded;
the third terminal of the first bias transistor is coupled to the input terminal of the first amplifying transistor to output a first bias current to the input terminal of the first amplifying transistor.
2. The power amplifier of claim 1, wherein the first bias circuit further comprises a first bias resistor, a third terminal of the first bias transistor coupled to an input terminal of the first amplifying transistor through the first bias resistor.
3. The power amplifier of claim 1, wherein a first bias current output by a third terminal of the first bias transistor is configured to be related to a first current output by the bias supply terminal and an output power of the power amplifier.
4. The power amplifier of claim 1, wherein the first bias circuit is configured to improve gain flatness of the first amplifying transistor.
5. The power amplifier of claim 3 wherein the first bias current output from the third terminal of the first bias transistor is [0.05ma,0.1ma ] when the first current output from the bias power supply terminal is [0.01ma,0.5ma ], and the output power of the power amplifier reaches a saturated state.
6. The power amplifier of claim 3 wherein the first bias current output from the third terminal of the first bias transistor is [ 0.04 ma,0.4ma ] when the first current output from the bias power supply terminal is [0.01ma,0.5ma ], the power back-off before the output power of the power amplifier reaches saturation [4dB-6dB ].
7. The power amplifier of claim 5, wherein the first bias current output from the third terminal of the first bias transistor is [0.001mA,0.1mA ] when the first current output from the bias power supply terminal is [0.01mA,0.5mA ], the power back-off before the output power of the power amplifier reaches the saturation state [4dB-6dB ].
8. The power amplifier of claim 1, further comprising a switching circuit, a first terminal of the switching circuit being coupled to the second terminal of the first bias transistor, the second terminal of the switching circuit being floating or grounded, a third terminal of the switching circuit being coupled to a power supply terminal.
9. The power amplifier of claim 7, wherein the switching circuit is configured to switch a first terminal of the switching circuit to connect with a second terminal or a third terminal of the switching circuit depending on an operating mode of the power amplifier.
10. The power amplifier of claim 8, wherein the switching circuit is configured to control a first terminal of the switching circuit to be connected to a second terminal of the switching circuit when a power mode of the power amplifier is a first power mode; and when the power mode of the power amplifier is a second power mode, controlling the second end of the switching circuit to be connected with the third end of the switching circuit, wherein the second power mode is larger than the first power mode.
11. The power amplifier of claim 9, wherein the switching circuit is configured to control a first terminal of the switching circuit to be connected to a second terminal of the switching circuit when an operating frequency band of the power amplifier is a first frequency band; and when the working frequency band of the power amplifier is a second frequency band, controlling the second end of the switching circuit to be connected with the third end of the switching circuit, wherein the second frequency band is larger than the first frequency band.
12. The power amplifier of claim 7, wherein the switching circuit comprises a single pole double throw switch having a stationary terminal connected to the second terminal of the first bias transistor, a first terminal of the single pole double throw switch being suspended or grounded, and a second terminal of the single pole double throw switch being connected to the power supply terminal.
13. The power amplifier of claim 1, wherein the first bias transistor is a bias MOS transistor, a gate of the bias MOS transistor is a first terminal of the first bias transistor, a drain of the bias MOS transistor is a second terminal of the first bias transistor, and a source of the bias MOS transistor is a third terminal of the first bias transistor;
Or the first bias transistor is a bias BJT transistor, the substrate of the bias BJT transistor is a first end of the first bias transistor, the collector electrode of the bias BJT transistor is a second end of the first bias transistor, and the emitter of the bias BJT transistor is a third end of the first bias transistor.
14. The power amplifier of any of claims 1-13, further comprising a second bias circuit comprising a second bias transistor;
the first end of the second bias transistor is connected with a bias power supply end so as to receive a second current output by the bias power supply end;
the second end of the second bias transistor is suspended or grounded;
the third terminal of the second bias transistor is coupled to the input terminal of the first amplifying transistor to output a second bias current to the input terminal of the first amplifying transistor.
15. The power amplifier of claim 14, further comprising a second amplifying transistor and a third bias circuit,
an input of the second amplifying transistor is coupled to an output of the first amplifying transistor;
The third bias circuit includes a third bias transistor;
the first end of the third bias transistor is connected with a bias power supply end so as to receive third current output by the bias power supply end;
the second end of the third bias transistor is suspended or grounded;
a third terminal of the third bias transistor is coupled to the input terminal of the second amplifying transistor to output a third bias current to the input terminal of the second amplifying transistor.
16. A radio frequency front-end circuit comprising the power amplifier of any of claims 1-15.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211726539.6A CN116131774A (en) | 2022-12-30 | 2022-12-30 | Power amplifier and radio frequency front-end circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211726539.6A CN116131774A (en) | 2022-12-30 | 2022-12-30 | Power amplifier and radio frequency front-end circuit |
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| CN116131774A true CN116131774A (en) | 2023-05-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116346107A (en) * | 2023-05-31 | 2023-06-27 | 广东工业大学 | HBT-based radio frequency switch |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040095192A1 (en) * | 2002-11-14 | 2004-05-20 | Enver Krvavac | Radio frequency power amplifier adaptive bias control circuit |
| US20190036488A1 (en) * | 2016-03-30 | 2019-01-31 | Murata Manufacturing Co., Ltd. | Radio-frequency signal amplifier circuit, power amplifier module, front-end circuit, and communication device |
| CN113395045A (en) * | 2021-05-31 | 2021-09-14 | 锐石创芯（深圳）科技有限公司 | Doherty power amplifier, system and control method |
| CN114094950A (en) * | 2021-09-26 | 2022-02-25 | 深圳飞骧科技股份有限公司 | Radio frequency power amplifier |
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2022
- 2022-12-30 CN CN202211726539.6A patent/CN116131774A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040095192A1 (en) * | 2002-11-14 | 2004-05-20 | Enver Krvavac | Radio frequency power amplifier adaptive bias control circuit |
| US20190036488A1 (en) * | 2016-03-30 | 2019-01-31 | Murata Manufacturing Co., Ltd. | Radio-frequency signal amplifier circuit, power amplifier module, front-end circuit, and communication device |
| CN113395045A (en) * | 2021-05-31 | 2021-09-14 | 锐石创芯（深圳）科技有限公司 | Doherty power amplifier, system and control method |
| CN114094950A (en) * | 2021-09-26 | 2022-02-25 | 深圳飞骧科技股份有限公司 | Radio frequency power amplifier |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116346107A (en) * | 2023-05-31 | 2023-06-27 | 广东工业大学 | HBT-based radio frequency switch |
| CN116346107B (en) * | 2023-05-31 | 2023-08-11 | 广东工业大学 | HBT-based radio frequency switch |
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