JP2008125044A - Amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplifier which attains high gain by preventing a gain from being deteriorated by the distribution loss of an input distributor in a high-efficiency Doherty amplifier, and is capable of reducing high-order distortion by suppressing an increase in the high-order distortion. <P>SOLUTION: Outputs from a carrier amplifier circuit 4 which operates in a class-AB and a peak amplifier circuit 5 which operates in a class-B or C class are combined at a node 62 and output. The length of a transmission line 33 is adjusted for a signal distributed by a distributor 2, a reflection coefficient in low input is changed, impedance conversion is applied to a signal from the carrier amplifier circuit 4 by an impedance converter 64 and regarding a signal from the peak amplifier circuit 5, impedance in low input is made large so as not to cause a loss on a transmission line 65. During the low input, input impedance at a side of the peak amplifier circuit 5 from the distributor 2 is made closer to infinity, so that the amplifier increases a gain during low input. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an amplifier that amplifies a radio frequency signal, and more particularly to an amplifier that achieves a high gain and reduces high-order distortion.

  Conventionally, when amplifying a radio frequency signal such as a CDMA (Code Division Multiple Access) signal or a multicarrier signal, distortion compensation means is added to the common amplifier, and the operation range of the common amplifier is saturated. Low power consumption is achieved by extending it to the vicinity.

  Examples of distortion compensation means include feedforward distortion compensation and predistortion distortion compensation. However, distortion compensation alone is approaching the limit of reducing power consumption. Therefore, in recent years, Doherty amplifiers have attracted attention as highly efficient amplifiers.

A conventional Doherty amplifier will be described with reference to FIG. FIG. 8 is a configuration block diagram of a conventional Doherty amplifier.
As shown in FIG. 8, the conventional Doherty amplifier includes an input terminal 1, a distributor 2, a phase shifter 3, a carrier amplifier circuit 4, a peak amplifier circuit 5, a Doherty synthesizer 6, and a λ / 4 transformer. A device 7, an output terminal 8, and an output load 9 are provided.

The carrier amplifier circuit 4 includes an input matching circuit 41, an amplification element 42, and an output matching circuit 43.
The peak amplifier circuit 5 includes an input matching circuit 51, an amplification element 52, and an output matching circuit 53.
The Doherty synthesizer 6 includes a λ / 4 transformer 61 and a node (synthesis point) 62.

Next, the operation of the conventional Doherty amplifier will be described.
A signal input from the input terminal 1 is distributed by the distributor 2 and output to the carrier amplifier circuit 4 and the phase shifter 3.
One signal distributed by the distributor 2 is input to the carrier amplifier circuit 4, matched with the input side of the amplifier element 42 by the input matching circuit 41, amplified by the amplifier element 42, and output matching circuit At 43, the output is matched with the output side of the amplifying element 42 and output to the Doherty synthesizer 6.

The other signal distributed by the distributor 2 is input to the phase shifter 3, the phase is delayed by 90 degrees by the phase shifter 3, and input to the peak amplification circuit 5.
The signal input to the peak amplifier circuit 5 is matched with the input side of the amplification element 52 by the input matching circuit 51, the input signal is amplified by the amplification element 52, and the output side of the amplification element 52 is output by the output matching circuit 53. Matching is performed and output to the Doherty combining unit 6.

  In the Doherty combining unit 6, the output from the carrier amplifier 4 is impedance-converted by the λ / 4 transformer 61, and the output from the λ / 4 transformer 61 and the output from the peak amplifier 5 are combined at the node 62, and λ / 4 It is output to the transformer 7.

In the λ / 4 transformer 7, impedance conversion is performed to match the load Z ₀ of the output load 9. The output side of the λ / 4 transformer 7 is connected to an output load 9 via an output terminal 8.

  The carrier amplifier 4 and the peak amplifier 5 are different in that the amplifying element 42 is biased to class AB and the amplifying element 52 is biased to class B or class C. Therefore, even when a signal is input to the amplifier, the amplification element 42 operates alone until the amplification element 52 operates, and the amplification element 42 enters the saturation region. That is, when the linearity of the amplifying element 42 starts to break, the amplifying element 52 starts to operate, the output of the amplifying element 52 is supplied to the output load 9, and the output load 9 is driven together with the amplifying element 42.

At this time, as will be described later, the load line of the output synthesis circuit 43 moves from a high resistance to a low resistance. However, since the amplification element 42 is in the saturation region, efficiency is high.
When the input from the input terminal 1 increases and further amplification is performed, the amplifying element 52 starts to be saturated. However, since both the amplifying element 42 and the amplifying element 52 are saturated, the efficiency is also good at this time.

  Next, theoretical collector efficiency and drain efficiency in a conventional Doherty amplifier will be described with reference to FIG. FIG. 9 is a diagram illustrating theoretical collector efficiency and drain efficiency according to a conventional Doherty amplifier.

  Collector efficiency means the ratio of the radio frequency output power that can be extracted from the collector to the product of the voltage (DC) of the power supply applied to the collector and the current (DC) supplied from the power supply. It has the same meaning.

  In FIG. 9, the horizontal axis is back-off (the difference between the maximum output amplitude level and the output saturation power level), and the input level to the minimum input terminal 1 at which both the amplifying elements 42 and 52 are saturated, In other words, the compression point is 0 dB, and this is a numerical value indicating how much the input level has a margin with respect to the compression point.

  The compression point is a point where the input level of the circuit increases, output saturation occurs, and the output level does not increase. This is the point where the 1 dB response has dropped from the ideal input / output straight line.

In FIG. 9, the dotted line indicates the efficiency of a general class B amplifier, and the solid line indicates the efficiency of the Doherty amplifier in a simple model.
When the input level is in the section A, only the carrier amplifier circuit 4 basically operates. The carrier amplifier circuit 4 starts to saturate near the backoff of 6 dB, and the efficiency reaches near the maximum efficiency of the class B amplifier. Assuming that the maximum output of the Doherty amplifier is P ₀ , the output of the carrier amplifier circuit 4 at this time is about P _0/4 .

In section B where the backoff is 6 dB or less, as the input level increases, the output of the carrier amplifier circuit 4 increases from about P _0/4 to P _0/2 , and the output of the peak amplifier circuit 5 is almost 0 (zero). Increases from P to P _0/2 .

  At this time, the sum of the output powers of the carrier amplifier circuit 4 and the peak amplifier circuit 5 is proportional to the input power to the input terminal 1 with the same proportionality constant as in the section A. When the peak amplifying circuit 5 starts to operate, the efficiency once decreases, but reaches a peak again at the compression point at which the peak amplifying circuit 5 also begins to saturate. At the compression point, the outputs of the carrier amplifier circuit 4 and the peak amplifier circuit 5 are equal.

  In general, a CDMA signal and a multicarrier signal have a high peak factor, that is, a ratio of peak power to average power. However, in a normal amplifier, a point corresponding to the peak factor of 7 to 12 dB is lowered from the compression point. Is the operating point.

The impedance of each part in FIG. 8 will be described.
Since the output load Z ₀ is defined to be constant, this is the starting point. The impedance Z ₇ when the λ / 4 transformer ₇ is viewed from the node 62 is Z ₂ , where the characteristic impedance of the λ / 4 transformer 7 is Z ₂ .
Z ₇ = Z ₂ ² / Z ₀
It becomes.

The impedance Z _{4 when the} λ / 4 transformer 61 is viewed from the output matching circuit 43 is obtained in the same manner as described above because the output impedance of the output adjustment circuit 53 is substantially infinite in the A region.
In the C region, since the load is equally shared, the load impedance of the λ / 4 transformer 61 (the contribution of the carrier amplifier circuit 4 at the node 62) and the load impedance of the output matching circuit 53 are 2Z ₇ respectively. Impedance Z ₄ and impedance Z _{5 when the} node 62 is viewed from the output matching circuit 53 are obtained by the following equation.

However, the impedance Z ₁ is the characteristic impedance of the λ / 4 transformer 61. Impedances Z ₄ and Z ₅ transition in the B region between values in the A region and values in the C region, respectively.

When the Doherty amplifier is applied to a high frequency region, the following description is easier to understand than the above description.
That is, the impedance Z ₄ is halved when the input signal level is high (C region) with respect to the impedance value when the input signal level is low (A region), that is, the load fluctuates twice.

For example, if Z ₇ = 25Ω and Z ₁ = 50Ω, Z ₄ varies between 100 and 50Ω. Accordingly, the load impedance of the amplifying element 42 also varies. This is generally called load modulation.

In the prior art shown in FIG. 8, a distributor is used on the input side and basically 3 dB is lost. Therefore, although the load modulation increases, the gain decreases.
Even if the collector (drain) efficiency increases due to the gain reduction, the added efficiency (power added efficiency) decreases.
The added efficiency is obtained by the following formula.
(Output RF power−input RF power) / DC input power = output RF power (1-1 / G) / DC input power

  As an example, when the collector (drain) efficiency is 35%, the additional efficiency with a gain of 10 dB is 31.5%, and when the collector (drain) efficiency is 35% and the gain is 13 dB, the additional efficiency is 33.25%. Improving the gain is important.

  As for the distortion, the carrier amplifier may be used near saturation, and has higher-order distortion than the conventional AB class amplifier.

As a prior art, there is "Amplifier" in Japanese Patent Laid-Open No. 2006-157900 (Patent Document 1).
In addition, as other prior art, Japanese Patent Application Laid-Open No. 2005-173231 “Signal Amplifier Using Doherty Amplifier” (Patent Document 2), Japanese Patent Application Laid-Open No. 2004-096729 “Doherty Amplifier” (Patent Document 3), Japanese Patent Laid-Open No. 2006-093773 “High Frequency Power Amplifying Module” (Patent Document 4) is available.
US2006 / 0028297 POWER DIVIDER AND COMBINER IN COMMUNICATION SYSTEM (Patent Document 5) describes a T-branch with low loss.
Further, as related documents, there are the following patent documents 6 and 7 and non-patent documents 1 to 6.

JP 2006-157900 A JP 2005-173231 A JP 2004-096729 A JP 2006-093773 A US2006 / 0028297 JP-T-2006-525749 JP 2006-339981 A Younkyu Chung, Jinseong Jeong, Yuanxun Wang, Dal Ahn, Tatsuo Itoh Power Level-Dependent Dual-Operating Mode LDMOS Power Amplifier for CDMA Wireless Base-Station Applications IEEE Transaction on Microwave Theory and Techniques, vol. 53, No.2, February 2005 pp.739-745 Simon M. Wood, Raymond S. Pengelly Design of a High Power Doherty Amplifier Using a New Large Signal LDMOS FET Model, 2004 IEEE, the Wireless and Microwave Technology Conference proceedings Nam-Sik Ryu, Su-tae Kim, Su-jin Seo, Yong-Chae Jeong HBT Doherty Amplifier Using Ballast Resistor Control and Arbitrary Termination Impedance Power Divider APMC 2005 Proceedings Younkyu Chung, Jinseong Jeong, Yuanxun Wang, Dal Ahn, Tatsuo Itoh Efficiency-Enhancing Technique: LDMOS Power Amplifier Using Dual-Mode Operation Design Approach IEEE MTT-S International June 2004 Vol.2 pp.859-862 Pyonho Hong, Hoe-sung Yang, Youngsang Jeon A Novel Envelope Following Power Amplifier with Power Tracking Doherty Operation, http://www.samsung.com/AboutSAMSUNG/ELECTRONICSGLOBAL/SocialCommitment/HumantechThesis/WinningPapers/downloads/work10/h21.pdf [ Search on June 30, 2006] Bumman Kim, Youngoo Yang, Jaehyok Yi, Joongjin Nam, Young Yun Woo, Jeong Hyeon Cha Efficiency Enhancement of Linear Power Amplifier Using Load Modulation Technique, 2001, Int.Nicrowave and Optical Technology Symp.Dig, pp.505-508

  However, Patent Document 1 is a very effective method for improving drain efficiency. However, since the input is distributed to the carrier amplifier circuit and the peak amplifier circuit, the distribution loss is basically 3 dB, and the gain improvement by load modulation is improved. Even if there was, there was a problem that it could not be improved more than 3 dB.

In Patent Documents 2 and 3, the bias of the peaking amplifier of the Doherty amplifier is controlled, the amplification element is turned off in the low power mode, and the class AB operation is performed in the high power mode.
However, in Patent Documents 2 and 3, in the off region where the peaking amplifier does not operate, a loss of 3 dB is generated by the splitter, and when the peaking amplifier becomes class AB when in the high power mode, there is no distribution loss. Since it becomes a composition method, it rises by 3 dB. Therefore, Patent Documents 2 and 3 have a problem that the AM-AM characteristic (amplitude vs. amplitude characteristic) is poor.

Note that Patent Document 4 merely shows a high-frequency power amplification module with improved isolation and good stability against changes in input impedance. This prior art uses a small output AMP or a large output AMP according to the input level, and has a problem of distribution loss.
Patent Document 5 only shows a T-branch with little loss.

  Patent Documents 6 and 7 describe that in the Doherty amplifier, the input is unequally distributed to the carrier amplifier circuit and the peak amplifier circuit, but the distribution ratio is not variable according to the input power.

Non-Patent Document 2 merely shows that a FET (Field Effect Transistor) model is applied to a Doherty amplifier as a CMC (Curtice Modelithics Cree) model.
In Non-Patent Document 3, low impedance matching is performed without matching with a 50 Ω load. To reduce the number of matching elements, the stabilization resistance is changed when the peak amplifier is operated to reduce loss and equivalent. Only a Doherty amplifier that increases the gain is shown.

Non-Patent Document 4 merely shows an LDMOS (Laterally Diffused Metal-Oxide-Semiconductor) power amplifier that controls input impedance matching with a switch. According to the prior art, the efficiency is increased to 1 PA at the low level and 4 PA at the high level according to the input level.
Non-Patent Document 6 shows that the Doherty line is 90 degrees (λ / 4) + offset line, that is, λ / 4 to infinity.

  The present invention has been made in view of the above circumstances, and prevents gain reduction due to distribution loss of an input distributor of a high-efficiency Doherty amplifier to achieve high gain and suppress increase in high-order distortion to reduce high-order distortion. An object of the present invention is to provide an amplifier that can be used.

  The present invention for solving the problems of the above-described conventional example is an amplifier in which an input signal is equally distributed or unevenly distributed, and an evenly distributed or less unevenly distributed signal is operated in class AB and amplified. A carrier amplifier circuit, a first transmission line that adjusts the reflection coefficient at the time of low input by adjusting the length of the line with respect to a signal that is equally distributed or highly unevenly distributed, and a first transmission line A peak amplifying circuit for operating and amplifying the signal in class B or C, an impedance converter for converting the impedance of the signal from the carrier amplifying circuit, and a second for reducing the influence of the peak amplifying circuit at low input A node for combining the transmission line, the terminal of the impedance converter and the terminal of the second transmission line to combine the outputs of the carrier amplifier and the peak amplifier, an output load connected to the node, the node and the output negative Provided between, and having a transformer for converting the output load impedance for the output from the node.

  The present invention relates to an amplifier in which an input signal is equally distributed or unevenly distributed, a carrier amplifier circuit that operates and amplifies an equally distributed or less unevenly distributed signal in class AB, and is equally distributed or largely unbalanced. The first transmission line that changes the reflection coefficient at the time of low input by adjusting the length of the line with respect to the equally distributed signal, and the signal from the first transmission line is operated in class B or class C. An amplifying peak amplifying circuit; an impedance converter for converting the impedance of the signal from the carrier amplifying circuit; a second transmission line for reducing the influence of the peak amplifying circuit when the input is low; and an end of the impedance converter; A node for combining the terminal ends of the second transmission line to combine the outputs of the carrier amplifier circuit and the peak amplifier circuit, an output load connected to the node, and an output from the node provided between the node and the output load; On the other hand, a transformer that converts the impedance into an output load, a branching device that branches the input signal, and a signal that is output from the branching device are detected and level-converted to bias the peak amplification circuit. And an adaptive bias circuit that outputs current, and the peak amplifier circuit is class C when the input signal is lower than the threshold value, and less idle current from class C when the input signal exceeds the threshold value. It is characterized by operating in the AB class with a large idle current after passing through the AB class.

  The present invention also provides a distributor that distributes an input signal to two ports, a carrier amplification circuit that operates and amplifies the distributed signal in class AB, and operates a distributed signal in class B or class C. A peak amplifying circuit that amplifies the signal, an impedance converter that converts the impedance of the signal from the carrier amplifying circuit, and a carrier amplifying circuit and a peak amplifying circuit by combining the terminal end of the impedance converter and the terminal amplifying circuit. And an output load connected to the node, and a transformer provided between the node and the output load for converting the impedance from the node into an output load. The distributor includes a first voltage variable resistor that connects the distribution destination ports alone, or the first voltage variable resistor and the distributed signal to the peak signal. A distributor including a second voltage variable resistor for connecting between a port output to the amplifier circuit and the ground, and provided in a preceding stage of the distributor and branching an input signal; A detector that detects the output signal and outputs an input power level, and controls and distributes the resistance values of the first voltage variable resistor and the second voltage variable resistor of the distributor according to the input power level. And a control unit that adjusts the ratio and restricts the input to the peak amplifier circuit when the input power level is low.

  According to the present invention, in the above amplifier, the control unit controls the bias voltage of the peak amplifier circuit according to the input power level so that the input signal is class C when the input signal is a low input equal to or lower than a threshold value. When the threshold value is exceeded, operation is performed from class C to class AB with a large idle current through class AB with a small idle current.

  According to the present invention, a distributor that distributes an input signal equally or unequally, a carrier amplifier circuit that operates and amplifies a signal that is equally distributed or lessly unequally distributed in class AB, and is equally distributed or largely unequal. A first transmission line that adjusts the reflection coefficient at the time of low input by adjusting the length of the line with respect to the distributed signal, and operates the signal from the first transmission line in class B or C At the time of low input when the peak amplifier circuit to be amplified does not operate, the gain at the time of low input is increased by bringing the input impedance from the distributor to the peak amplifier circuit side close to infinity, and the input level dependence of gain is monotonically increased There is an effect of reducing the secondary distortion.

  According to the present invention, a distributor that distributes an input signal equally or unequally, a carrier amplifier circuit that operates and amplifies a signal that is equally distributed or lessly unequally distributed in class AB, and is equally distributed or largely unequal. A first transmission line that adjusts the reflection coefficient at the time of low input by adjusting the length of the line with respect to the distributed signal, and a peak amplification circuit that amplifies the signal from the first transmission line, When the input signal is lower than the threshold value, it is class C, and when the input signal exceeds the threshold value, the amplifier is operated from class C to class AB with a small idle current and then a class AB with a large idle current. At low input when the circuit does not operate, the input impedance from the distributor to the peak amplifier circuit side is made close to infinity, thereby increasing the gain at low input and monotonizing the input level dependence of gain to reduce higher-order distortion. There is an effect that can be

  Further, according to the present invention, the distributor that distributes the input signal to the carrier amplifier circuit and the peak amplifier circuit includes the first voltage variable resistor that connects between the distribution destination ports, and the peak amplification of the distributed signal. A distributor having a second voltage variable resistor that connects between a port that outputs to the circuit and the ground, and the control unit includes a first voltage variable resistor of the distributor according to the input power level; The distribution ratio is adjusted by controlling the resistance value of the second voltage variable resistor. Since the amplifier limits the input to the peak amplifier circuit when the input power level is low, it is distributed to the carrier amplifier circuit 4 side. There are effects that the gain reduction can be prevented and the mutual interference between the carrier amplifier circuit and the peak amplifier circuit can be reduced.

  Further, according to the present invention, the control unit controls the bias voltage of the peak amplifier circuit according to the input power level, and when the input signal is a low input that is equal to or lower than the threshold value, the control unit class C, and the input signal is the threshold value. If the value exceeds the value, the amplifier is operated from class C through class AB with low idle current to class AB with high idle current, so the output of the Doherty amplifier when the input power level is high is brought close to the combined output of the class AB amplifier. And gain reduction can be prevented.

Embodiments of the present invention will be described with reference to the drawings.
An amplifier according to an embodiment of the present invention combines outputs from a carrier amplifier circuit operating in class AB and a peak amplifier circuit operating in class B or class C at a node, and is distributed by a distributor. The first transmission line is adjusted to change the reflection coefficient at the time of low input, the distribution loss is reduced, and the signal from the carrier amplifier circuit is impedance-converted by the impedance converter. The signal from the peak amplifier circuit is synthesized via the second transmission line, and at low input when the peak amplifier circuit does not operate, the input impedance on the side of the peak amplifier circuit from the distributor is made close to infinity. The higher order distortion can be reduced by increasing the gain and monotonizing the dependence of the gain on the input level.

  The amplifier according to the embodiment of the present invention combines the outputs from the carrier amplifier circuit operating in class AB and the peak amplifier circuit operating in class B or class C at the node, and is a distributor. For the distributed signal, the line length is adjusted in the first transmission line to change the reflection coefficient at the time of low input, reduce the distribution loss, and the signal from the carrier amplifier circuit is impedance converted by the impedance converter Then, the signal from the peak amplifier circuit is synthesized via the second transmission line, the input signal is branched by the branching device, the signal from the branching device is detected by the adaptive bias circuit, the level is converted, and the peak amplification is performed. Outputs as a bias voltage current of the circuit, and the peak amplification circuit class C when the input signal is low and below the threshold, and class AB with less idle current from class C when the input signal exceeds the threshold In the case of low input when the peak amplifier circuit does not operate, the gain at the time of low input is increased by bringing the input impedance from the distributor to the peak amplifier circuit side close to infinity. Higher-order distortion can be reduced by monotonizing the input level dependence of gain.

  The amplifier according to the embodiment of the present invention is a distributor that distributes the input to the carrier amplifier circuit and the peak amplifier circuit, and the resistance value is variable according to the input power as an isolation resistor that connects between the distribution destination ports. And a Wilkinson divider having a second voltage variable resistor between the distribution port and the port that outputs a signal to the peak amplifier circuit and the ground. The Doherty amplifier used can vary the distribution ratio in the distributor according to the input level, limit the distribution to the peak amplifier when the input is low, and suppress the gain reduction of the amplifier, Mutual interference of the peak amplifier circuit is reduced.

An amplifier according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of an amplifier according to the first embodiment of the present invention. In addition, the same code | symbol is attached | subjected and demonstrated about the part which has the structure similar to FIG.
As shown in FIG. 1, an amplifier according to a first embodiment of the present invention (first amplifier) includes an input terminal 1, a distributor 2, a transmission line 33, a phase shifter 34, and a carrier amplifier circuit. 4, a peak amplifying circuit 5, an impedance converter 64, a transmission line 65, a node (synthesis point) 62, a λ / 4 transformer 7, an output terminal 8, and an output load 9.

The carrier amplifier circuit 4 includes an input matching circuit 41, an amplification element 42, and an output matching circuit 43.
The peak amplifier circuit 5 includes an input matching circuit 51, an amplification element 52, and an output matching circuit 53.

The input terminal 1 is a terminal to which an input signal to the amplifier is input.
The distributor 2 distributes the signal input to the input terminal 1 and outputs the signal to the transmission line 33 and the phase shifter 34. The distributor 2 is, for example, a T-branch line formed on a wiring board. The same effect can be obtained not only with the T branch line but also with other couplers, baluns, rat races and the like.

The transmission line 33 is a line having an optimum reflection coefficient when the input is in the A region.
The phase shifter 34 compensates for the phase difference between the two paths so that the outputs of the carrier amplifier circuit 4 and the peak amplifier circuit 5 can be combined in phase.

The input matching circuit 41 in the carrier amplifier circuit 4 is a circuit that converts the impedance of the signal distributed by the distributor 2 into the input impedance of the subsequent amplification element 42.
The amplifying element 42 is an element that amplifies the signal. The amplifying element 42 is biased to class AB.
Output matching circuit 43 in the load impedance A region of the amplifier element 42 with the impedance converter 64 is matched to any impedance on a circle around the Z _A, in the C region matches the Z _A.

The input matching circuit 51 of the peak amplifier circuit 5 is a circuit that converts the impedance of the signal distributed by the distributor 2 into the input impedance of the subsequent amplification element 52.
The amplifying element 52 is an element that amplifies a signal. The amplifying element 52 is biased to class B or class C.

  The amplifying elements 42 and 52 are usually one of LD-MOS (Lateral Double-diffused MOS), GaAs-FET (gallium arsenide-Field Effect Transistor), HEMT (High Electron Mobility Transistor), HBT (Hetero-Bipolar Transistor) and the like. One semiconductor device.

The output matching circuit 53 is a circuit in which the load impedance of the amplifying element 52 is infinite in the A region and substantially changes to 2Z ₇ in the C region.
The input matching circuits 41 and 51 and the output matching circuits 43 and 53 are configured by either a lumped constant circuit, a distributed constant circuit, or a combination thereof.
The output matching circuits 43 and 53 may include a straight capacitance, an inductance, and the like that are unavoidable in mounting.

  The node 62 couples the output signal from the output matching circuit 43 of the carrier amplifier circuit 4 via the impedance converter 64 and the output signal from the output matching circuit 53 of the peak amplifier circuit 5 via the transmission line 65. It is a composite point.

The impedance converter 64 is an impedance converter composed of a transmission line having an electrical length of length l = 0 to λ / 2 or more. Its characteristic impedance Z ₁ is equal to 2Z ₇ = 2Z ₂ ² / Z ₀ .
The impedance converter 64 has a structure that is simply connected on the wiring board when the electrical length is 0λ.

  The transmission line 65 is for making the impedance large (ensure) so that there is no signal loss when the transmission line 65 is viewed from the node 62 in the A region.

The λ / 4 transformer 7 converts the impedance Z ₇ viewed from the node 62 into an output load Z ₀ .
The λ / 4 transformer 7 may be formed on the wiring board as a conductor pattern having a line width corresponding to the characteristic impedance Z ₂ and a length corresponding to λ / 4.
Although matching can be achieved in a relatively wide frequency range by using the λ / 4 transformer, matching means other than the λ / 4 transformer may be used as long as matching can be achieved.

Next, matching by the output matching circuit 43 and the impedance converter 64 of FIG. 1 will be described with reference to FIG. FIG. 2 is a Smith chart showing matching by the output matching circuit 43 and the impedance converter 64.
As shown in FIG. 2, first, the output matching circuit 43 is configured so that it can output the electric power P ₀ when the load Z ₉ is Z ₁ . This is the maximum output of the carrier amplifier circuit 4 alone.

That is, in the C region, the load impedance of the amplifying element 42 is matched with Z _A , and at this time, the impedance converter 64 becomes a simple transmission line.

In the region A, the output impedance of the output matching circuit 53 is infinite, so Z ₉ becomes Z ₇ when the length l = 0 or λ / 2 indicated by the point a, and the length indicated by the point b. When l = λ / 4, Z ₁ ² / Z ₇ is obtained. When the length l is moved in the range of 0 to λ / 2, Z ₉ changes clockwise on a circle centered on Z ₁ .

The impedance on the circle centered on Z ₁ is mapped onto the substantially circle centered on Z _A by the output matching circuit 43.
The points a, b and c correspond to the points a ′, b ′ and c ′, respectively, and the impedance can be changed to the points a ′, b ′ and c ′ by changing the length l. Is shown.
Therefore, the length l may be set so that the point c ′ is the position with the best performance.

  The optimum value of the length l is determined by trial (trial production), for example. The trial may be a carrier amplifier circuit alone, but it should be performed for the entire amplifier so that the performance of the entire amplifier is maximized.

According to the first amplifier, without depending on the type of amplifier element, even if the optimum position changes where on almost circumference around the Z _A, the load by changing the length l It can cope with the optimum matching of impedance.
In the above embodiment, the length l of the impedance converter 64 is set to 0 to λ / 2. However, the amplification element is large and the length between the output matching circuits 43 and 53 cannot be λ / 2 or less. In some cases, there is no problem even if the length l of the impedance converter 64 is further increased.
Z ₁ of the impedance converter 64 does not need to be completely coincident with 2Z ₇ and may be slightly deviated depending on optimization.

Next, the input-side distributor 2 and the surrounding structure will be described with reference to FIG. FIG. 3 is a block diagram showing the input-side distributor and the peripheral structure.
As shown in FIG. 3, the distributor 2 includes an input side terminal 10 connected to the input terminal 1, a first output side terminal 11 connected to the phase shifter 34, and a second output side connected to the transmission line 33. A transmission line (Z ₁₀ ) 21 provided between the terminal 12, the input side terminal 10 and the first output side terminal 11, and a transmission provided between the input side terminal 10 and the second output side terminal 12. And a track (Z ₁₁ ) 22.

Characteristic impedance Z ₁₁ of the characteristic impedance Z ₁₀ of the transmission line 21 transmission line 22 is different by the distribution ratio. In addition, it is possible to match the load of the distributed output.
In general, it is easy to design the transmission line 21 and 22 to have a line length of λ / 4.
The phase shifter 34 is a transmission line having a characteristic impedance Z ₁₂ having the same magnitude as the standard input impedance of the carrier amplifier circuit 4, and the phase is set according to its length.
The characteristic impedance of the transmission line 33 is equal to the standard input impedance when the peak amplifier circuit 5 is in operation.

The main signal is distributed to the transmission line 21 and the transmission line 22 in the distributor 2.
The distribution ratio in the distributor 2 in the vicinity of the C region is distributed to the peak amplifier circuit 5 in a large amount. This is realized by making the impedance of the transmission line 21 viewed from the input side terminal 10 larger than the impedance of the transmission line 22 viewed.

In the region A, the peak amplifier circuit 5 does not operate, so that the signal is reflected, and it is considered that reflection loss occurs when viewed from the input side terminal 10.
This means that the “transmission line 21 terminated with the load Z ₁₂ ” and the “transmission line 22 that looks almost pure reactance” are connected in parallel to the input side terminal 10 of the distributor 2.

  At this time, the impedance of the transmission line 21 viewed from the input side terminal 10 can be freely changed along the edge of the Smith chart depending on the length of the transmission line 33, and the reflection loss from the input side terminal 10 is further reduced. can do.

For example, when the transmission line 22 is λ / 4, when the length of the transmission line 33 is adjusted so that the impedance viewed from the output terminal 12 is short-circuited, the transmission line 21 is viewed from the input terminal 10. Sometimes it becomes infinite and the input signal flows through Z ₁₀ with almost no loss.
The return loss at the input side terminal 10 at this time is at most about -0.5 dB.

The input / output characteristics of the first amplifier and the conventional amplifier will be described with reference to FIG. FIG. 4 is a diagram showing input / output characteristics of the first amplifier and the conventional amplifier.
In FIG. 4, a characteristic a is an input / output characteristic of an example of a simple synthesis of class AB, and the gain increases slightly when the output increases due to the general property of the FET whose gain increases according to the drain current. As it approaches the region, it drops again due to saturation. Therefore, high order distortion is expected to occur.
a ₀ is shown with reference to a constant gain line.

Characteristic d is a conventional Doherty amplifier with an equal distribution of distribution loss of 3 dB. In the area A, the load changes compared to when the output is large, and the gain also increases. However, there is a decrease in gain due to distribution loss. In the B region, the gain in the A region is generally maintained, but the output of the peak amplifier circuit 5 is insufficient and cannot enter the C region. This is because the gain of the C class is low. Further, the gain is higher when the output is slightly higher.
Therefore, since only the operation with a low output can be performed in the entire amplifier, the original capability of the amplifying element 52 cannot be obtained and it is not economical.

The characteristic f shows a case where the distribution ratio of the distributor 2 is a non-uniformly distributed conventional Doherty amplifier having a distribution loss difference of 1 dB to 4 dB, for example, and the distribution ratio of the distributor 2 is increased on the peak amplification circuit 5 side and the carrier amplification circuit 4 side is decreased. Is. The gain reduction on the route on the carrier amplification circuit 4 side matches the gain increase on the peak amplification circuit 5 side, and the maximum output P can be amplified.
Since the distribution loss on the carrier amplifier circuit 4 side is increased, the gain of the entire first amplifier is reduced. The gain is high in the region where the output is slightly high.

When the difference in distribution loss is 0 dB, the output of the peak amplifier circuit 5 is insufficient with respect to the ideal state, and a sufficient load modulation effect cannot be obtained for the load impedance of the carrier amplifier circuit 4 as in the characteristic d. The maximum output of the Doherty amplifier is reduced.
If the difference in distribution loss is too large, the gain decreases as a whole and increases rapidly from a certain level.

  The characteristic g shows the case of the amplifier according to the embodiment. Since the peak amplifier circuit 5 does not operate in the A region, the input impedance is almost pure reactance, but the length of the transmission line 33 is appropriately set. By being set, the input impedance from the input side terminal 10 to the transmission line 22 is infinite.

  Therefore, the signal input to the distributor 2 is input to the carrier amplifier circuit 4 with a loss of about −0.5 to −1 dB.

  As described above, in the region A, even when only distribution loss is considered, the gain of the characteristic g is higher than that of the characteristic d of the equally distributed conventional Doherty amplifier by 2 dB or more. In FIG. 4, the characteristic g is shown higher than the characteristic a, but it takes into account gain increase (such as load modulation) due to the output of the carrier amplifier circuit 4 being increased by about 3 dB.

The gain increase varies depending on the type of FET, and slightly varies depending on the element and adjustment, considering the T-branch reflection loss or the combined loss.
This gain increase is adjusted by adjusting the length of the transmission line 33 to change the reflection loss of the input side terminal 10 and changing the signal input of the carrier amplifier circuit 4 system.
That is, a characteristic between the characteristic g and the characteristic f is possible.

In the region B, the input signal flows to the output side terminal 12 side of the distributor 2, the input signal decreases on the output side terminal 11 side of the distributor 2, the load of the amplifying element 42 starts to change, and the gain of the characteristic g decreases. . Further, as the input increases, the load on the amplifying element 42 further changes, and the gain decreases so as to approach the characteristic f.
In the final C region, the characteristic f is equal to the characteristic f obtained by unevenly distributing the distributor 2.

  In other words, the gain of the characteristic g increases in the vicinity of the normally used output P / 4 or lower than that of the characteristic f, so that the average added efficiency can be improved. The characteristic f shows a complicated behavior in which the gain once rises as the input increases and then decreases due to saturation. On the other hand, the characteristic g is monotonous such that the gain continues to decrease little by little as the input increases. Since it is attenuated, it is almost only third-order distortion, and when combined with distortion compensation techniques such as predistortion, compensation is easy because there is little high-order distortion.

  By adjusting the length of the transmission line 33 and adjusting the reflection loss, the gap between the characteristic g and the characteristic f can be obtained. In other words, it is possible to adjust the monotonic attenuation so that it is gentle or close to a straight line. Further, the distribution ratio and the length of the transmission line 33 may be adjusted simultaneously.

  In addition, the gain may increase by changing the distribution ratio of the distributor 2 from unequal distribution to equal distribution. In the case of an element with little gain decrease even in the C class, it is included in the C region, so the equal distribution is adopted. It is possible to do.

According to the first amplifier, as described above, the effective power to be used has a high gain and a high added efficiency, and the peak power reduces the gain, but the monotonic gain decreases. It has good compatibility with distortion compensation.
Here, the class C distribution angle of the peak amplifying element 52 is not described, but the adjustment of the amplifier is performed by adjusting the distribution angle.

Next, an amplifier according to a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a configuration block diagram of an amplifier according to the second embodiment.
As shown in FIG. 5, the amplifier according to the second embodiment (second amplifier) includes an input terminal 1, a bias control unit 150, a distributor 2, a transmission line 33, a phase shifter 34, The carrier amplifier circuit 4, the peak amplifier circuit 5, the impedance converter 64, the transmission line 65, the node (synthesis point) 62, the λ / 4 transformer 7, the output terminal 8, and the output load 9 are provided. ing.

The carrier amplifier circuit 4 includes an input matching circuit 41, an amplification element 42, and an output matching circuit 43.
The peak amplifier circuit 5 includes an input matching circuit 51, an amplification element 52, and an output matching circuit 53.

The bias controller 150 includes a branching device 15 and an adaptive bias circuit 16.
The branching device 15 branches an input signal output from the input terminal 10 to the distributor 2 to the adaptive bias circuit 16.
The adaptive bias circuit 16 detects the signal level output from the branching device 15, converts the level, and outputs the level as a bias voltage to the amplification element 52 of the peak amplification circuit 5.

  When the amplifying element 52 of the peak amplifier circuit 5 is biased to class B or class C and is controlled by the bias control unit 150, it operates as a class C amplifier when the input is low, and the input is in the middle and requires peak injection. Then, a bias gate voltage for class AB with a small idle current is supplied from the bias controller 150, and a bias gate voltage for class AB with a large idle current is supplied as the input further increases.

  The second amplifier has the same configuration and operation as the first amplifier except that a bias control unit 150 is provided and the peak amplifier circuit 5 is controlled by the bias control unit 150 as described above.

The operation of the second amplifier will be described more specifically with reference to FIG. FIG. 6 is a diagram illustrating the bias voltage characteristics.
The branching device 15 branches a part of the input signal, detects it by the adaptive bias circuit 16, converts the detection level, and changes the bias of the amplification element 52 of the peak amplification circuit 5.

  As shown in FIG. 6, in the A region, a bias value at which a drain current does not flow through the peak amplifier circuit 5, in the C region, a bias value through which a current equal to or around the drain current value flows through the carrier amplifier circuit 4, and B In the region, the bias value is an arbitrary bias value in the shape of FIG. 6 between the A region and the C region. This bias power supply may be created by other methods.

Therefore, the peak amplifying circuit 5 changes from the C class to the weak AB class and the AB class as the input increases.
A general C class amplifier has a maximum output inferior to that of the AB class. However, the bias control is characterized by the AB class synthesis in the C region.
An example of the structure of the distributor 2 and its surroundings and the operation thereof are the same as those described with reference to FIG.

  In the C region, a signal distributed at the distribution ratio of the distributor 2 is input to each amplifier circuit. When combined with the bias controller 150 at the time of equal distribution, the peak amplifier circuit 5 is basically the AB class, and the synthesis result is the same as the AB class synthesis. When the unequal distribution is combined with the bias control unit 150, the peak amplification circuit 5 is basically the AB class, and the final output of the synthesis result is the same as the AB class synthesis, but the input / output characteristics are slightly gentler.

Input / output characteristics in various methods will be described with reference to FIG. FIG. 7 is a diagram showing input / output characteristics.
In FIG. 7, characteristic a is an input / output characteristic of an example of AB class synthesis. When the output becomes high, a current flows and the gain becomes slightly high. Therefore, some high-order distortion occurs.
a ₀ is shown with reference to a constant gain line.

The characteristic b is an input / output characteristic when the impedance of the amplifier according to the embodiment viewed from the input side terminal 10 in the Z11 direction is made infinite by adjusting the transmission line 33.
Since the peak amplifying circuit 5 does not operate in the A region, the input side terminal 10 of the distributor 2 has “load Z ₁₂ on the transmission line 21 of Z ₁₀ ” and “input matching circuit on the transmission lines 22 and 33 of Z ₁₁ and Z ₁₃ ”. 51 and a substantially open amplification element 52 "are connected in parallel.

For example, when the transmission line 22 is λ / 4, when the length of the transmission line 33 is adjusted so that the impedance viewed from the output terminal 12 is short-circuited, the Z ₁₁ direction is viewed from the input terminal 10. Sometimes it becomes infinite and the input signal flows through Z ₁₀ with almost no loss.
Therefore, it is transmitted to the carrier amplifier circuit 4 with almost no loss.

When the distributor 2 is equally distributed, load modulation is performed in the area A (output side), the gain further increases, the signal enters the area B, the signal flows to the output terminal 12 side of the distributor 2, and the output terminal 11 On the side, the signal decreases, and the output power increases due to the injection from the peak amplifier circuit 5 including the bias controller 150. However, the gain gradually decreases.
Further, in the C region, the characteristics are the same as those in the normal AB class, and the gain is greatly reduced from that in the A region.

  Further, at the time of unequal distribution by the distributor 2, the gain changes in the A region, and the final output is the same as that of the AB class composition, but the input / output characteristics slightly change.

The characteristic c is a case where an adaptive bias is operated. When a normal 3 dB distributor, for example, an equal distributor such as a 3 dB coupler is used, 3 dB is lost in the A region at the time of equal distribution in the distributor 2, but due to load modulation, Although the gain increases, the distribution loss cannot be compensated and the gain decreases.
In the region B, the output is increased by the injection from the peak amplifier circuit 5 including the bias control unit 150, and the gain is gradually increased. In the C region, it is almost the same as the AB class.

  Further, at the time of unequal distribution by the distributor 2, the gain changes in the A region, and the final output is the same as that of the AB class composition, but the input / output characteristics slightly change.

  The characteristic d is the same as the characteristic d in FIG. 4. When the peak amplifying circuit 5 that does not use the bias control unit 150 is fixed to the conventional C class at the time of equal distribution in the distributor 2, compared to when the output is large in the A region. Although there is an increase in gain for load modulation, there is a decrease in gain due to distribution loss.

  In the B region, although the gain of the A region is maintained, the output of the peak amplifier circuit 5 is insufficient and cannot enter the C region. Since only a low output operation can be used in addition to a decrease in gain, the original capability of the amplifying element 52 cannot be obtained and it is not economical.

  The characteristic e is adjusted between the characteristic a and the characteristic b by the input reflection coefficient, unequal distribution, etc., and the gain increases in the area close to the high output of the characteristic a. Therefore, in the small signal area (A area) The gain is increased moderately. Since the peak amplification circuit 5 does not operate in the A region, the signal is reflected and a reflection loss occurs when viewed from the input terminal 1.

This is because the input side terminal 10 of the distributor 2 has “a load Z ₁₂ on the transmission line 21 of Z ₁₀ ” and “an input matching circuit 51 and a substantially open amplification element 52 on the transmission lines 22 and 33 of Z ₁₁ and Z ₁₃ ”. Are connected in parallel.
Therefore, the impedance seen from the input side terminal 10 toward the output side terminal 12 of the distributor 2 changes the reflection loss from the input side terminal 10 by changing the length of the transmission line 33. Therefore, the signal level to the carrier amplifier circuit 4 system is lowered and lowered from the characteristic b.

  The input level of the carrier amplifier circuit 4 can be changed by changing the length of the transmission line 33, changing the distribution ratio of the distributor 2, or changing both.

In the A region (output side), the distribution loss (including reflection loss) is moderate, the gain increases due to the load modulation compared to when the output is large, enters the B region, and the output side terminal 12 side of the distributor 2 In the output terminal 11 side, the signal decreases, the gain increase due to load modulation decreases, and the output power increases due to the injection from the peak amplifier circuit 5 including the bias control unit 150, but the gain gradually increases. It goes down.
The characteristic e operates in the same way as the characteristic b and is linear or monotonous attenuation, but has a gentler slope than the characteristic b and reduces distortion.

An amplification element having a large gain amplification on the high output side of the characteristic a is linear while increasing the gain by the characteristic e (changing the reflection loss and changing the input of the carrier amplifier circuit 4).
Furthermore, in the C region, the characteristics are almost the same as those of the normal AB class, and the gain is greatly reduced compared to the A region.

As a method other than the method of changing the distribution loss by changing the length of the transmission line 33, the distribution ratio of the distributor 2 may be changed, or both the length of the transmission line 33 and the distribution ratio of the distributor 2 may be changed. However, the optimum method may be selected by checking the characteristics of the amplifying element. This is because the characteristics differ depending on the type of element, item, etc., and the optimum state is selected.
Here, although the distribution angle is not described even in class C of the peak amplifying element 52, the distribution angle is adjusted to perform overall adjustment of the amplifier.

According to the second amplifier, the gain is high at the effective power used, the added efficiency is high, and the gain is reduced at the peak power. However, as shown in FIG. 7, the characteristic e is substantially the third order distortion, and the fifth order distortion having the undulations of the characteristic a and the characteristic c is reduced.
In addition, the characteristic b and the characteristic b and the characteristic e are monotonically attenuated, and when combined with distortion compensation such as predistortion, distortion compensation can be easily performed.

  In addition, for multi-way hearty amplifiers that use multiple carrier amplifier circuits and multiple peak amplifier circuits, efficiency, distortion, etc. can be improved in the same way as above, and compatibility with distortion compensation such as predistortion Is good.

  According to the first and second amplifiers, the gain is increased and the added efficiency is increased as compared with a normal AB class amplifier, and it is extremely compatible with distortion compensation such as predistortion due to the reduction of higher-order distortion. Has the effect of improving.

Next, an amplifier according to a third embodiment of the present invention will be described.
Before describing the amplifier according to the third embodiment, a commonly used distributor will be described. In general, in 1960, E. A circuit called “Wilkinson Power Divider” (Wilkinson Divider) published by IEEE by Wilkinson is often used. FIG. 10 is a configuration diagram illustrating an example of a general Wilkinson distributor.

  As shown in FIG. 10, a general Wilkinson bi-distributor has transmission lines 71 and 72 having a characteristic impedance of 70.7Ω and an electrical length of λ / 4, and resistances that isolate ports 2 and 3 with 100Ω. (Isolation resistor) 73. The circuit shown in FIG. 10 is a two-distributor under the condition that a load of 50Ω is applied to ports 1, 2, and 3.

The electrical characteristics of the two distributor shown in FIG. 10 will be described.
A signal input from port 1 is equally distributed to port 2 and port 3. For example, when a 0 dBm signal is input to port 1, a -3 dB signal is output to the terminals of port 2 and port 3. At this time, the reflection characteristics of each port and the isolation between the ports (port 2 and port 3) are good.

The signal (reflection) input from the port 2 is divided into two signals, a signal A that goes to the port 3 through a 100Ω resistor and a signal B that is output to the port 3 through two 70.7Ω transmission lines. . Since the length of the transmission line is λ / 4, the phases of the signal A and the signal B are different by λ / 2 (180 °). Therefore, since two signals appearing at the port 3 through different paths have the same amplitude and opposite phases, good isolation can be obtained.
Such a dual distributor is also used in a Doherty amplifier that has recently attracted attention as a high efficiency amplifier.

However, when the general two-distributor as shown in FIG. 10 is used as the distributor 2 of the general Doherty amplifier as shown in FIG. 8, only the carrier amplifier is used at the time of low input as described above. Since it does not operate, a gain reduction occurs, and at the time of high input, the peak amplifier is biased to the BC class. Therefore, the gain is not equal to that of the AB class, and a gain reduction occurs.
Further, when a general two distributor is used in the configuration of FIG. 1 or FIG. 5, there is mutual interference between the carrier amplifier circuit 4 and the peak amplifier circuit 5, and the frequency characteristics are slightly deteriorated.

  In the amplifier according to the third embodiment, instead of the distributor 2 shown in FIGS. 1 and 5 and the general distributor shown in FIG. 10, an isolation resistance variable type distributor having a variable isolation resistance is used. Thus, the distribution ratio between the carrier amplifier circuit and the peak amplifier circuit is made variable according to the input power so as to prevent the gain from being lowered, and the mutual interference between the carrier amplifier circuit 4 and the peak amplifier circuit 5 is reduced.

The configuration of the amplifier according to the third embodiment will be described with reference to FIG. FIG. 11 is a configuration block diagram of an amplifier according to the third embodiment.
As shown in FIG. 11, the amplifier (third amplifier) according to the third embodiment includes an input terminal 1, a directional coupler 102, a detection circuit 103, a control unit 104, a delay circuit 105, The isolation resistance variable distributor 101, the phase shifter 3, the carrier amplifier circuit 4, the peak amplifier circuit 5, the Doherty synthesizer 6, the λ / 4 transformer 7, the output terminal 8, and the output load 9 And.

The carrier amplifier circuit 4 includes an input matching circuit 41, an amplification element 42, and an output matching circuit 43.
The peak amplifier circuit 5 includes an input matching circuit 51, an amplification element 52, and an output matching circuit 53.
The Doherty combining unit 6 includes a λ / 4 transformer 61 and a node 62.

The directional coupler 102 is a branching device that branches the signal output from the input terminal 1 to the delay circuit 105 to the detection circuit 103.
The detection circuit 103 is composed of, for example, a Schottky diode, converts the power of the signal input from the directional coupler 102 into a voltage, and outputs the voltage to the control unit 104 as an input power level.

The control unit 104 is configured by, for example, an operational amplifier, and controls signals (Vc1, Vc2) that respectively control resistance values of two variable resistors provided in the isolation resistor variable distributor 101 described later according to the input power level. ) Is output.
The delay circuit 105 delays the input signal and corrects the delay difference from the control signals (Vc1, Vc2).

Next, the isolation resistance variable distributor 101 which is a characteristic part of the third amplifier will be described with reference to FIG. FIG. 12 is a configuration block diagram of the isolation resistance variable distributor 101.
As shown in FIG. 12, the variable isolation resistor type distributor 101 is a variable resistor that isolates transmission lines 71 and 72 having a characteristic impedance of 70.7Ω and an electrical length of λ / 4, and ports 2 and 3. And a variable resistor 75 for changing the impedance of the port 2.

  The variable resistors 74 and 75 have a circuit configuration in which diodes and the like are combined. The variable resistor 74 is controlled by a control signal (control voltage) Vc1 from the control unit 104, and the variable resistor 75 is controlled by a control signal (control voltage). The resistance value changes according to Vc2.

  When this distributor is used in the amplifier of FIG. 11, the delay circuit 105 is connected to the port 1, the peak amplifier circuit 5 is connected to the port 2, and the carrier amplifier circuit 4 is connected to the port 3. .

Here, control of the variable resistor of the isolation resistance variable type distributor 101 will be described with reference to FIG. FIG. 13A is an explanatory diagram illustrating a setting example of a variable resistor in the isolation resistance variable distributor 101, and FIG. 13B is a schematic diagram illustrating a control example of resistance values of the variable resistors 74 and 75. FIG.
In FIG. 13, “voltage variable resistor 1” corresponds to the variable resistor 74, and “voltage variable resistor 2” corresponds to the variable resistor 75.

  When the input power is low, as shown in FIG. 13A, the control unit 104 determines that the voltage variable resistor 1 (variable resistor 74) = 1 KΩ and the voltage variable resistor 2 (variable resistor) according to “Setting 1”. 75) = 1Ω, the input to the peak amplifier circuit 5 is limited, and a large amount is distributed to the carrier amplifier circuit 4 side. At this time, the insertion loss between port 1 and port 2 is -30 dB, the insertion loss between port 1 and port 3 is -1 db, and the loss is smaller on the carrier amplifier circuit 4 side than -3 dB at the time of equal distribution.

  Conversely, when the input power level is high, as shown in FIG. 13B, the control unit 104 determines that the voltage variable resistor 1 (variable resistor 74) = 100Ω and the voltage variable resistor 2 ( The variable resistor 75) is set to 1 KΩ and is equally distributed. At this time, the insertion loss between port 1 and port 2 is −3 dB, and the insertion loss between port 1 and port 3 is −3 db.

  The isolation between the ports 2 and 3 is determined by the relationship between the input of the resistor 74 and the resistance value. However, since the peak amplifier circuit does not operate in the A region, the isolation is not a problem. In the C region, the resistor 74 is 100Ω. Therefore, sufficient isolation (about 30 dB) is obtained, and at least resistance is added in the B region, so that further sufficient isolation can be obtained in a place close to about 10 dB or the C region.

  That is, when there is little influence on the amplifiers (B area close to the A area), the isolation may be small, and when the influence is large (B area close to the C area), sufficient isolation can be obtained. is there.

The control unit 104 stores an input power level and corresponding control voltages Vc1 and Vc2 for setting the variable resistors 74 and 75 to desired resistance values.
For example, as shown in FIG. 13B, in the section where the input power level changes from the low input level to the high input level, the resistance values of the variable resistors 74 and 75 are changed from the setting 1 value to the setting 2 value. In order to change gradually, the resistance value of each variable resistor is controlled according to the input power, the distribution ratio is adjusted, and isolation is also obtained.
As a result, when the input is low, a large amount can be distributed to the carrier amplifier circuit 4 to prevent a decrease in gain, and the mutual interference between the carrier amplifier circuit 4 and the peak amplifier circuit 5 is reduced.

According to the amplifier according to the third embodiment of the present invention, as a distributor that distributes input power to the carrier amplifier circuit 4 and the peak amplifier circuit 5, the port 3 and the peak amplifier circuit 5 that output to the carrier amplifier circuit 4 are used. A variable resistor 74 is provided between the output port 2 and the variable resistance 75 is provided between the port 2 output to the peak amplifier circuit 5 and the ground. The resistance value of the variable resistor 74 and the variable resistor 75 is controlled according to the input power level detected by the detection circuit 103 so that the distribution ratio is variable, and the distribution to the peak amplifier circuit 5 side is limited when the input is low. Therefore, a large amount can be distributed to the carrier amplifier circuit 4 side to prevent a decrease in gain at the low input level of the Doherty amplifier. Further, the carrier amplifier circuit 4 and the peak amplifier circuit 5 are mutually connected. There is an effect of reducing the negotiations.
Although the third amplifier is a Wilkinson divider, other dividers can be similarly implemented.

Further, the impedance of the peak amplifier circuit 5 viewed from the port 2 is only a reactance component at a low level where the peak amplifier circuit 5 does not operate, and a short-circuit can be easily achieved by the transmission line. Instead, a fixed transmission line may be used.
As described above, the variable resistors 74 and 75 are operated simultaneously. However, the variable resistor 74 alone has a sufficient effect.

Next, an amplifier according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 14 is a block diagram showing the configuration of an amplifier according to the fourth embodiment of the present invention.
As shown in FIG. 14, the amplifier (fourth amplifier) according to the fourth embodiment of the present invention has substantially the same configuration as that of the third amplifier shown in FIG. A detector 101, a detection circuit 103, a control unit 104, and a delay circuit 105 are provided. The isolation resistor 74 reduces the mutual interference between the carrier amplifier circuit 4 and the peak amplifier circuit 5.

As a feature of the fourth amplifier, in addition to controlling the variable resistors 74 and 75 of the isolation resistance variable distributor 101, the control unit 104 controls the amplification element 52 of the peak amplifier 5 according to the input power level. It controls the bias voltage.
The bias voltage is applied to the terminal 106. The terminal 106 is a base terminal when the amplifying element 52 is a transistor, and is a gate terminal when the FET (Field-Effect Transistor) is used. Here, the case of FET will be described as an example.

A control example of the gate voltage of the amplification element 52 of the peak amplification circuit 5 will be described with reference to FIG. FIG. 15 is an explanatory diagram illustrating a control example of the gate voltage of the amplifying element 52 in the fourth device.
As shown in FIG. 15, the control unit 104 applies a low gate voltage when the input power level is low based on the input power level from the detection circuit 103, and increases the gate voltage as the input power level increases. Apply the gate voltage according to the level.
Specifically, the control of the gate voltage is the same as the method described with reference to FIG. 6 for the second amplifier, and as the input power level increases, the amplification element is changed from C class to weak AB class and AB class. The gate voltage of 52 is controlled.

Further, the input / output characteristics of the fourth amplifier are substantially the same as the characteristics shown in FIG.
In the section A where the input power is low, the resistance values of the variable resistors 74 and 75 of the isolation resistance variable type distributor 101 are set to “setting 1” shown in FIG. The insertion loss can be reduced to about -1 dB.
On the contrary, the insertion loss between the port 1 and the port 2 increases (−30 dB) in this section, but there is no problem because the peak amplifier circuit 5 does not operate in the section A.

  Further, in the B section where the input power is high, the resistance values of the variable resistors 74 and 75 of the isolation resistance variable distributor 101 are set to “setting 2” shown in FIG. 101 is a general Wilkinson type two divider (equal distribution, good isolation), and further, the gate terminal of the amplifying element 52 in the peak amplifying circuit 5 is appropriately set according to the input power level as shown in FIG. Apply gate voltage. The transition region is the same as the third amplifier.

  By performing these controls, the fourth amplifier can suppress a decrease in gain at the power power level at both the low input power level and the high input power level, and the combined output shown in FIG. Thus, the monotonic attenuation characteristic is obtained. If the distribution ratio of the distributor 101 is changed and the variable resistor 74 is changed in the same way, the characteristics shown in FIG. 7E can be obtained.

  According to the amplifier of the fourth embodiment of the present invention, the variable resistor 74 is output to the peak amplifier circuit 5 between the port 3 output to the carrier amplifier circuit 4 and the port 2 output to the peak amplifier circuit 5. The isolation resistor variable distributor 101 having a variable resistor 75 provided between the port 2 to be grounded and the ground is provided, and the control unit 104 can change the variable resistor 74 and variable according to the input power level detected by the detection circuit 103. The resistance value of the resistor 75 is controlled to make the distribution ratio variable. When the input is low, the distribution to the peak amplifier circuit 5 side is restricted, and the bias voltage of the amplifier element 52 of the peak amplifier circuit 5 according to the input power level. Is controlled to be class C when input is low and operates as class AB when input is high, so that it is close to the combined output of class AB booster, so the gain decreases at both low and high inputs. It can be prevented, there is an effect that it is possible to improve the power added efficiency of the Doherty amplifier.

Furthermore, there is an effect that the mutual interference between the carrier amplifier circuit 4 and the peak amplifier circuit 5 can be reduced.
As described above, the variable resistors 74 and 75 are operated at the same time, but the variable resistor 74 alone can provide a sufficient effect.

  INDUSTRIAL APPLICABILITY The present invention is suitable for an amplifier that can prevent a gain decrease due to a distribution loss of an input distributor of a high-efficiency Doherty amplifier, achieve a high gain, suppress an increase in high-order distortion, and reduce high-order distortion.

1 is a configuration block diagram of an amplifier according to a first embodiment of the present invention. 5 is a Smith chart showing matching by an output matching circuit 43 and an impedance converter 64. It is a block diagram which shows an input side divider | distributor and peripheral structure. It is a figure which shows the input / output characteristic of a 1st amplifier and the conventional amplifier. FIG. 5 is a configuration block diagram of an amplifier according to a second embodiment. It is a figure which shows a bias voltage characteristic. It is a figure which shows an input / output characteristic. It is a block diagram of a conventional Doherty amplifier. It is a figure which shows the theoretical collector efficiency and drain efficiency which concern on the conventional Doherty amplifier. It is a block diagram which shows an example of a common Wilkinson divider | distributor. FIG. 5 is a configuration block diagram of an amplifier according to a third embodiment. FIG. 3 is a block diagram showing the configuration of a variable isolation resistance distributor 101. (A) is explanatory drawing which shows the example of a setting of the variable resistor in the isolation resistance variable type | mold distributor 101, (b) is typical explanatory drawing which shows the example of control of the resistance value of the variable resistors 74 and 75. is there. FIG. 6 is a configuration block diagram of an amplifier according to a fourth embodiment of the present invention. It is explanatory drawing which shows the example of control of the gate voltage of the amplification element 52 in a 4th apparatus.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Input terminal, 2 ... Divider, 3 ... Phaser, 4 ... Carrier amplifier circuit, 5 ... Peak amplifier circuit, 6 ... Doherty synthesis part, 7 ... λ / 4 transformer, 8 ... Output terminal, 9 ... Output load , 10 ... input side terminal, 11 ... first output side terminal, 12 ... second output side terminal, 15 ... branching device, 16 ... adapti bias circuit, 21, 22 ... transmission line, 33 ... transmission line, 34 ... Phase shifter, 41, 51 ... Input matching circuit, 42, 52 ... Amplifying element, 43, 53 ... Output matching circuit, 61 ... λ / 4 transformer, 62 ... Node, 64 ... Impedance converter, 65 ... Transmission line, 71, 72 ... Transmission line, 74, 75 ... Variable resistor, 101 ... Variable isolation resistor type, 102 ... Directional coupler, 103 ... Detection circuit, 104 ... Control unit, 105 ... Delay circuit, 106 A gate terminal (base terminal), 150 ... bias controller

Claims (7)

A distributor for equally or unevenly distributing the input signal;
A carrier amplification circuit for operating and amplifying equally distributed or less unevenly distributed signals in class AB;
A first transmission line that adjusts the reflection coefficient at the time of low input by adjusting the length of the line with respect to an equally distributed signal or a highly unevenly distributed signal;
A peak amplifying circuit that operates and amplifies the signal from the first transmission line in class B or class C;
An impedance converter for converting impedance with respect to a signal from the carrier amplifier circuit;
A second transmission line that reduces the influence of the peak amplifier at the time of low input;
A node that combines the termination of the impedance converter and the termination of the second transmission line to synthesize the outputs of the carrier amplification circuit and the peak amplification circuit;
An output load connected to the node;
An amplifier comprising: a transformer provided between the node and the output load and converting an impedance to the output load with respect to an output from the node. A distributor for equally or unevenly distributing the input signal;
A carrier amplification circuit for operating and amplifying equally distributed or less unevenly distributed signals in class AB;
A first transmission line that adjusts the reflection coefficient at the time of low input by adjusting the length of the line with respect to an equally distributed signal or a highly unevenly distributed signal;
A peak amplifying circuit that operates and amplifies the signal from the first transmission line in class B or class C;
An impedance converter for converting impedance with respect to a signal from the carrier amplifier circuit;
A second transmission line that reduces the influence of the peak amplifier at the time of low input;
A node that combines the termination of the impedance converter and the termination of the second transmission line to synthesize the outputs of the carrier amplification circuit and the peak amplification circuit;
An output load connected to the node;
A transformer provided between the node and the output load for converting impedance to the output load with respect to an output from the node;
A branching device provided before the distributor and branching the input signal;
An adaptive bias circuit that detects a signal output from the branching device, converts the level, and outputs the bias current of the peak amplifier circuit;
The peak amplifying circuit is class C when the input signal is a low input below the threshold value, and when the input signal exceeds the threshold value, the class A is changed from class C to class AB with a small idle current and class AB with a large idle current. An amplifier characterized by operation.   The first transmission line length is changed or / and the distribution ratio in the distributor is set such that the peak amplifier circuit is large and the carrier amplifier circuit side is small, and the difference in distribution loss is 1 to 4 dB. The amplifier according to claim 1 or 2.   The distributor includes an input terminal connected to the input terminal, a first output terminal connected to the phase shifter, a second output terminal connected to the first transmission line, the input terminal, and the first terminal. A third transmission line provided between the first output side terminal and a fourth transmission line provided between the input side terminal and the second output side terminal. 4. The amplifier according to claim 1, wherein the impedance of the line and the impedance of the fourth transmission line are matched to the load of the distribution output. A distributor for distributing an input signal to two ports;
A carrier amplification circuit that operates and amplifies the distributed signal in class AB;
A peak amplification circuit that operates and amplifies the distributed signal in class B or class C;
An impedance converter for converting impedance with respect to a signal from the carrier amplifier circuit;
A node for combining the terminal of the impedance converter and the terminal of the peak amplifier circuit to combine the outputs of the carrier amplifier circuit and the peak amplifier circuit;
An output load connected to the node;
An amplifier that is provided between the node and the output load and that converts an impedance of the output from the node to the output load;
The distributor is a distributor including a first voltage variable resistor that connects between ports of distribution destinations,
A branching device provided before the distributor and branching the input signal;
A detector that detects a signal output from the branching device and outputs an input power level;
An amplifier comprising: a control unit that increases resistance between the ports by controlling a resistance value of the first voltage variable resistor of the distributor according to the input power level.   The control unit controls the bias voltage of the peak amplifier circuit according to the input power level so that the input signal is class C when the input signal is lower than the threshold value, and class C when the input signal exceeds the threshold value. 6. The amplifier according to claim 5, wherein the amplifier is operated in a class AB having a large idle current through a class AB having a small idle current. The distributor is a distributor including a second voltage variable resistor at a port for outputting the distributed signal to the peak amplifier circuit;
6. The control unit according to claim 5, wherein the control unit is a control unit that controls a resistance value of the second voltage variable resistor to adjust a distribution ratio and restricts an input of the peak amplifier circuit according to an input level. Or the amplifier of 6.

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