CN116093233A - High-reliability film flip Micro-LED display chip and preparation method thereof - Google Patents

High-reliability film flip Micro-LED display chip and preparation method thereof Download PDF

Info

Publication number
CN116093233A
CN116093233A CN202310017693.4A CN202310017693A CN116093233A CN 116093233 A CN116093233 A CN 116093233A CN 202310017693 A CN202310017693 A CN 202310017693A CN 116093233 A CN116093233 A CN 116093233A
Authority
CN
China
Prior art keywords
layer
chip
substrate
passivation
gan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310017693.4A
Other languages
Chinese (zh)
Inventor
周圣军
施浪
孙月昌
蒋晶晶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangsu Chuandu Optoelectronic Technology Co ltd
Original Assignee
Wuhan University WHU
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan University WHU filed Critical Wuhan University WHU
Priority to CN202310017693.4A priority Critical patent/CN116093233A/en
Publication of CN116093233A publication Critical patent/CN116093233A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The application discloses a high-reliability film flip Micro-LED display chip and a preparation method thereof. In the technical scheme, the electrochemical corrosion technology and the mechanical stripping technology are utilized to realize high-efficiency and low-cost stripping of the substrate, the ion implantation technology is utilized to realize effective passivation of the suspension bond on the side wall of the chip, a surface electric field is formed, and non-radiative recombination of electrons and holes on the surface of the chip is inhibited. In addition, the Micro-LED display chip is further passivated by depositing a composite passivation layer on the side wall of the chip. The composite passivation layer comprises a passivation bottom layer and a passivation top layer which are stacked in sequence, the passivation bottom layer is used for contacting the surface of the thin film flip-chip Micro-LED display chip, the passivation top layer is made of a high dielectric constant material, the high dielectric constant material enables the surface energy band of the chip to bend, a large hole potential barrier is generated, holes are restrained from moving to the surface of the thin film flip-chip Micro-LED display chip, the surface recombination rate of the thin film flip-chip Micro-LED display chip is reduced, and the reliability of the thin film flip-chip Micro-LED display chip is improved.

Description

High-reliability film flip Micro-LED display chip and preparation method thereof
Technical Field
The application relates to the technical field of semiconductor light-emitting devices, in particular to a high-reliability thin film flip Micro-LED display chip and a preparation method thereof.
Background
Micro light emitting diode (Micro-LED) display chips are considered as a next generation display technology that is secondary to Liquid Crystal Display (LCD) and Organic Light Emitting Diode (OLED) display because of their small size, self-luminescence, high efficiency, high brightness, high resolution, long life, and the like. In order to inhibit the problem of luminescence crosstalk between adjacent Micro-LED pixels, a substrate stripping technology is generally adopted to strip the growth substrate of the flip-chip Micro-LED chip, so as to manufacture a thin film flip-chip Micro-LED chip structure. However, the conventional substrate peeling technology (such as the laser peeling technology) has the defects of high process difficulty, serious damage to the epitaxial layer, low peeling speed and the like, so that the substrate peeling technology with high peeling speed and low cost is required.
The size of the thin film flip-chip Micro-LED display chip is generally several tens of micrometers to several micrometers, and as the size of the thin film flip-chip Micro-LED display chip decreases, the luminous efficiency thereof drastically decreases. The reason for this phenomenon is the surface recombination effect of the thin film flip-chip Micro-LED chip. Compared with the traditional large-size LED (the size is hundreds of micrometers to millimeters), the ratio of the area of the side wall of the thin film flip-chip Micro-LED to the total surface area is large, the surface damage on the side wall caused by dry etching is used as a non-radiation recombination center to generate non-radiation recombination, the radiation recombination of an active area is inhibited, the light-emitting efficiency of the thin film flip-chip Micro-LED chip is reduced, and the reliability of the device is weakened. As the size of thin film flip-chip Micro-LED display chips decreases, the surface recombination effect becomes more severe. Therefore, there is a need to design a high reliability thin film flip-chip Micro-LED display chip.
Disclosure of Invention
In view of the above, the application provides a high-reliability thin film flip-chip Micro-LED display chip and a preparation method thereof, which can effectively reduce the surface recombination effect of the flip-chip Micro-LED chip and improve the reliability of the thin film flip-chip Micro-LED display chip.
In a first aspect, the present application provides a method for manufacturing a high-reliability thin film flip-chip Micro-LED display chip, including the steps of:
s1, epitaxial growth of GaN on a substrateA base epitaxial layer comprising an n-GaN layer and an In layer stacked In sequence 0.12 Ga 0.88 An N/GaN multiple quantum well layer and a p-GaN layer;
s2, depositing an ITO current expansion layer with ohmic contact with the p-GaN layer on the surface of the p-GaN layer of the GaN-based epitaxial layer;
s3, etching the GaN-based epitaxial layer to form a step structure;
s4, implanting nitrogen ions into the side wall of the step structure by adopting an ion implantation technology to form passivation;
s5, sequentially depositing a passivation bottom layer and a passivation top layer made of a high dielectric constant material on the side wall of the step structure from first to second;
s6, depositing a Distributed Bragg Reflector (DBR) on the surface of the passivation top layer;
s7, depositing a plurality of layers of metal electrodes on the surfaces of the n-GaN layer and the ITO current expanding layer respectively to form an n electrode and a p electrode;
s8, stripping the substrate.
Optionally, before S1, the method further includes: s11, forming a porous structure on the surface and the inside of the substrate, wherein the density of holes close to the surface of the substrate is large, the size of holes is small, and the density of holes in the inside of the substrate is small, and the size of holes is large.
Preferably, in S11, the porous structure is formed by electrochemical etching.
Optionally, S12 is further included before S1 and after S11, to heal the holes on the surface of the substrate, and to planarize the surface of the substrate.
Preferably, at S12, the hole heals by annealing.
Alternatively, the substrate is a silicon substrate (Si), a germanium substrate (Ge), silicon carbide (SiC), or a gallium nitride single crystal substrate (GaN).
Optionally, in S8, the manner of peeling the substrate is mechanical peeling;
preferably, after S8, the step structure further comprises removing the remaining substrate by wet etching.
Optionally, in S1, the manner of epitaxially growing the GaN-based epitaxial layer on the substrate is Metal Organic Chemical Vapor Deposition (MOCVD);
preferably, in S2, forming the ITO current spreading layer includes:
s21, depositing an ITO transparent conductive film on the surface of the p-GaN layer by adopting an electron beam evaporation technology;
s22, forming an ITO current expansion layer on the ITO transparent conductive film by adopting a photoetching and wet etching technology;
s23, annealing the ITO current expansion layer to enable the ITO current expansion layer to form ohmic contact with the p-GaN layer;
preferably, in S23, the annealing atmosphere is nitrogen, and the annealing temperature is 550 ℃;
preferably, the thickness of the ITO transparent conductive film is 10nm.
Optionally, in S3, the step structure is formed by first forming a pattern by photolithography, and then etching by using an Inductively Coupled Plasma (ICP) technique;
preferably, the step depth is 700-800 nm.
Optionally, in S5, depositing a passivation bottom layer is an Atomic Layer Deposition (ALD) technique;
preferably, the thickness of the passivation bottom layer is 2-3 nm;
preferably, the thickness of the passivation top layer is 30nm;
preferably, the passivation bottom layer material is Al 2 O 3 ；
Preferably, the passivation top layer material is HfO 2 、Ta 2 O 5 、ZrO 2 、Bi 2 SeO 5 Or Sb (Sb) 2 O 3 。
Optionally, in S6, the deposition mode of the distributed bragg reflector is a Plasma Enhanced Chemical Vapor Deposition (PECVD) technique;
preferably, the distributed Bragg reflector is made of Ti 3 O 5 Or SiO 2 ；
In S7, the deposition method for forming the n-electrode and the p-electrode is an electron beam evaporation technique;
preferably, the material of the multilayer metal electrode is Cr, pt or Au.
As used herein, the term "electrochemical etching technique" refers to immersing a substrate in an electrolyte, placing an anode electrode in the electrolyte, and connecting another cathode electrode to the substrate to effect etching of the substrate.
As mentioned above, the "ion implantation technology" is to implant nitrogen ions into the side wall of the chip to achieve effective passivation, on one hand, nitrogen ions are combined with dangling bonds on the surface of the chip, so that the density of the surface state of the chip is reduced, the surface recombination velocity is reduced, on the other hand, a large amount of nitrogen ions are accumulated on the surface of the chip, and a surface electric field is formed on the surface of the chip of nitrogen ions, so that electrons can be prevented from moving to the surface of the chip, the surface recombination velocity is reduced, and the reliability of the chip is improved.
A passivation composite layer stacked by a passivation bottom layer and a passivation top layer, wherein the passivation bottom layer material is used for isolating the side wall of the chip from being contacted with water vapor of air, so as to reduce the surface state density; the passivation top layer is covered on the passivation bottom layer by adopting a high dielectric constant material, the high dielectric constant material realizes the bending of the chip surface energy band, generates a large hole barrier, and prevents the hole from generating surface recombination on the surface of the thin film flip Micro-LED display chip.
In a second aspect, the present application provides a high reliability thin film flip-chip Micro-LED display chip obtained by the above-described manufacturing method.
The technical scheme that this application provided has following beneficial effect:
(1) The ion implantation technology is adopted to realize effective passivation, so that dangling bonds on the side wall of the chip are passivated, a surface electric field is formed, and non-radiative recombination of carriers on the surface of the chip is inhibited.
(2) The composite passivation layer is deposited on the side wall of the chip, wherein the composite passivation layer comprises a passivation bottom layer and a passivation top layer which are stacked in sequence, the passivation bottom layer is used for contacting the surface of the thin film flip-chip Micro-LED display chip, positive charges are accumulated in the interface of the passivation bottom layer to form an electric field, and movement of holes to the surface of the thin film flip-chip Micro-LED display chip is restrained. The passivation top layer is made of a high-dielectric constant material, the high-dielectric constant material realizes the bending of the chip surface energy band, and a large hole potential barrier is generated to prevent holes from surface recombination on the surface of the thin film flip Micro-LED display chip.
(3) The electrochemical corrosion technology is adopted to corrode the substrate, holes are formed in the substrate, and the subsequent mechanical stripping technology can realize stripping.
Drawings
Technical solutions and other advantageous effects of the present application will be made apparent from the following detailed description of specific embodiments of the present application with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of the result of forming a porous structure on top and inside a substrate using electrochemical etching techniques according to an embodiment of the present application;
FIG. 2 is a schematic diagram of the results of planarizing holes in a substrate surface using an annealing technique and a chemical mechanical polishing technique according to an embodiment of the present application;
FIG. 3 is a schematic diagram of the result of forming isolation trenches on a substrate by using MOCVD technique to epitaxially grow GaN-based epitaxy on the substrate and using photolithography and ICP etching techniques according to the embodiment of the present application;
FIG. 4 is a schematic diagram of the result of depositing an ITO transparent conductive layer using electron beam evaporation technique according to an embodiment of the present application;
fig. 5 is a schematic diagram of a result of forming a step structure by using an ICP etching technique and further passivating a side wall of a chip by using an ion implantation technique according to an embodiment of the present application;
FIG. 6 is a schematic diagram of the results of ALD techniques for depositing a passivation bottom layer and passivation top layer on the sidewalls of a chip, as provided in the examples herein;
FIG. 7 is a schematic diagram of the result of deposition of DBR on the chip side wall using PECVD technique according to one embodiment of the present application;
FIG. 8 is a schematic diagram of the results of depositing multilayer electrodes on n-GaN and ITO surfaces using electron beam evaporation techniques according to embodiments of the present application;
FIG. 9 is a schematic diagram of the results of removing a substrate using a mechanical lift-off technique provided in an embodiment of the present application;
FIG. 10 illustrates removal of residual substrate using wet etching techniques provided in an embodiment of the present application;
fig. 11 is a schematic diagram of the principle of implanting nitrogen ions to passivate the sidewalls of a chip according to the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below in connection with the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or an implicit indication of the number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not in themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.
The embodiment provides a preparation method of a high-reliability film flip Micro-LED display chip, which specifically comprises the following steps:
(1) As shown in fig. 1, the electrochemical corrosion technology is adopted to corrode the substrate, so that a large number of porous structures are formed on the surface and inside the substrate, the density of holes close to the surface of the substrate is large, the size of the holes is small, the density of holes inside the substrate is small, and the size of the holes is large;
here, the substrate includes a silicon substrate (Si), a germanium substrate (Ge), silicon carbide (SiC), and a gallium nitride single crystal substrate (GaN).
(2) As shown in fig. 2, the annealing method is adopted to heal the holes on the surface of the substrate, so that the surface of the substrate is leveled, the chemical mechanical polishing technology is adopted to further level the surface of the substrate, the growth of subsequent epitaxial materials is facilitated, and the position 1-2 microns below the surface of the substrate is still in a porous structure, so that a fracture position is provided for the subsequent mechanical stripping of the substrate.
(3) As shown in fig. 3, a GaN epitaxial layer structure is sequentially grown on a substrate by MOCVD equipment, wherein the GaN epitaxial layer structure comprises from bottom to top: n-GaN layer 2, in 0.12 Ga 0.88 An N/GaN multiple quantum well layer 3 and a p-GaN layer 4.
(4) As shown in fig. 4, an ITO transparent conductive film 5 with a thickness of 10nm is deposited on the surface of the chip by using an electron beam evaporation technique, and an ITO current expansion layer is formed by using photolithography and wet etching techniques. At N 2 And carrying out thermal annealing at 550 ℃ in the atmosphere so that the ITO and the p-GaN layer form ohmic contact.
(5) As shown in FIG. 5, BCl is used 3 /Cl 2 And etching the GaN-based epitaxial structure by the mixed gas to form a step structure, wherein the step depth is 600-700 nm. And implanting nitrogen ions into the side wall of the chip by adopting an ion implantation technology, and passivating the side wall of the chip.
(6) As shown in FIG. 6, ALD technique is used to deposit on the chip side wallAl with product of 2-3 nm thick 2 O 3 A passivation bottom layer 6 and a high dielectric constant passivation top layer 7 of 30nm thickness.
Wherein, the ALD technique grows Al 2 O 3 The passivation bottom layer has good uniformity, no pinholes are formed on the surface of the film layer, the film forming quality is good, and the water vapor can be prevented from entering the device. The passivation top layer is covered on the passivation bottom layer by adopting a high dielectric constant material, the high dielectric constant material realizes the bending of the chip surface energy band, generates a large hole barrier, and prevents the hole from generating surface recombination on the surface of the thin film flip Micro-LED display chip.
(7) As shown in FIG. 7, deposition of Ti on the surface of the passivation top layer by PECVD technique 3 O 5 /SiO 2 A distributed bragg mirror 8.
(8) As shown in fig. 8, cr/Pt/Au multilayer metal electrodes 9 were deposited on the n-GaN and ITO surfaces, respectively, using electron beam evaporation technique, to form n-electrodes and p-electrodes.
Wherein the thickness of the Cr layer in the Cr/Pt/Au composite metal layer is about 20nm, the thickness of the Pt layer is about 70nm, and the thickness of the Au layer is 1200-1300 nm.
(9) As shown in fig. 9, the chip on the substrate is peeled by using a mechanical peeling technology, and the mechanical performance of the substrate is reduced by the holes in the substrate, so that the peeling of the substrate and the chip is realized by using the mechanical peeling technology.
(10) As shown in fig. 10, the remaining substrate on the epitaxy is removed using a wet etching technique.
Fig. 11 is a schematic diagram showing the principle of nitrogen ion implantation passivation of the sidewalls of a chip by ion implantation, in which a large number of defects (such as dangling bonds, point defects, etc.) are inevitably introduced into the sidewalls of a Micro-LED chip during the process, and the dangling bonds on the sidewalls of the chip are oxidized to become recombination centers of non-radiative recombination, and electrons and holes are non-radiative recombined therein to generate reverse leakage current, thereby reducing the stability of the device. The nitrogen ions are injected into the side wall of the chip by adopting the ion injection technology to realize effective passivation, on one hand, the nitrogen ions are combined with the surface dangling bonds of the chip, so that the surface state density of the chip is reduced, the surface recombination speed is reduced, on the other hand, a large amount of nitrogen ions are accumulated on the surface of the chip, a surface electric field is formed on the surface of the chip of the nitrogen ions, electrons can be prevented from moving to the surface of the chip, the surface recombination speed is reduced, and the reliability of the chip is improved.
According to the high-reliability film flip-chip Micro-LED display chip and the preparation method thereof, a porous structure is formed in a substrate by adopting an electrochemical corrosion technology, and a fracture layer is provided for the subsequent mechanical stripping of the substrate; the nitrogen ions are injected into the side wall of the chip by adopting the ion injection technology, so that the side wall dangling bonds can be effectively passivated by the nitrogen ions, the surface state density is reduced, an electric field can be formed on the surface of the chip by the nitrogen ions, electrons are prevented from moving to the surface of the chip, the surface recombination speed is reduced, and the reliability of the chip is improved. Atomic layer deposition technique is adopted to produce on the side wall of the chip
The long passivation bottom layer/the high dielectric constant passivation top layer has good passivation bottom layer uniformity, no pinholes on the surface of the film layer, good film forming 5 quality and can prevent water vapor from entering the device. The passivation top layer is made of high dielectric constant material and is covered on the passivation top layer
On the passivation bottom layer, the high dielectric constant material realizes the bending of the chip surface energy band, generates a large hole potential barrier, prevents holes from moving to the side wall of the chip, inhibits the non-radiative recombination of the chip surface, and can obviously reduce the chip leakage current and improve the reliability of the device.
The foregoing is merely a preferred embodiment of the present application, but the scope of the present application is not limited to 0, and any changes or substitutions easily contemplated by those skilled in the art within the technical scope of the present application should be covered by the scope of the present application.

Claims (10)

1. The preparation method of the high-reliability film flip-chip Micro-LED display chip is characterized by comprising the following steps of:
s1, epitaxially growing a GaN-based epitaxial layer on a substrate, wherein the GaN-based epitaxial layer comprises an n-GaN layer and an In which are sequentially stacked 0.12 Ga 0.88 An N/GaN multiple quantum well layer and a p-GaN layer;
s2, depositing an ITO current expansion layer with ohmic contact with the p-GaN layer on the surface of the p-GaN layer of the GaN-based epitaxial layer;
s3, etching the GaN-based epitaxial layer to form a step structure;
s4, implanting nitrogen ions into the side wall of the step structure by adopting an ion implantation technology to form passivation;
s5, sequentially depositing a passivation bottom layer and a passivation top layer made of a high dielectric constant material on the side wall of the step structure from first to second;
s6, depositing a distributed Bragg reflector on the surface of the passivation top layer;
s7, depositing a plurality of layers of metal electrodes on the surfaces of the n-GaN layer and the ITO current expanding layer respectively to form an n electrode and a p electrode;
s8, stripping the substrate.
2. The method of claim 1, further comprising, prior to S1: s11, forming a porous structure on the surface and the inside of the substrate, wherein the density of holes close to the surface of the substrate is high, the size of holes is small, and the density of holes in the substrate is low, and the size of holes is large;
preferably, in S11, the porous structure is formed by electrochemical etching.
3. The method of claim 2, further comprising S12, before S1 and after S11, healing the holes on the surface of the substrate and leveling the surface of the substrate;
preferably, at S12, the hole heals by annealing.
4. The method of manufacturing according to claim 1, wherein the substrate is a silicon substrate, a germanium substrate, silicon carbide or gallium nitride single crystal substrate.
5. The method of claim 1, wherein in S8, the substrate is peeled off mechanically;
preferably, after S8, the step structure further comprises removing the remaining substrate by wet etching.
6. The preparation method according to claim 1, wherein in S1, the GaN-based epitaxial layer is epitaxially grown on the substrate by a metal-organic chemical vapor deposition technique;
preferably, in S2, forming the ITO current spreading layer includes:
s21, depositing an ITO transparent conductive film on the surface of the p-GaN layer by adopting an electron beam evaporation technology;
s22, forming an ITO current expansion layer on the ITO transparent conductive film by adopting a photoetching and wet etching technology;
s23, annealing the ITO current expansion layer to enable the ITO current expansion layer to form ohmic contact with the p-GaN layer;
preferably, in S23, the annealing atmosphere is nitrogen, and the annealing temperature is 550 ℃;
preferably, the thickness of the ITO transparent conductive film is 10nm.
7. The method of claim 1, wherein in S3, the step structure is formed by photolithography to form a pattern, and then etching by inductively coupled plasma technique;
preferably, the step depth is 700-800 nm.
8. The method of claim 1, wherein in S5, the passivation bottom layer is deposited by atomic layer deposition;
preferably, the thickness of the passivation bottom layer is 2-3 nm;
preferably, the thickness of the passivation top layer is 30nm;
preferably, the passivation bottom layer material is Al 2 O 3 ；
Preferably, the passivation top layer material is HfO 2 、Ta 2 O 5 、ZrO 2 、Bi 2 SeO 5 Or Sb (Sb) 2 O 3 。
9. The method according to claim 1, wherein in S6, the deposition method of the distributed bragg mirror is a plasma enhanced chemical vapor deposition technique;
preferably, the distributed Bragg reflector is made of Ti 3 O 5 Or SiO 2 ；
In S7, the deposition method for forming the n-electrode and the p-electrode is an electron beam evaporation technique;
preferably, the material of the multilayer metal electrode is Cr, pt or Au.
10. A high reliability thin film flip chip Micro-LED display chip obtained by the method of manufacturing as claimed in claim 1.
CN202310017693.4A 2023-01-06 2023-01-06 High-reliability film flip Micro-LED display chip and preparation method thereof Pending CN116093233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310017693.4A CN116093233A (en) 2023-01-06 2023-01-06 High-reliability film flip Micro-LED display chip and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310017693.4A CN116093233A (en) 2023-01-06 2023-01-06 High-reliability film flip Micro-LED display chip and preparation method thereof

Publications (1)

Publication Number Publication Date
CN116093233A true CN116093233A (en) 2023-05-09

Family

ID=86205861

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310017693.4A Pending CN116093233A (en) 2023-01-06 2023-01-06 High-reliability film flip Micro-LED display chip and preparation method thereof

Country Status (1)

Country Link
CN (1) CN116093233A (en)

Similar Documents

Publication Publication Date Title
JP4177097B2 (en) Method of manufacturing a semiconductor chip emitting radiation based on III-V nitride semiconductor and semiconductor chip emitting radiation
JP5286045B2 (en) Manufacturing method of semiconductor light emitting device
TWI434433B (en) Method for fabricating light-emitting diode
US7943942B2 (en) Semiconductor light-emitting device with double-sided passivation
JP2014179654A (en) GaN-BASED COMPOUND SEMICONDUCTOR LIGHT EMITTING ELEMENT, AND METHOD OF MANUFACTURING THE SAME
TW201004000A (en) Process for manufacturing optoelectronic device and optoelectronic device
US20110140081A1 (en) Method for fabricating semiconductor light-emitting device with double-sided passivation
JPH10107316A (en) Semiconductor light-emitting device of iii group nitride
WO2018129697A1 (en) Semiconductor component and manufacturing method therefor
KR101008268B1 (en) Vertical Light Emitting Diode and manufacturing method of the same
KR20100002485A (en) Light emitting diode having the transparent electrode layer with nano rods or nano holes and method of fabricating the same
KR100960279B1 (en) Iii-nitride semiconductor light emitting device
KR101018280B1 (en) Vertical Light Emitting Diode and manufacturing method of the same
JP2012060061A (en) Method for manufacturing semiconductor light emitting device and the semiconductor light emitting device
CN116093233A (en) High-reliability film flip Micro-LED display chip and preparation method thereof
KR101136521B1 (en) Light emitting diode and manufacturing method thereof
KR101272707B1 (en) Light emitting diode having nano wire electrode pad and method of fabricating the light emitting diode thereby
KR100996447B1 (en) Iii-nitride semiconductor light emitting device
KR100688037B1 (en) Iii-nitride semiconductor light emitting device
CN217588966U (en) Light-emitting diode
CN113410346B (en) Deep ultraviolet LED chip with flip structure and preparation method thereof
TW201225338A (en) Method for manufacturing light-emitting semiconductor chip
CN101375416B (en) III-nitride semiconductor light emitting device and method for manufacturing the same
KR20090045156A (en) Iii-nitride semiconductor light emitting device
JP2004193498A (en) Semiconductor light-emitting element and manufacturing method therefor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20230925

Address after: 221200 Plant 6, Precision Manufacturing Park, Suining Economic Development Zone, Xuzhou City, Jiangsu Province

Applicant after: Jiangsu Chuandu Optoelectronic Technology Co.,Ltd.

Address before: 430072 No. 299 Bayi Road, Wuchang District, Hubei, Wuhan

Applicant before: WUHAN University