CN116048980A - FPGA prototype verification method and device - Google Patents
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Abstract
The embodiment of the invention provides an FPGA prototype verification method and device, comprising the following steps: the system on a chip of the FPGA receives a target signal sent by an upper computer; the system on a chip of the FPGA determines the type of the target signal according to the time interval between the target signal and the adjacent signal; if the type of the target signal is a control instruction, executing an operation corresponding to the control instruction; if the type of the target signal is the configuration data, executing the configuration data according to a previous control instruction of the configuration data; the configuration data is the software code of the chip module to be verified. The system on chip of the FPGA can accurately distinguish the control instruction from the configuration data according to the time interval between the target signal and the adjacent signal, so that the problem can be quickly found and corrected later, and the system on chip of the FPGA has certain expansibility, so that more control instructions can be conveniently expanded later.
Description
Technical Field
The invention relates to the technical field of communication detection, in particular to an FPGA prototype verification method and device.
Background
Because of the high cost and high cost of the advanced process chip design, the quality of the chip is greatly dependent on verification, wherein one of the verification methods of the chip is FPGA prototype verification.
At present, in the simulation test, preset data and instructions are generally written into codes and are burnt into an FPGA, so that a test result is a test failure, and the codes are required to be readjusted according to the test result and are burnt into the FPGA until the obtained test result is a test success. This results in problems of excessively long time consumption and complicated operation steps.
In summary, how to simply and quickly perform FPGA prototype verification is a technical problem that needs to be solved currently.
Disclosure of Invention
The embodiment of the invention provides an FPGA prototype verification method, which is used for solving the problems of long time consumption and complex operation steps in the prior art due to FPGA prototype verification.
In a first aspect, an embodiment of the present invention provides an FPGA prototype verification method, including: the system on a chip of the FPGA receives a target signal sent by an upper computer; the system on a chip of the FPGA determines the type of the target signal according to the time interval between the target signal and the adjacent signal; if the type of the target signal is a control instruction, executing an operation corresponding to the control instruction; if the type of the target signal is configuration data, executing the configuration data according to a previous control instruction of the configuration data; the configuration data is the software code of the chip module to be verified.
In the embodiment of the invention, the system on a chip of the FPGA can more accurately distinguish the control instruction from the configuration data according to the time interval between the target signal and the adjacent signal, so that the problem can be quickly found and corrected later. And the control instructions are distinguished from the configuration data, so that the system-on-chip of the FPGA has a certain expansibility, and more control instructions can be conveniently expanded later.
Optionally, if the type of the target signal is configuration data, executing the configuration data according to a previous control instruction of the configuration data includes: and if the previous control instruction of the configuration data is a pin configuration instruction, performing pin configuration according to the configuration data.
Optionally, if the type of the target signal is configuration data, executing the configuration data according to a previous control instruction of the configuration data includes: and if the previous control instruction of the configuration data is a burning instruction, burning the configuration data into a storage space corresponding to the burning instruction.
Optionally, the control instruction is an execution instruction; the executing the operation corresponding to the control instruction includes: executing the configuration data burnt in the RAM, and reporting the executed test result to the upper computer; and if the RAM has no configuration data, executing the configuration data burnt in the ROM, and reporting the executed test result to the upper computer.
Optionally, the system on a chip of the FPGA determines the type of the target signal according to a time interval between the target signal and an adjacent signal, including: if the time interval between the target signal and any adjacent signal is larger than a set threshold value, determining the target signal as a control instruction; and if the time intervals between the target signal and the front and rear adjacent signals are all larger than a set threshold value, determining the target signal as configuration data.
Optionally, before the system on chip of the FPGA receives the target signal sent by the host computer, the method further includes: the system on a chip of the FPGA carries out regression testing according to the test script; the test script records the test steps aiming at each chip to be verified; and taking the chip to be verified with test failure in the regression test as the chip to be verified in the subsequent single machine test.
Optionally, the system on chip of the FPGA performs a regression test according to the test script, including: for any chip to be verified, the system on a chip of the FPGA reads the software code of the chip to be verified from a preset folder, burns the software code to the FPGA and executes the software code of the chip to be verified, and writes the test result of the chip to be verified into the preset folder; and the software codes of the chips to be verified are stored in the preset folder, and the test results of the chips to be verified are written in the preset folder.
In a second aspect, an embodiment of the present invention further provides an FPGA prototype verification apparatus, including: the acquisition unit is used for receiving the target signal sent by the upper computer; the processing unit is used for determining the type of the target signal according to the time interval between the target signal and the adjacent signal by the system on chip of the FPGA; if the type of the target signal is a control instruction, executing an operation corresponding to the control instruction; if the type of the target signal is configuration data, executing the configuration data according to a previous control instruction of the configuration data; the configuration data is the software code of the chip module to be verified.
Optionally, the processing unit is specifically configured to: and if the previous control instruction of the configuration data is a pin configuration instruction, performing pin configuration according to the configuration data.
Optionally, the processing unit is specifically configured to: and if the previous control instruction of the configuration data is a burning instruction, burning the configuration data into a storage space corresponding to the burning instruction.
Optionally, the control instruction is an execution instruction; the processing unit is specifically configured to: executing the configuration data burnt in the RAM, and reporting the executed test result to the upper computer; and if the RAM has no configuration data, executing the configuration data burnt in the ROM, and reporting the executed test result to the upper computer.
Optionally, the processing unit is specifically configured to: if the time interval between the target signal and any adjacent signal is larger than a set threshold value, determining the target signal as a control instruction; and if the time intervals between the target signal and the front and rear adjacent signals are all larger than a set threshold value, determining the target signal as configuration data.
Optionally, the acquiring unit further includes: the system on a chip of the FPGA carries out regression testing according to the test script; the test script records the test steps aiming at each chip to be verified; and taking the chip to be verified with test failure in the regression test as the chip to be verified in the subsequent single machine test.
Optionally, the acquiring unit further includes: for any chip to be verified, the system on a chip of the FPGA reads the software code of the chip to be verified from a preset folder, burns the software code to the FPGA and executes the software code of the chip to be verified, and writes the test result of the chip to be verified into the preset folder; and the software codes of the chips to be verified are stored in the preset folder, and the test results of the chips to be verified are written in the preset folder.
In a third aspect, an embodiment of the present invention further provides an electronic device, including at least one processor and at least one memory, where the memory stores a computer program, and when the program is executed by the processor, causes the processor to execute the FPGA prototype verification method in the first aspect.
In a fourth aspect, an embodiment of the present invention further provides a computer readable storage medium storing a program, which when executed on a computer, causes the computer to implement the method for verifying an FPGA prototype in the first aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it will be apparent that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of an FPGA prototype verification method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of identifying a target signal type;
FIG. 3 is a control command mapping chart according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an FPGA prototype verification apparatus according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In a possible scenario, since the design link of the chip is relatively costly, it is necessary to find defects and errors of the chip design by verification before mass production. In the verification process of the chip, the written codes are burnt into the FPGA to perform prototype verification, so that the test result of each chip to be verified is obtained. Wherein prototype verification includes regression testing and stand-alone testing. Firstly introducing regression test, and because a plurality of chips to be verified exist, simulation test is required to be carried out on each chip to be verified, prototype verification can be carried out on each chip to be verified through the regression test, and thus test results of each test module are obtained, wherein the test results comprise test success and test failure. And determining the chip to be verified which fails to be tested as the chip to be verified in the single-machine test, wherein the single-machine test is used for determining which step of the chip to be verified has a problem and debugging the chip to be verified according to the problem until the test result is that the test is successful. Therefore, a stand-alone test is required for the chip to be verified.
Under one possible condition, the chip to be verified is subjected to single-machine test, specifically, the pre-configured data and instructions are burnt into the FPGA together, but the single-machine test is required to be a next step according to the flexible change of the current situation, so that the test result obtained after the single-machine test is burnt into the FPGA, if the test result is a test failure, the data and instructions are required to be re-configured, and the single-machine test is burnt into the FPGA again until the test result is a test success. This results in a long time and cumbersome operation.
In another possible case, one of the characteristics of the simulation test is that the chip to be verified is subjected to the regression test firstly, and then the targeted single-machine test is performed on the chip to be verified according to the result of the regression test, but because the systems of the single-machine test and the regression test are not uniform, the possibility that errors caused by different systems exist in the process of synchronizing data between the regression test and the single-machine test can be caused, and the error of the simulation test is larger.
In summary, the embodiment of the invention provides an FPGA prototype verification method, which is used for simply, conveniently, rapidly and accurately performing FPGA prototype verification.
As shown in fig. 1, a flowchart of an FPGA prototype verification method according to an embodiment of the present invention is provided, where the method includes the following steps:
and step 101, receiving a target signal sent by an upper computer by a system on chip of the FPGA.
In the embodiment of the invention, the upper computer sends the target signal to the system on chip of the FPGA through the serial port, wherein the type of the target signal comprises a control instruction and configuration data.
In step 102, the system on a chip of the fpga determines the type of the target signal according to the time interval between the target signal and the adjacent signal.
In the embodiment of the invention, because the target signals of the system-on-chip sent to the FPGA by the upper computer are all 8 effective UART communication data signals, the system-on-chip of the FPGA can identify the type of the target signals according to the time interval between receiving adjacent target signals, and the corresponding operation is convenient to be executed according to the type of the target signals.
In an embodiment of the present invention, for example, the target signal includes a first signal and a second signal, and if the first signal and the second signal are adjacent signals, a time interval between the first signal and the second signal is greater than a set threshold value, it is indicated that the first signal and the second signal are independent signals, and therefore, the first signal and the second signal are control instructions. If the time interval between the first signal and the second signal is smaller than the set threshold value, it is indicated that the first signal and the second signal are continuous signals, and therefore, it can be determined that the first signal and the second signal are identified as configuration data. See fig. 2.
In the embodiment of the invention, the control instruction comprises an execution instruction, if the RAM has configuration data, the configuration data burnt in the RAM is executed, and the executed test result is reported to the upper computer. If the RAM has no configuration data, the configuration data burnt in the ROM is executed, and the executed test result is reported to the upper computer.
In the embodiment of the present invention, the control instruction includes a pin configuration instruction, a burning instruction, and the like, which are not limited herein. If the previous control instruction of the configuration data is a pin configuration instruction, the pin configuration is carried out according to the configuration data. If the previous control instruction of the configuration data is a burning instruction, the configuration data is burnt into a storage space corresponding to the burning instruction. The configuration data is a software code of the chip module to be verified.
Through the steps 101 to 105, it can be seen that the system on a chip of the FPGA can more accurately distinguish the control instruction from the configuration data according to the time interval between the target signal and the adjacent signal, so that the problem can be found and corrected quickly. And the control instructions are distinguished from the configuration data, so that the system-on-chip of the FPGA has a certain expansibility, and more control instructions can be conveniently expanded later.
In the embodiment of the present invention, before step 101, the upper computer needs to generate the target signal. Specifically, first, a single character needs to be corresponding to a control instruction, as shown in fig. 3, which is a control instruction mapping diagram provided for an embodiment of the present invention. The control instruction is used for switching the current working mode, specifically, the execution instruction corresponds to the single character a, wherein the execution instruction has priority execution, specifically, if the RAM has configuration data, the configuration data burnt in the RAM is executed, and the executed test result is reported to the upper computer. If the RAM has no configuration data, the configuration data burnt in the ROM is executed, and the executed test result is reported to the upper computer. The burning instructions are divided into ROM burning instructions and RAM burning instructions. The ROM programming command corresponding to the single character s, it can be understood that the current operation mode is switched to the ROM programming mode. The RAM burning command corresponding to the single character f can be understood as switching the current working mode to the RAM burning mode. The single character d corresponds to a pin configuration instruction, and it can be understood that the current working mode is switched to a pin configuration mode, and after the current working mode is entered, if the configuration data in the configuration data received next time is a character string, the pin connection configuration is performed according to the identification of the character string. For example, if the character string is 0X01, 0X02 … 0X0a, the character string is identified by configuring pin 1 to port 1, pin 2 to port 2, and pin a to port n. The single character r corresponds to switching the current operating mode to the reset mode. By inputting a single character on a keyboard of the upper computer, a corresponding control instruction can be determined, and then the control instruction is generated into a target signal, so that the target signal can be conveniently transmitted to a system on a chip of the FPGA.
In the embodiment of the invention, for example, if the target signal received by the system on chip of the FPGA at the first moment is a control instruction, the system on chip of the FPGA executes an operation corresponding to the control instruction according to the control instruction. If the target signal received by the system on chip of the FPGA at the second moment is the configuration data, the system on chip of the FPGA identifies a previous control instruction of the configuration data, and then the system on chip of the FPGA executes the configuration data. If the target signal received by the on-chip system of the FPGA at the third moment is an execution instruction signal, the on-chip system of the FPGA judges whether the RAM has configuration data according to the execution instruction, if so, the configuration data burnt in the RAM is executed, and the executed test result is reported to the upper computer; if not, executing the configuration data burnt in the ROM, and reporting the executed test result to the upper computer.
The test results show the test results of each step, and the test results comprise test success and test failure. The first time is earlier than the second time, which is earlier than the third time.
In the embodiment of the invention, the on-chip system of the FPGA sends the test result to the upper computer, and under one possible condition, the test result is a test failure, and the on-chip system of the FPGA receives the adjusted configuration data sent by the upper computer and then the upper computer inputs a single character according to the test failure result of the on-chip system of the FPGA, so that the upper computer can switch the control instruction according to the test failure result of the on-chip system of the FPGA, then generates an adjusted control instruction, then the upper computer sends the control instruction to the on-chip system of the FPGA, the on-chip system of the FPGA subsequently needs to execute corresponding operation according to the control instruction according to the adjusted control instruction, then the on-chip system of the FPGA receives the adjusted configuration data sent by the upper computer, and then the upper computer inputs the single character, thereby realizing the execution instruction, then generates an execution instruction signal and sends the execution instruction signal to the on-chip system of the FPGA, and the on-chip system of the FPGA judges whether the configuration data exists in the RAM according to the execution instruction, if the configuration data exists, the configuration data in the execution is recorded and the execution result is reported to the upper computer; if not, executing the configuration data burnt in the ROM, and reporting the executed test result to the upper computer. And repeating until the test result is that the test is successful.
In the embodiment of the present invention, steps 101 to 105 are specific steps of single-machine test, wherein the chips to be verified mentioned in steps 101 to 105 are chips to be verified of single-machine test, and before step 101, the chips to be verified of single-machine test need to be found out from a plurality of chips to be verified. Then how to determine the chip to be verified for stand-alone testing is described below.
In the embodiment of the invention, as a plurality of chips to be verified which need prototype verification are provided, regression test is needed before single machine test. Specifically, for any chip to be verified, the system on a chip of the FPGA reads the software code of the chip to be verified from a preset folder, burns the software code to the FPGA and executes the software code of the chip to be verified, and writes the test result of the chip to be verified into the preset folder; the software codes of the chips to be verified are stored in a preset folder, and the test results of the chips to be verified are written in the preset folder. The test script records the test steps aiming at each chip to be verified; and taking the chip to be verified with test failure in the regression test as the chip to be verified in the subsequent single machine test. In one possible implementation manner, the chip to be verified which fails in the test can be found from the preset folder by searching for the keyword, wherein the keyword is failed, and then the chip to be verified which fails in the test is determined to be the chip to be verified in the single machine test, so that the problem point can be found out more quickly according to the single machine test and corrected.
Based on the same technical concept, the embodiment of the present invention further provides an FPGA prototype verification apparatus, as shown in fig. 4, where the apparatus 400 includes: an obtaining unit 401, configured to receive a target signal sent by an upper computer; a processing unit 402, configured to determine a type of the target signal according to a time interval between the target signal and an adjacent signal by using a system on chip of the FPGA; if the type of the target signal is a control instruction, executing an operation corresponding to the control instruction; if the type of the target signal is configuration data, executing the configuration data according to a previous control instruction of the configuration data; the configuration data is the software code of the chip module to be verified.
Optionally, the processing unit 402 is specifically configured to: and if the previous control instruction of the configuration data is a pin configuration instruction, performing pin configuration according to the configuration data.
Optionally, the processing unit 402 is specifically configured to: and if the previous control instruction of the configuration data is a burning instruction, burning the configuration data into a storage space corresponding to the burning instruction.
Optionally, the control instruction is an execution instruction; the processing unit 402 is specifically configured to: executing the configuration data burnt in the RAM, and reporting the executed test result to the upper computer; and if the RAM has no configuration data, executing the configuration data burnt in the ROM, and reporting the executed test result to the upper computer.
Optionally, the processing unit 402 is specifically configured to: if the time interval between the target signal and any adjacent signal is larger than a set threshold value, determining the target signal as a control instruction; and if the time intervals between the target signal and the front and rear adjacent signals are all larger than a set threshold value, determining the target signal as configuration data.
Optionally, the acquiring unit 401 further includes: the system on a chip of the FPGA carries out regression testing according to the test script; the test script records the test steps aiming at each chip to be verified; and taking the chip to be verified with test failure in the regression test as the chip to be verified in the subsequent single machine test.
Optionally, the acquiring unit 401 further includes: for any chip to be verified, the system on a chip of the FPGA reads the software code of the chip to be verified from a preset folder, burns the software code to the FPGA and executes the software code of the chip to be verified, and writes the test result of the chip to be verified into the preset folder; and the software codes of the chips to be verified are stored in the preset folder, and the test results of the chips to be verified are written in the preset folder.
Based on the same technical concept, the embodiment of the present application further provides an electronic device, as shown in fig. 5, where the electronic device 500 includes at least one processor 501 and a memory 502 connected to the at least one processor, in the embodiment of the present application, a specific connection medium between the processor 501 and the memory 502 is not limited, and in fig. 5, the processor 501 and the memory 502 are connected by a bus, for example. The buses may be divided into address buses, data buses, control buses, etc.
In the embodiment of the present application, the memory 502 stores instructions executable by the at least one processor 501, and the at least one processor 501 may execute the steps included in the FPGA prototype verification method by executing the instructions stored in the memory 502.
Where the processor 501 is a control center of a computing device, various interfaces and lines may be utilized to connect various portions of the computing device, and to implement data processing by executing or executing instructions stored in the memory 502 and invoking data stored in the memory 502. Alternatively, the processor 501 may include one or more processing units, and the processor 501 may integrate an application processor and a modem processor, where the application processor primarily processes operating systems, user interfaces, application programs, etc., and the modem processor primarily processes issuing instructions. It will be appreciated that the modem processor described above may not be integrated into the processor 501. In some embodiments, processor 501 and memory 502 may be implemented on the same chip, or they may be implemented separately on separate chips in some embodiments.
The processor 501 may be a general purpose processor such as a Central Processing Unit (CPU), digital signal processor, application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, and may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present application. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in connection with the FPGA prototype verification method embodiment may be embodied directly in hardware processor execution or in a combination of hardware and software modules in the processor.
The memory 502, as a non-volatile computer readable storage medium, may be used to store non-volatile software programs, non-volatile computer executable programs, and modules. The Memory 502 may include at least one type of storage medium, and may include, for example, flash Memory, hard disk, multimedia card, card Memory, random access Memory (Random Access Memory, RAM), static random access Memory (Static Random Access Memory, SRAM), programmable Read-Only Memory (Programmable Read Only Memory, PROM), read-Only Memory (ROM), charged erasable programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory), magnetic Memory, magnetic disk, optical disk, and the like. Memory 502 is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory 502 in the present embodiment may also be circuitry or any other device capable of implementing a memory function for storing program instructions and/or data.
Based on the same technical idea, the embodiments of the present application also provide a computer-readable storage medium storing a computer program executable by a computing device, which when run on the computing device, causes the computing device to perform the steps of the above-described FPGA prototype verification method.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (10)
1. An FPGA prototype verification method, comprising:
the system on a chip of the FPGA receives a target signal sent by an upper computer;
the system on a chip of the FPGA determines the type of the target signal according to the time interval between the target signal and the adjacent signal;
if the type of the target signal is a control instruction, executing an operation corresponding to the control instruction;
if the type of the target signal is configuration data, executing the configuration data according to a previous control instruction of the configuration data; the configuration data is the software code of the chip module to be verified.
2. The method of claim 1, wherein if the type of the target signal is configuration data, executing the configuration data according to a previous control instruction of the configuration data comprises:
and if the previous control instruction of the configuration data is a pin configuration instruction, performing pin configuration according to the configuration data.
3. The method of claim 1, wherein if the type of the target signal is configuration data, executing the configuration data according to a previous control instruction of the configuration data comprises:
and if the previous control instruction of the configuration data is a burning instruction, burning the configuration data into a storage space corresponding to the burning instruction.
4. The method of claim 1, wherein the control instruction is an execution instruction;
the executing the operation corresponding to the control instruction includes:
executing the configuration data burnt in the RAM, and reporting the executed test result to the upper computer;
and if the RAM has no configuration data, executing the configuration data burnt in the ROM, and reporting the executed test result to the upper computer.
5. The method of claim 1, wherein the system on a chip of the FPGA determining the type of the target signal based on a time interval between the target signal and an adjacent signal comprises:
if the time interval between the target signal and any adjacent signal is larger than a set threshold value, determining the target signal as a control instruction;
and if the time intervals between the target signal and the front and rear adjacent signals are all larger than a set threshold value, determining the target signal as configuration data.
6. The method of any one of claims 1-5, wherein before the system on a chip of the FPGA receives the target signal sent by the host computer, further comprising:
the system on a chip of the FPGA carries out regression testing according to the test script; the test script records the test steps aiming at each chip to be verified;
and taking the chip to be verified with test failure in the regression test as the chip to be verified in the subsequent single machine test.
7. The method of claim 6, wherein the system on a chip of the FPGA performs regression testing according to a test script, comprising:
for any chip to be verified, the system on a chip of the FPGA reads the software code of the chip to be verified from a preset folder, burns the software code to the FPGA and executes the software code of the chip to be verified, and writes the test result of the chip to be verified into the preset folder; and the software codes of the chips to be verified are stored in the preset folder, and the test results of the chips to be verified are written in the preset folder.
8. An FPGA prototype verification apparatus, comprising:
the acquisition unit is used for receiving the target signal sent by the upper computer;
the processing unit is used for determining the type of the target signal according to the time interval between the target signal and the adjacent signal by the system on chip of the FPGA; if the type of the target signal is a control instruction, executing an operation corresponding to the control instruction; if the type of the target signal is configuration data, executing the configuration data according to a previous control instruction of the configuration data; the configuration data is the software code of the chip module to be verified.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method of any of claims 1-7 when the program is executed by the processor.
10. A computer readable storage medium, characterized in that it stores a computer program executable by a computer device, which program, when run on the computer device, causes the computer device to perform the steps of the method according to any of claims 1-7.
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