CN115964237A - Method and device for testing functions and performance of Central Processing Unit (CPU) - Google Patents
Method and device for testing functions and performance of Central Processing Unit (CPU) Download PDFInfo
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Abstract
The embodiment of the invention relates to a method and a system for testing functions and performance of a Central Processing Unit (CPU). The method comprises the following steps: in the simulation test of the programmable array logic FPGA, configuring at least one piece of random test software for a first CPU to be tested so that the first CPU to be tested performs function and performance tests by executing the at least one piece of random test software; after the first CPU to be tested finishes executing the at least one piece of random test software, acquiring an abnormal random test program; in the simulation test based on the software, the abnormal random test program is configured for the second CPU to be tested, so that the second CPU to be tested runs the abnormal random test program, and the fault point of the second CPU to be tested running abnormally is debugged. The random test software is divided into random test programs with finer granularity, so that the range of positioning the error points of the CPU is reduced. And the abnormal random test program is configured to the simulation system, so that the test time of the second CPU to be tested is shortened, and the development cycle is accelerated.
Description
Technical Field
The embodiment of the invention relates to the technical field of processors, in particular to a method, a system, a device, a computing device and a computer readable storage medium for testing functions and performances of a Central Processing Unit (CPU).
Background
The Central Processing Unit (CPU) is the core brain of many devices, and its importance is self evident. The reliability, stability, versatility and comprehensiveness of the functions of the CPU affect the final quality of the overall device. Therefore, the function and performance test of the CPU becomes very complicated and rigorous.
In the existing method for testing functions and performance of a CPU, a Simulation test (Simulation) based on software is generally performed first, and then a Simulation test (Simulation) based on an FPGA (Field Programmable Gate Array) is performed. In the simulation test, firstly, the test is carried out, and after the problems of the functions and the performance of the CPU are found through observation and analysis, the debugging is carried out aiming at the error points with the problems; and after the function and the performance of the CPU after debugging reach the preset standard, carrying out simulation test. In the simulation test, the test is firstly carried out, and the specific error point of the CPU cannot be determined quickly because the simulation test cannot be observed and analyzed; the debugging process is cumbersome and requires multiple attempts to gradually approach the error point.
In summary, in the simulation test, the test speed is slow because the amount of virtual data is too large, but the debugging speed is fast because the test can be observed and analyzed. In the simulation test, the test is performed based on a real physical module, so the test speed is very high, but the debugging speed is very low because the simulation test cannot be observed and analyzed. If the function and performance of the CPU are tested in the above manner, the development cycle is long.
Disclosure of Invention
The embodiment of the invention provides a method for testing functions and performance of a Central Processing Unit (CPU), which is used for shortening the development period.
In a first aspect, an embodiment of the present invention provides a method for testing a function and performance of a CPU of a central processing unit, including:
in the simulation test of the programmable array logic FPGA, configuring at least one piece of random test software for a first CPU to be tested so that the first CPU to be tested performs function and performance tests by executing the at least one piece of random test software; any random test software comprises n random test programs, and each random test program corresponds to one detection comparison program; the detection comparison program is used for comparing the execution result of the random test program with the standard result corresponding to the random test program according to the first CPU to be tested, and determining the abnormal random test program with the execution result inconsistent with the standard result;
after the first CPU to be tested finishes executing the at least one piece of random test software, acquiring an abnormal random test program;
in a software-based simulation test, configuring the abnormal random test program for a second CPU to be tested so as to enable the second CPU to be tested to run the abnormal random test program, thereby debugging the fault point of the abnormal running of the second CPU to be tested; and the first CPU to be tested is realized by the second CPU to be tested in the hardware of the FPGA board.
In the technical scheme, the random test software comprises n random test programs which are randomly generated, so that the development pressure of developers is reduced. And one detection alignment program after each random test program. The detection comparison program comprises a standard result of normal operation of the random test program. Comparing the execution result of the first to-be-tested CPU for each random test program with the standard result, it can be determined whether the first to-be-tested CPU operates normally in the random test program. If the comparison is inconsistent, the first to-be-tested CPU runs the random test program abnormally, and the abnormal random test program can be reproduced in the simulation test. In the embodiment of the application, each piece of random test software is divided into random test programs with finer granularity, and the execution result of each random test program is judged through a detection comparison program. Therefore, the abnormal random test program which is abnormally executed is determined, and the range of positioning the error point of the CPU is reduced. And configuring the abnormal random test program to the simulation system, so that the second CPU to be tested of the simulation system runs the abnormal random test program, and the granularity of the abnormal random test program is finer, so that the test time of the second CPU to be tested is shortened, and the development period is accelerated. Because the first CPU to be tested is realized by the second CPU to be tested in the hardware of the FPGA board, the second CPU to be tested is debugged in the simulation test, and the determined abnormal fault point is also the abnormal fault point of the first CPU to be tested.
In some embodiments, the random test software is generated by:
generating a random test program;
adopting a framework-level accurate model to run the random test program to obtain a standard result of the random test program; marking the standard result in a detection comparison program corresponding to the random test program;
and after the detection comparison program is arranged in the random test program corresponding to the detection comparison program, returning to the step of generating the random test programs, and after each random test program is arranged in the detection comparison program of the last random test program, generating n random test programs and n detection comparison programs, wherein the n random test programs and the n detection comparison programs form the random test software.
In some embodiments, the placing the detection and alignment program after the random test program corresponding to the detection and alignment program further comprises:
placing a reset program for clearing the state of the CPU behind the detection comparison program;
placing each random test program after the detection alignment program of the previous random test program comprises:
each random test program is placed after the reset program following the test alignment program of the previous random test program.
In some embodiments, the standard result includes at least any one of:
the method comprises the steps of standard memory of a CPU to be tested, a standard state controller of the CPU to be tested, a standard general register of the CPU to be tested, a standard special register of the CPU to be tested and standard computer page table data.
In a second aspect, an embodiment of the present invention further provides a system for testing functions and performance of a CPU of a central processing unit, including: the system comprises a programmable array logic FPGA board, a simulation system and a test server; the FPGA board comprises a first CPU to be tested; the simulation system comprises a second CPU to be tested; the first CPU to be tested is realized by the second CPU to be tested in the hardware of the FPGA board;
the test server is configured to:
in the simulation test of the programmable array logic FPGA, configuring at least one piece of random test software for a first CPU to be tested so that the first CPU to be tested performs function and performance tests by executing the at least one piece of random test software; any random test software comprises n random test programs, and each random test program corresponds to one detection comparison program; the detection comparison program is used for comparing the execution result of the random test program with the standard result corresponding to the random test program according to the first CPU to be tested, and determining the abnormal random test program with the execution result inconsistent with the standard result;
after the first CPU to be tested finishes executing the at least one piece of random test software, acquiring an abnormal random test program;
in the simulation test based on software, the abnormal random test program is configured for a second CPU to be tested, so that the second CPU to be tested runs the abnormal random test program, and the fault point of the second CPU to be tested running abnormally is debugged.
In some embodiments, the test server generates the random test software by:
generating n random test programs;
aiming at each random test program in n random test programs, adopting a framework-level accurate model to operate the random test program to obtain a standard result of the random test program; marking the standard result in a detection comparison program corresponding to the random test program;
and placing the detection comparison program behind the random test program corresponding to the detection comparison program, so that the n random test programs and the n detection comparison programs corresponding to the n random test programs form the random test software.
In some embodiments, after placing the detection and alignment program in the random test program corresponding to the detection and alignment program, the method further includes:
and placing a reset program for clearing the CPU state after the detection comparison program.
In some embodiments, the standard result includes at least any one of:
the CPU testing method comprises the following steps of a memory of a CPU to be tested, a state controller of the CPU to be tested, a general register of the CPU to be tested, a special register of the CPU to be tested and computer page table data.
In a third aspect, an embodiment of the present invention further provides a device for testing a function and performance of a CPU of a central processing unit, including:
a processing unit to:
in the simulation test of the programmable array logic FPGA, configuring at least one piece of random test software for a first CPU to be tested so that the first CPU to be tested performs function and performance tests by executing the at least one piece of random test software; any random test software comprises n random test programs, and each random test program corresponds to one detection comparison program; the detection comparison program is used for comparing the execution result of the random test program with the standard result corresponding to the random test program according to the first CPU to be tested, and determining the abnormal random test program with the execution result inconsistent with the standard result;
acquiring an abnormal random test program after the first CPU to be tested finishes executing the at least one piece of random test software;
in the simulation test based on software, configuring the abnormal random test program for a second CPU to be tested so as to enable the second CPU to be tested to run the abnormal random test program, thereby debugging the fault point of the abnormal running of the second CPU to be tested; and the first CPU to be tested is realized by the second CPU to be tested in the hardware of the FPGA board.
In a fourth aspect, an embodiment of the present invention further provides a computing device, including:
a memory for storing a computer program;
and the processor is used for calling the computer program stored in the memory and executing the function and performance test method for the Central Processing Unit (CPU) listed in any mode according to the obtained program.
In a fifth aspect, an embodiment of the present invention further provides a computer-readable storage medium, where a computer-executable program is stored, where the computer-executable program is configured to enable a computer to execute the method for testing the function and performance of a central processing unit CPU listed in any one of the above manners.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings may be obtained based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for testing functions and performance of a CPU according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a system architecture for testing the functions and performance of a CPU according to an embodiment of the present invention;
FIG. 3a is a schematic flow chart of a method for testing the functions and performance of a central processing unit CPU according to an embodiment of the present invention;
FIG. 3b is a diagram illustrating a random test procedure according to an embodiment of the present invention;
FIG. 3c is a diagram illustrating random test software according to an embodiment of the present invention;
FIG. 3d is a diagram illustrating random test software according to an embodiment of the present invention;
FIG. 3e is a diagram of random test software according to an embodiment of the present invention;
FIG. 4 is a schematic flow chart illustrating a method for testing the functions and performance of a CPU according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a device for testing the functions and performance of a CPU according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a computer device according to an embodiment of the present invention.
Detailed Description
To make the objects, embodiments and advantages of the present application clearer, the following description of exemplary embodiments of the present application will clearly and completely describe the exemplary embodiments of the present application with reference to the accompanying drawings in the exemplary embodiments of the present application, and it is to be understood that the described exemplary embodiments are only a part of the embodiments of the present application, and not all of the embodiments.
All other embodiments, which can be derived by a person skilled in the art from the exemplary embodiments described herein without inventive step, are intended to be within the scope of the claims appended hereto. In addition, while the disclosure herein has been presented in terms of one or more exemplary examples, it should be appreciated that aspects of the disclosure may be implemented solely as a complete embodiment.
It should be noted that the brief descriptions of the terms in the present application are only for convenience of understanding of the embodiments described below, and are not intended to limit the embodiments of the present application. These terms should be understood in their ordinary and customary meaning unless otherwise indicated.
The terms "first," "second," "third," and the like in the description and claims of this application and in the above-described drawings are used for distinguishing between similar or analogous objects or entities and are not necessarily intended to limit the order or sequence of any particular one, unless otherwise indicated. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein.
Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a product or device that comprises a list of elements is not necessarily limited to those elements explicitly listed, but may include other elements not expressly listed or inherent to such product or device.
In the simulation test, a CPU to be tested and each peripheral in a simulation system are virtually constructed, have no real physical module and are virtual simulation. States of the CPU to be tested and any register, logic gate, memory space, and the like of each peripheral device can all be observed and tracked within a full clock cycle by using an Electronic Design Automation (EDA) tool. Therefore, based on the assumed scene, the prior simulation has high controllability and observability, is easy to debug, has recoverable coverage rate and is suitable for the early hardware development stage. However, the virtual data size is large, which consumes a lot of time of the machine, and thus the test speed is slow. In conclusion, the test speed of the prior simulation is slow, but the debugging speed is higher.
After the performance of the CPU to be tested reaches the preset standard, the CPU to be tested and the peripheral equipment are downloaded to the FPGA board and set into real physical modules, so that the CPU to be tested and the peripheral equipment are tested in a real physical environment under the configuration of test software, namely, the simulation test based on the FPGA. Because the CPU to be tested and each peripheral are real physical modules and are accelerated based on hardware, the testing speed is high. But debugging is slow, for example a single step debugging method may be used. The single step debugging refers to generally using a Joint Test Action Group (JTAG) interface and a Universal Asynchronous Receiver/Transmitter (UART) interface of an FPGA board to perform input and output, and analyzing again after outputting a specific observable hardware such as a state register, a general purpose register and a memory space of a CPU to be measured at a specific operation time point, and gradually approaching an error point after performing effective iterative debugging by repeatedly using output contents. The debugging process is extremely time consuming. Therefore, the test speed of the simulation test is faster than that of the simulation test, but the debugging speed is slower.
In summary, the embodiments of the present application provide a method for testing functions and performance of a CPU, so as to shorten a development cycle. In the simulation test, the debugging is not carried out any more, and the debugging process is carried out in the simulation test.
Specifically, firstly, simulation test is carried out, after the performance of the CPU to be tested reaches a preset standard, the CPU to be tested and the peripherals are downloaded to the FPGA board, the CPU to be tested and the peripherals are set into real physical modules, test software is configured for the CPU to be tested and the peripherals, and the test is carried out in a real physical environment, namely simulation test. In the simulation test, the error point may be a problem of testing software, and may also be a hardware error of the CPU which is not captured by the simulation system in the simulation test stage. If unreasonable hardware errors are found, some register values or memory values corresponding to the test software with errors reappear in the simulation test, software and hardware scenes on the FPGA are simulated on the EDA platform of the simulation test as much as possible, and the simulation test can observe and analyze, so that the debugging speed is high.
For example, in the simulation test, 10 pieces of test software are set for the CPU to be tested and each peripheral, and after the test is completed, if it is found that the CPU to be tested operates abnormally with respect to the 2 nd test software, the 2 nd test software and some registers or memory values corresponding to the test software are reproduced in the simulation test. Therefore, in the simulation test, the specific error point of the CPU to be tested is found.
However, the above method has problems that: the code amount of each test software is very large, and if the test software with the abnormality is located in the simulation test and then the test software is reproduced in the simulation test, the test speed is very slow if the large amount of codes are run in the simulation test. For example, 10000 lines of codes of the abnormal test software are located, and we do not know which line of specific codes the CPU to be tested is running, and cannot accurately locate a specific error point. Therefore, the 10000 lines of codes are repeatedly run in the simulation test, the running process is the test, the test speed is extremely slow, and the more the codes are, the slower the running is. Moreover, because of too many codes, the involved influence factors are more, and the scenes in the simulation test are difficult to reproduce in the simulation test.
In summary, another method for testing the functions and performance of the CPU is provided, as shown in fig. 1, and the testing method can be performed by using the testing system shown in fig. 2. The test system of fig. 2 includes: the system comprises a programmable array logic FPGA board, a simulation system and a test server. The FPGA board comprises a first CPU to be tested; the simulation system comprises a second CPU to be tested; the first CPU to be tested is realized by the second CPU to be tested in the hardware of the FPGA board. The test server essentially completes the test method as shown in fig. 1.
The method comprises the following steps:
step 101, configuring at least one piece of random test software for a first CPU to be tested in a simulation test of a programmable array logic FPGA, so that the first CPU to be tested performs function and performance tests by executing the at least one piece of random test software; any random test software comprises n random test programs, and each random test program corresponds to one detection comparison program; the detection comparison program is used for comparing the execution result of the random test program with the standard result corresponding to the random test program according to the first CPU to be tested, and determining the abnormal random test program with the execution result inconsistent with the standard result;
102, acquiring an abnormal random test program after the first CPU to be tested finishes executing the at least one random test software;
103, configuring the abnormal random test program for a second CPU to be tested in a software-based simulation test so that the second CPU to be tested runs the abnormal random test program, thereby debugging the fault point of the second CPU to be tested running abnormally; and the first CPU to be tested is realized by the second CPU to be tested in the hardware of the FPGA board.
In the technical scheme, the random test software comprises n random test programs which are randomly generated, so that the development pressure of developers is reduced. And one detection alignment program after each random test program. The detection comparison program comprises a standard result of normal operation of the random test program. Comparing the execution result of the first to-be-tested CPU for each random test program with the standard result, it can be determined whether the first to-be-tested CPU operates normally in the random test program. If the comparison is not consistent, the first CPU to be tested operates the random test program abnormally, and the abnormal random test program can be reproduced in the simulation test. In the embodiment of the application, each piece of random test software is divided into random test programs with finer granularity, and the execution result of each random test program is judged through a detection comparison program. Therefore, the abnormal random test program which is abnormally executed is determined, and the range of positioning the error point of the CPU is reduced. And configuring the abnormal random test program to the simulation system, so that the second CPU to be tested of the simulation system runs the abnormal random test program, and the granularity of the abnormal random test program is finer, so that the test time of the second CPU to be tested is shortened, and the development period is accelerated. Because the first CPU to be tested is realized by the second CPU to be tested in the hardware of the FPGA board, the second CPU to be tested is debugged in the simulation test, and the determined abnormal fault point is also the abnormal fault point of the first CPU to be tested.
Before testing the function and performance of the CPU to be tested, the test server generates at least one test software. The steps for generating a test software are described below. The test software comprises a plurality of test programs with finer granularity, and can be used in simulation test and simulation test.
The specific steps are shown in fig. 3a, and include:
step 301, generating a random test program;
through the random selection and collocation of the instructions, a random test program is generated, and the random test program comprises at least one instruction. The test software does not need to be manually set and is generated by a machine, so that the development time is saved, and the development pressure of research personnel is reduced. Fig. 3b shows a schematic diagram of a random test program generated by the above method.
302, operating the random test program by adopting an architecture-level accurate model to obtain a standard result of the random test program; marking the standard result in a detection comparison program corresponding to the random test program;
the architecture level precision model is generally provided by a CPU architecture owner, such as an ARM, MIPS or RISCV open source community. And running any random test program in the architecture-level precise model to obtain a standard result corresponding to the random test program. That is, when the CPU is running normally without any exception, the random test program is run to obtain the result. The standard results may be memory of the CPU, state controllers, general purpose registers, special registers, computer page table data, and the like. For example, after running the random test program 1 in the architecture level precision model, the memory of the CPU is a1, the state controller is b1, the general register is c1, the special register is d1, and the computer page table data is e1.
Each random test program corresponds to one detection comparison program, and a standard result obtained by operating a certain random test program by the framework-level accurate model is marked in the detection comparison program corresponding to the random test program. For example, the standard result corresponding to the random test program 1 is labeled in the detection and comparison program 1 corresponding to the random test program 1.
Step 303, after the detection comparison program is placed in the random test program corresponding to the detection comparison program, returning to the step of generating random test programs, and placing each random test program in the detection comparison program of the previous random test program until n random test programs and n detection comparison programs are generated, where the n random test programs and the n detection comparison programs form the random test software.
FIG. 3c shows the placement position of the detection and alignment program 1 corresponding to the random test program 1, and the detection and alignment program 1 is placed after the random test program 1.
The random test program 2 is generated continuously, and the random test program 2 is placed after the detection comparison program 1. And (3) running a random test program 2 on the architecture-level accurate model, marking the obtained standard result in the detection comparison program 2, and placing the detection comparison program 2 behind the random test program 2. A random test program 3 is generated, and the random test program 3 is placed after the detection and comparison program 2. And (3) running a random test program 3 on the architecture-level accurate model, marking the obtained standard result in the detection comparison program 3, and placing the detection comparison program 3 behind the random test program 3. And repeating the steps until n random test programs and n detection comparison programs are generated. The n random test programs and the n detection comparison programs form the random test software.
FIG. 3d shows a possible random test software consisting of n random test programs and n detection alignment programs.
And running the obtained at least one piece of random test software in the simulation system to perform simulation test, wherein the test speed is relatively low. But the simulation system can observe and analyze, so the debugging speed is extremely high. The functions and performance of the CPU to be tested can reach the preset standard through continuous test-debugging iteration. And then downloading the CPU to be tested to the FPGA board for simulation test.
In the simulation test, one possible way is to still configure at least one piece of random test software used in the simulation test to the first CPU to be tested on the FPGA board. And enabling the first CPU to be tested to run the random test software. Another possibility is to re-randomly generate new random test software. In the simulation test, new random test software is configured for the first CPU to be tested. That is, the random test software used in the simulation test and the simulation test may not be the same.
The manner how the failure point of the CPU under test is determined in the simulation test is described below.
In the simulation test, at least one piece of random test software is configured for the first CPU to be tested, and the random test software is generated by adopting the mode described above. The first CPU under test runs these random test software. Then, when each random test program in each random test software is operated, an execution result is obtained; when the detection comparison program is operated, whether the execution result of the first CPU to be tested operating the random test program is consistent with the standard result or not can be determined through the detection comparison program, and if not, the random test program is determined to be an abnormal random test program.
After the first CPU to be tested finishes running all the random test software, the test server may obtain all the abnormal random test programs. In general, the detection and alignment program can be configured to perform the following actions: and when the execution result is determined to be inconsistent with the standard result, displaying the random test program corresponding to the detection comparison program on a display interface of the test server so as to enable developers to quickly position the abnormal random test program.
For example, the abnormal test programs are obtained as a random test program 1 and a random test program 2 in the random test software 1; random test program 3 and random test program 4 in random test software 5.
Configuring the abnormal random test program for the second CPU to be tested in the simulation system to make the second CPU to be tested run the abnormal random test program, and observing and analyzing in the simulation test, so that the specific fault point of the second CPU to be tested with abnormal operation can be quickly determined. I.e. the debugging speed will be faster. Because the first CPU to be tested is realized by the second CPU to be tested in the hardware of the FPGA board, the fault point of the second CPU to be tested with abnormal operation is the fault point of the first CPU to be tested with abnormal operation.
Of course, the abnormal random test software and the detection comparison program corresponding to the abnormal random test software may also be configured for the second CPU to be tested in the simulation system. And enabling the second CPU to be tested to run each abnormal random test software and a detection comparison program corresponding to each abnormal random test software.
It can be found that, by dividing the test software into more fine-grained random test programs, the number of detected and compared nodes is increased, the test granularity is reduced, and the problems are easier to focus and highlight. If n random test programs are not set, the code amount of abnormal random software running in the simulation test every time is too large, and the problem is not easy to locate quickly. And if n random test programs are set, the random test programs with smaller granularity can be directly positioned, and the random test programs with problems can be directly operated in the simulation system, so that the code amount is smaller and the operation speed is higher. Thus shortening the development cycle.
In some embodiments, in order to cut off the hardware correlation between the small particle random test programs and avoid the influence of the previous random test program on the next random test program, after the placing the detection and comparison program in the random test program corresponding to the detection and comparison program, the method further includes: and placing a reset program for clearing the CPU state after the detection comparison program. Then placing each random test program after the test alignment program of the last random test program comprises: each random test program is placed after the reset program following the test alignment program of the previous random test program.
Specifically, a reset program is set behind each detection and comparison program and used for clearing state changes caused by the operation of the detection and comparison program and the corresponding random test program by the first CPU to be tested. For example, after the first CPU to be tested runs the random test program 1 and detects the comparison program 1, hardware resources such as a memory are greatly consumed, which affects the performance of running the random test program 2. In order to avoid such an influence, after the comparison program 1 is detected, a reset program 1 is set to clear occupation of hardware resources such as a memory of the first CPU to be detected. Figure 3e shows a schematic diagram of one possible random test software.
When the simulation test is performed for the first time, since the function of the CPU to be tested is not yet mature, the number of random test programs may be small, that is, n may be small. With the gradual improvement of the functions of the CPU to be tested, the number of random test programs can be larger during the simulation test.
In some embodiments, the standard result includes at least any one of:
the method comprises the steps of standard memory of a CPU to be tested, a standard state controller of the CPU to be tested, a standard general register of the CPU to be tested, a standard special register of the CPU to be tested and standard computer page table data.
The execution result at least includes any one of the following items:
the system comprises an execution memory of the CPU to be tested, an execution state controller of the CPU to be tested, an execution general register of the CPU to be tested, an execution special register of the CPU to be tested and page table data of the execution computer.
Then the detection and comparison program can compare each execution result with each standard result, and when one execution result is consistent with the standard result, the next execution result is compared with the standard result. If a certain execution result is inconsistent with the standard result, reporting the corresponding random test program and the inconsistent execution result. The reported results can form a table for developers to check, so that the abnormal random test program and the execution result with the abnormality can be quickly positioned.
FIG. 4 shows a possible flow chart for forming an abnormal random test program and executing results, comprising:
step 401, acquiring each execution result of the random test program 1 executed by the CPU to be tested;
step 402, comparing whether the value of the execution memory of the CPU to be tested in the execution result is consistent with the value of the standard memory in the standard result, and if not, writing the values of the random test program 1 and the execution memory into an exception table.
Step 403, comparing whether the value of the execution state controller of the CPU to be tested in the execution result is consistent with the value of the standard state controller in the standard result, and if not, writing the values of the random test program 1 and the execution state controller into an exception table.
Step 404, comparing whether the value of the general purpose register of the CPU to be tested in the execution result is consistent with the value of the standard general purpose register in the standard result, and if not, writing the values of the random test program 1 and the general purpose register into the exception table.
Step 405, comparing whether the value of the special execution register of the CPU to be tested in the execution result is consistent with the value of the standard special register in the standard result, and if not, writing the values of the random test program 1 and the special execution register into the exception table.
Step 406, comparing whether the value of the execution computer page table data of the CPU to be tested in the execution result is consistent with the value of the standard computer page table data in the standard result, if not, writing the values of the random test program 1 and the execution computer page table data into the exception table.
Table 1 shows one possible exception table.
TABLE 1
| Abnormal random test program for abnormal | Execution result with exception | Specific value |
| Random test procedure 1 | Execution memory | 12％ |
| Executing general purpose registers | 1 | |
| Random test procedure 2 | Execution memory | 14％ |
| Executing computer page table data | 2 |
Based on table 1, the execution result of the abnormal random test program in which the abnormality occurs can be more accurately located. Therefore, a more real environment can be reproduced in the simulation test, and the accuracy of determining the specific fault point of the CPU can be improved.
Based on the same technical concept, fig. 5 exemplarily shows a structure of a function and performance testing apparatus for a central processing unit CPU according to an embodiment of the present invention, where the structure can execute a flow of the function and performance testing for the central processing unit CPU.
As shown in fig. 5, the apparatus specifically includes:
a processing unit 501, configured to:
in the simulation test of the programmable array logic FPGA, configuring at least one piece of random test software for a first CPU to be tested so that the first CPU to be tested performs function and performance tests by executing the at least one piece of random test software; any random test software comprises n random test programs, and each random test program corresponds to one detection comparison program; the detection comparison program is used for comparing the execution result of the random test program with the standard result corresponding to the random test program according to the first CPU to be tested, and determining the abnormal random test program with the execution result inconsistent with the standard result;
acquiring an abnormal random test program after the first CPU to be tested finishes executing the at least one piece of random test software;
in the simulation test based on software, configuring the abnormal random test program for a second CPU to be tested so as to enable the second CPU to be tested to run the abnormal random test program, thereby debugging the fault point of the abnormal running of the second CPU to be tested; the first CPU to be tested is realized by the second CPU to be tested in the hardware of the FPGA board.
In some embodiments, the processing unit 501 is specifically configured to:
generating a random test program;
adopting a framework-level precise model to run the random test program to obtain a standard result of the random test program; marking the standard result in a detection comparison program corresponding to the random test program;
and after the detection comparison program is arranged in the random test program corresponding to the detection comparison program, returning to the step of generating the random test programs, and after each random test program is arranged in the detection comparison program of the last random test program, generating n random test programs and n detection comparison programs, wherein the n random test programs and the n detection comparison programs form the random test software.
In some embodiments, the processing unit 501 is further configured to:
placing a reset program for clearing the CPU state behind the detection comparison program;
the processing unit is specifically configured to: each random test program was placed after the reset program following the test alignment program of the last random test program.
In some embodiments, the standard result includes at least any one of:
the method comprises the steps of standard memory of a CPU to be tested, a standard state controller of the CPU to be tested, a standard general register of the CPU to be tested, a standard special register of the CPU to be tested and standard computer page table data.
Based on the same technical concept, the embodiment of the present application provides a computer device, as shown in fig. 6, including at least one processor 601 and a memory 602 connected to the at least one processor, where a specific connection medium between the processor 601 and the memory 602 is not limited in the embodiment of the present application, and the processor 601 and the memory 602 are connected through a bus in fig. 6 as an example. The bus may be divided into an address bus, a data bus, a control bus, etc.
In the embodiment of the present application, the memory 602 stores instructions executable by the at least one processor 601, and the at least one processor 601 may execute the steps of the method for testing the functions and performance of the central processing unit CPU by executing the instructions stored in the memory 602.
The processor 601 is a control center of the computer device, and may connect various parts of the computer device by using various interfaces and lines, and perform a function and performance test for the central processing unit CPU by executing or executing instructions stored in the memory 602 and calling data stored in the memory 602. In some embodiments, processor 601 may include one or more processing units, and processor 601 may integrate an application processor, which primarily handles operating systems, user interfaces, applications, etc., and a modem processor, which primarily handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 601. In some embodiments, the processor 601 and the memory 602 may be implemented on the same chip, or in some embodiments, they may be implemented separately on separate chips.
The processor 601 may be a general-purpose processor, such as a Central Processing Unit (CPU), a digital signal processor, an Application Specific Integrated Circuit (ASIC), a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, configured to implement or perform the methods, steps, and logic blocks disclosed in the embodiments of the present Application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in a processor.
The memory 602, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The Memory 602 may include at least one type of storage medium, and may include, for example, a flash Memory, a hard disk, a multimedia card, a card-type Memory, a Random Access Memory (RAM), a Static Random Access Memory (SRAM), a Programmable Read Only Memory (PROM), a Read Only Memory (ROM), a charge Erasable Programmable Read Only Memory (EEPROM), a magnetic Memory, a magnetic disk, an optical disk, and so on. The memory 602 is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory 602 in the embodiments of the present application may also be circuitry or any other device capable of performing a storage function for storing program instructions and/or data.
Based on the same technical concept, the embodiment of the present invention further provides a computer-readable storage medium, where a computer-executable program is stored, and the computer-executable program is used to enable a computer to execute the method for testing the functions and performance of the central processing unit CPU listed in any of the above manners.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A method for testing functions and performance of a Central Processing Unit (CPU) is characterized by comprising the following steps:
in the simulation test of the programmable array logic FPGA, configuring at least one piece of random test software for a first CPU to be tested so that the first CPU to be tested performs function and performance tests by executing the at least one piece of random test software; any random test software comprises n random test programs, and each random test program corresponds to one detection comparison program; the detection comparison program is used for comparing the execution result of the random test program with the standard result corresponding to the random test program according to the first CPU to be tested, and determining the abnormal random test program with the execution result inconsistent with the standard result;
acquiring an abnormal random test program after the first CPU to be tested finishes executing the at least one piece of random test software;
in the simulation test based on software, configuring the abnormal random test program for a second CPU to be tested so as to enable the second CPU to be tested to run the abnormal random test program, thereby debugging the fault point of the abnormal running of the second CPU to be tested; the first CPU to be tested is realized by the second CPU to be tested in the hardware of the FPGA board.
2. The method of claim 1, wherein the random test software is generated by:
generating a random test program;
adopting a framework-level accurate model to run the random test program to obtain a standard result of the random test program; marking the standard result in a detection comparison program corresponding to the random test program;
and after the detection comparison program is arranged in the random test program corresponding to the detection comparison program, returning to the step of generating the random test programs, and after each random test program is arranged in the detection comparison program of the last random test program, generating n random test programs and n detection comparison programs, wherein the n random test programs and the n detection comparison programs form the random test software.
3. The method of claim 2, wherein placing the detection alignment program after the random test program corresponding to the detection alignment program further comprises:
placing a reset program for clearing the CPU state behind the detection comparison program;
placing each random test program after the detection alignment program of the previous random test program comprises:
each random test program is placed after the reset program following the test alignment program of the previous random test program.
4. A method according to any one of claims 1 to 3, wherein the standard results include at least any one of:
the method comprises the steps of standard memory of a CPU to be tested, a standard state controller of the CPU to be tested, a standard general register of the CPU to be tested, a standard special register of the CPU to be tested and standard computer page table data.
5. A functional and performance test system for a Central Processing Unit (CPU), comprising: the system comprises a programmable array logic FPGA board, a simulation system and a test server; the FPGA board comprises a first CPU to be tested; the simulation system comprises a second CPU to be tested; the first CPU to be tested is realized by the second CPU to be tested on the FPGA board through hardware;
the test server is configured to:
in the simulation test of the programmable array logic FPGA, configuring at least one piece of random test software for a first CPU to be tested so that the first CPU to be tested performs function and performance tests by executing the at least one piece of random test software; any random test software comprises n random test programs, and each random test program corresponds to one detection comparison program; the detection comparison program is used for comparing the execution result of the random test program with the standard result corresponding to the random test program according to the first CPU to be tested, and determining an abnormal random test program with the execution result inconsistent with the standard result;
acquiring an abnormal random test program after the first CPU to be tested finishes executing the at least one piece of random test software;
in the simulation test based on software, the abnormal random test program is configured for a second CPU to be tested, so that the second CPU to be tested runs the abnormal random test program, and the fault point of the second CPU to be tested running abnormally is debugged.
6. The system of claim 5, wherein the test server generates the random test software by:
generating n random test programs;
aiming at each random test program in n random test programs, adopting a framework-level accurate model to operate the random test program to obtain a standard result of the random test program; marking the standard result in a detection comparison program corresponding to the random test program;
and placing the detection comparison program behind the random test program corresponding to the detection comparison program, so that the n random test programs and the n detection comparison programs corresponding to the n random test programs form the random test software.
7. The system of claim 5, wherein the step of placing the testing alignment program after the random testing program corresponding to the testing alignment program further comprises:
and placing a reset program for clearing the CPU state after the detection comparison program.
8. The system of any one of claims 5 to 7, wherein the standard results include at least any one of:
the CPU testing method comprises the following steps of a memory of a CPU to be tested, a state controller of the CPU to be tested, a general register of the CPU to be tested, a special register of the CPU to be tested and computer page table data.
9. A computing device, comprising:
a memory for storing a computer program;
a processor for calling a computer program stored in said memory, for executing the method of any one of claims 1 to 4 in accordance with the obtained program.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer-executable program for causing a computer to execute the method of any one of claims 1 to 4.
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| CN116467131A (en) * | 2023-06-19 | 2023-07-21 | 上海芯联芯智能科技有限公司 | ECC function verification method, device, medium and equipment of processor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116467131A (en) * | 2023-06-19 | 2023-07-21 | 上海芯联芯智能科技有限公司 | ECC function verification method, device, medium and equipment of processor |
| CN116467131B (en) * | 2023-06-19 | 2023-08-25 | 上海芯联芯智能科技有限公司 | ECC function verification method, device, medium and equipment of processor |
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