CN111400116A - Chip test verification method, computer device and computer readable storage medium - Google Patents
Chip test verification method, computer device and computer readable storage medium Download PDFInfo
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The invention provides a chip test verification method, a computer device and a computer readable storage medium, wherein the method comprises the steps of inputting input data to a chip to be tested, and the chip to be tested calculates the input data to form hardware output data; moreover, the hardware output data is checked and calculated to obtain a hardware output data check value; acquiring a reference output data check value, wherein the reference output data check value is obtained by performing check calculation on reference output data formed by the operation of a code model on input data; and confirming whether the chip to be tested passes the verification or not according to the consistency of the reference output data verification value and the hardware output data verification value. The invention also provides a computer device and a computer readable storage medium for realizing the method. The invention can reduce the time of chip verification and improve the efficiency of chip verification.
Description
Technical Field
The invention relates to the technical field of chip test verification, in particular to a chip test verification method, a computer device for realizing the method and a computer readable storage medium.
Background
A System On Chip (SOC) is widely used in small electronic devices, and generally, the SOC integrates a complete System On a single Chip to package and group all or part of necessary electronic circuits, and generally, the SOC includes a Central Processing Unit (CPU), a memory, a peripheral circuit, and the like.
With the rapid development of large-scale integrated circuits, systems on chips are also upgraded with moore's law and processing technology, the design scale of systems on chips becomes more and more huge, and the performance, scale and complexity supported by video image algorithm ip (intelligent performance) circuits integrated in systems on chips are also correspondingly improved. Under such a background, the development efficiency and reliability of the video image algorithm IP circuit become particularly important, and therefore, chip manufacturers need to perform efficient verification on a designed chip to improve the development efficiency of the chip.
Generally, in the process of developing an IP circuit of a video image algorithm, a template is usually first manufactured by using an FPGA and the FPGA needs to be verified, and if the FPGA passes the verification, a template of an IC chip is manufactured and the IC chip needs to be verified. Whether the chip is an FPGA or an IC chip, the chip is provided with an IP circuit realized by application hardware, and the verification of the IP circuit is the core work of chip verification.
At present, the main way of verifying a chip is to verify the functions realized by a hardware circuit through software. For example, a code model of an algorithm required to implement a function is developed, where the code model may be a C model, such as h.265, a C model of an ISP algorithm, and the like, and then the test case is operated by using the code model to obtain reference output data obtained by the operation of the application software, and the reference output data is used as verification reference data. Taking a video as an example of a test case, the reference output data is often a video including a plurality of images, and each image has a large number of pixels.
Then, the same test case is burned into a chip waiting for testing of the FPGA or the IC chip, and the chip to be tested operates on the data of the test case to obtain hardware output data. If the test case is a video segment, the hardware output data is also a video segment, and each image of the video segment has a large number of pixel points. When verification is carried out, data of each pixel point of the reference output data and data of each pixel point of the hardware output data are required to be compared one by one, whether the hardware output data are completely the same as the reference output data or not is judged, if yes, the chip to be tested is considered to pass the verification, and if not, the verification is not passed.
However, for high-definition or ultra-high-definition videos, due to the fact that the number of pixels of an image is large, the calculation amount is large, the chip verification time is long, and the development progress of a chip is greatly limited. Since the first verification of the chip is performed by using a hardware circuit manufactured by the FPGA, similar verification is required after the chip is manufactured into an IC chip, and pixel points are required to be compared one by one, the development efficiency of the chip is greatly influenced by the operations, and the development progress of the multimedia algorithm type IP circuit is further influenced.
Disclosure of Invention
The invention mainly aims to provide a chip test verification method with short verification time.
Another objective of the present invention is to provide a computer apparatus for implementing the above chip test verification method.
Still another object of the present invention is to provide a computer readable storage medium for implementing the above chip test verification method.
In order to achieve the main purpose of the invention, the chip test verification method provided by the invention comprises the steps of inputting input data to a chip to be tested, and operating the input data by the chip to be tested to form hardware output data; moreover, the hardware output data is checked and calculated to obtain a hardware output data check value; acquiring a reference output data check value, wherein the reference output data check value is obtained by performing check calculation on reference output data formed by the operation of a code model on input data; and confirming whether the chip to be tested passes the verification or not according to the consistency of the reference output data verification value and the hardware output data verification value.
According to the scheme, after the benchmark output data and the hardware output data are calculated, the benchmark output data and the hardware output data are not directly compared, but the check value of the benchmark output data and the check value of the hardware output data are firstly calculated, and whether the chip passes the verification or not is judged by comparing the benchmark output data check value and the hardware output data check value. Because the data volume of the reference output data check value and the hardware output data check value is far smaller than that of the reference output data and the hardware output data, the time for data comparison in the chip verification process can be greatly reduced by comparing the reference output data check value and the hardware output data check value, and the chip development efficiency is improved.
A preferred scheme is that, when the chip to be tested is verified for the first time, acquiring the check value of the reference output data includes: inputting input data into a code model, and operating the input data by the code model to form reference output data; performing check calculation on the reference output data to obtain a check value of the reference output data; the method further comprises the following steps: and storing the benchmark output data check value to a preset folder.
Therefore, when the chip is verified for the first time, after the input data is operated by the preset code model to obtain the reference output data, the verification calculation is performed to obtain the reference output data verification value, and the reference output data verification value is stored in the preset folder, so that the subsequent verification can be conveniently performed, the calculation of the reference output data verification value is not required to be repeated, and the time for verifying the chip is further saved.
The further scheme is that when the chip to be tested is subjected to regression verification, the step of obtaining the check value of the reference output data comprises the following steps: and acquiring a reference output data check value from a preset folder.
Therefore, when the chip is subjected to regression verification, namely the chip is not verified for the first time, the verification value of the reference output data is at least obtained from the preset folder, namely the reference output data is obtained without calculation again, the reference output data is not required to be verified, and the time for the chip to perform regression verification is saved.
The further scheme is that the input data input to the chip to be tested is subjected to verification calculation to obtain a hardware input data verification value; acquiring a reference input data check value, wherein the reference input data check value is obtained by performing check calculation on input data input to the code model; before the consistency of the reference output data check value and the hardware output data check value is judged, executing the following steps: and confirming the consistency of the benchmark input data check value and the hardware input data check value.
Therefore, before the consistency of the reference output data check value and the hardware output data check value is judged, whether the reference input data check value is consistent with the hardware input data check value or not is judged, if not, the data input to the chip to be tested is wrong, and therefore the verification failure can be distinguished from the input data error or the hardware design error of the chip, and the verification efficiency of the chip is improved.
In addition, because the comparison of the input data is also performed by calculating the corresponding check value, the comparison of the input data is not performed directly, and because the input data is likely to be one or more frames of images, if the comparison of the input data is performed, the comparison of the data of each pixel point of the images is often required, so that the compared data volume is very large. According to the invention, by comparing the check values of the input data, the efficiency of input data comparison can be improved, and thus the time for chip verification is saved.
Preferably, the step of confirming the consistency of the reference input data check value and the hardware input data check value comprises: and if the standard input data check value is not consistent with the hardware input data check value, sending out prompt information of input data errors.
Therefore, once the reference input data check value is inconsistent with the hardware input data check value, the input data error is represented, and the tester can clearly know the reason of the verification failure by sending out the prompt message of the input data error.
Further, after sending out the prompt information of the input data error, the following steps are executed: and sending prompt information for re-verification after input data is clarified.
Therefore, once the input data is wrong, a tester can replace correct test data, namely the correct test data is input into the chip to be tested, and the chip to be tested operates again to generate new hardware output data.
Further, when the chip to be tested is verified for the first time, the obtaining of the reference input data check value includes: performing verification calculation on input data input to the code model to obtain a reference input data verification value; and storing the reference input data check value into a preset folder.
Therefore, when the chip is verified for the first time, the generated reference input data check value is stored in the preset folder, so that the reference input data check value does not need to be generated again when the chip is verified in a regression mode, and the chip verification time can be saved.
Further, the step of obtaining the check value of the reference input data during the regression verification of the chip to be tested comprises the following steps: and acquiring a reference input data check value from a preset folder.
Therefore, the generated reference input data check value can be directly obtained from the preset folder during chip regression verification, and the time for chip regression verification is greatly shortened.
In order to achieve the above another object, the present invention provides a computer device including a processor and a memory, wherein the memory stores a computer program, and the computer program implements the steps of the chip test verification method when executed by the processor.
To achieve the above-mentioned further object, the present invention provides a computer program stored on a computer readable storage medium, wherein the computer program, when executed by a processor, implements the steps of the chip test verification method.
Drawings
FIG. 1 is a block diagram of a test platform according to an embodiment of the chip test verification method of the present invention.
FIG. 2 is a flow chart of the first verification of the embodiment of the chip test verification method of the present invention.
FIG. 3 is a flowchart of regression verification according to an embodiment of the chip test verification method of the present invention.
The invention is further explained with reference to the drawings and the embodiments.
Detailed Description
The chip test and verification method is used for testing and verifying the chip, and particularly for testing and verifying integrated circuits such as an FPGA (field programmable gate array) chip or an IC (integrated circuit) chip. The chip test verification method of the invention can be realized by a computer device, the computer device is provided with a processor and a memory, and the processor can realize the following functions when executing a computer program: and operating the code model, carrying out check calculation on the reference input data and the reference output data, comparing and judging a reference input data check value and a hardware input data check value, and comparing a reference output data check value and a hardware output data check value.
The embodiment of the chip test verification method comprises the following steps:
the present embodiment may be applied to a chip testing platform, and the chip testing platform may include a hardware portion and a software portion implemented by a computer program.
For the verification of the chip to be tested, a corresponding software program is developed according to the functions to be realized by the chip to be tested, and a code model is formed, wherein the code model can be developed by using C, C + + or other languages. And then inputting the test case data into the code model, and operating the input data by the code model to obtain reference output data, wherein the reference output data is a reference for comparison. Thus, the chip test platform includes a set of code models.
Referring to fig. 1, a code model 11 may receive input data 10, and preferably, the input data 10 is a preset test case, and the test case may be a video or several frames of images. Of course, the code model 11 also receives configuration parameters and data corresponding to the register configuration 12, and applies these configuration parameters to perform operations on the input data 10.
Upon receiving the input data 10, the code model 11 performs an operation on the input data 10 to form reference output data C1, and the reference output data C1 is usually a single video or several frames of images. For each frame of image, if the resolution of the image is high, the number of pixels of one frame of image may be tens of thousands or even hundreds of millions, and each pixel includes data such as a luminance value, a chrominance value, and the like, and therefore, the data amount of the reference output data C1 is very large.
After the chip 13 to be tested is developed, for example, the first developed chip 13 to be tested is an FPGA, the input data 10 is written into the memory 14, the chip 13 to be tested reads the input data 10 from the memory 14, and the input data 10 is operated according to the corresponding configuration parameters, so as to obtain the hardware output data C2. Typically, the hardware output data C2 is also a piece of video or a number of frames of images. For a frame of image, if the resolution of the image is high, the number of pixels of the image may be tens of thousands or even hundreds of millions.
The existing chip verification method is to compare each pixel point of the reference output data C1 and the hardware output data C2 one by one, because of a lot of pixel points of images, the data of each pixel point are compared one by one, which causes huge computation amount of comparison, and the time consumption for comparison is long, which causes low verification efficiency of the chip.
Therefore, the present embodiment provides the verification algorithm 15 and the verification circuit 16, the verification algorithm 15 performs verification calculation on the reference output data C1 to obtain the reference output data verification value B1, and the verification circuit 16 performs verification calculation on the hardware output data C2 to obtain the hardware output data verification value B2. Then, by comparing whether the reference output data check value B1 is identical to the hardware output data check value B2, i.e., comparing the calculation 20, if they are identical, it can be considered that the chip 13 to be tested can achieve the same function as the code model 11. Since the data amount of the reference output data check value B1 is much smaller than that of the reference output data C1, and the data amount of the hardware output data check value B2 is much smaller than that of the hardware output data C2, the calculation amount for comparing the consistency of the reference output data check value B1 and the hardware output data check value B2 is much smaller than that for comparing the consistency of the reference output data C1 and the hardware output data C2, so that the time required for chip verification is greatly shortened.
In addition, if the reference output data check value B1 is determined to be inconsistent with the hardware output data check value B2, the data input to the chip to be tested 13 may be incorrect, that is, the data input to the chip to be tested 13 is different from the data input to the code model 11. Therefore, in order to distinguish whether the reason of the failure of the chip verification is the input data error or the design error of the chip to be tested 13, the embodiment also compares the input data, and in order to reduce the calculation amount of the input data comparison, the embodiment also performs the verification calculation on the input data and compares the verification value of the input data, so as to reduce the calculation amount of the input data comparison and further reduce the time required by the chip verification.
Specifically, the input data input to the code module 11 is used as reference input data, the reference input data is subjected to the verification calculation of the verification algorithm 15 to obtain a reference input data verification value a1, correspondingly, the input data input to the chip 13 to be tested is used as hardware input data, and the hardware input data is subjected to the verification calculation of the verification circuit 16 to obtain a hardware input data verification value a 2. When comparing the input data, it is only necessary to compare the reference input data verification value a1 with the hardware input data verification value a2, so as to determine whether the input data input to the code module 11 and the input data input to the chip 13 to be tested are the same.
In this embodiment, the verification algorithm 15 for performing the verification calculation on the reference input data and the reference output data is the same algorithm, the verification algorithm 15 may be implemented by using a known verification algorithm, and the specific calculation manner of the verification algorithm is not limited in this embodiment. The check circuit 16 for performing the check calculation on the hardware input data and the hardware output data is the same circuit, and the check circuit 16 may be implemented by a known check circuit. Furthermore, the verification circuit 16 implements the exact same algorithm as the verification algorithm 15.
Referring to fig. 2, if the chip to be tested is verified for the first time, that is, the chip to be tested is verified in the form of FPGA after being developed for the first time, step S1 is executed first, and the input data and the configuration parameters are sent to the chip to be tested, for example, the data of the test case is input to the chip to be tested. Then, step S2 is executed, the chip to be tested performs an operation on the input data, and the data obtained by the operation is the hardware output data C2. Next, step S3 is executed to perform a verification calculation on the input data input to the chip to be tested to obtain a hardware input data verification value a2, and at the same time, to perform a verification on the hardware output data C2 output by the chip to be tested to obtain a hardware output data verification value B2. In this embodiment, the same check circuit 16 is used to perform check calculation on the hardware input data and the hardware output data C2, so that the chip verification platform only needs to be provided with one set of check circuit, thereby reducing the production cost of the chip verification platform.
When the hardware input data and the hardware output data are subjected to verification calculation, a reference input data verification value and a reference output data verification value serving as a comparison reference are also required to be obtained. Therefore, while the steps S1 to S3 are performed, the steps S4 to S6 also need to be performed. In step S4, the test case data is input to the code model, and then, step S5 is executed, and the code model performs an operation on the input data to obtain reference output data C1. Next, step S6 is executed to perform a verification calculation on the reference output data C1, and obtain a reference output data verification value B1. Meanwhile, the input data input to the code model is also subjected to verification calculation, and a reference input data verification value a1 is obtained. In this embodiment, the same verification algorithm 15 is used to perform verification calculation on the reference input data and the reference output data C1, so that the chip verification platform only needs to set one set of verification algorithm, thereby reducing the production cost of the chip verification platform.
For the convenience of the subsequent verification calculation, the step S6 further needs to store the reference input data verification value a1 and the reference output data verification value B1 in a preset folder, for example, a folder designated by the chip verification platform.
Then, a comparison calculation is performed, and step S7 is first performed to determine whether the hardware input data check value a2 matches the reference input data check value a1, and if so, it indicates that the input data input to the chip to be tested is the same as the input data input to the code module, and step S8 is then performed. If the result of the determination in the step S7 is negative, indicating that the input data input to the chip to be tested is not the same as the input data input to the code module, executing step S11, sending a prompt message indicating that the input data is incorrect, so as to notify the tester that the data input to the chip to be tested is incorrect, and requiring the tester to clarify and re-verify the data input to the chip to be tested, that is, executing step S12, inputting correct data to the chip to be tested by the tester, and returning to execute step S1.
Since the step S7 does not need to compare the input data input to the chip to be tested with the input data input to the code model, that is, the data of each pixel point of the image as the input data does not need to be compared one by one, the comparison calculation amount is greatly reduced, and the time for verifying the chip is reduced. In addition, due to the fact that the correctness of the input data is judged, the tester can know that the reason that the verification fails is caused by the input data error, and therefore the reason that the tester analyzes the verification failure of the chip to be tested is reduced, and the verification efficiency of the chip is improved.
Step S8 determines whether the hardware output data check value B2 is consistent with the reference output data check value B1, if so, step S9 is executed to confirm that the chip to be tested passes the verification, otherwise, step S10 is executed to confirm that the chip to be tested does not pass the verification. Since the step S8 does not need to compare the hardware output data with the reference output data of the code model, that is, the data of each pixel point of the image of the hardware output data does not need to be compared with the data of each pixel point of the image of the reference output data one by one, the comparison calculation amount is greatly reduced, and thus the time for chip verification is reduced.
After the first verification of the chip to be tested is completed, a chip manufacturer needs to customize the IC chip according to the FPGA, and after the sample plate of the IC chip is manufactured, the sample plate of the IC chip needs to be verified, which is called as the regression verification of the chip. Referring to fig. 3, when the chip to be tested performs the regression verification, step S21 is executed first, and the input data and the configuration parameters are sent to the chip to be tested, where the chip to be tested is an IC chip. Then, step S22 is executed, the chip to be tested performs an operation on the input data, and the data obtained by the operation is the hardware output data C2. Next, step S23 is executed to perform a verification calculation on the input data input to the chip to be tested to obtain a hardware input data verification value a2, and at the same time, to perform a verification on the hardware output data C2 output by the chip to be tested to obtain a hardware output data verification value B2.
Then, the reference input data check value a1 and the reference output data check value B1 are obtained, and in this embodiment, it is not necessary to perform an operation on the input data through the code model to obtain the reference input data check value a1, it is not necessary to perform an operation on the input data through the code model to obtain the reference output data, and it is even not necessary to perform a check calculation on the reference output data to obtain the reference output data check value B1. Since the reference input data verification value a1 and the reference output data verification value B1 are already stored in the preset folder in step S6 when the chip is verified for the first time, only the reference input data verification value a1 and the reference output data verification value B1 need to be acquired from the preset folder in step S24, and the calculation amount of chip regression verification is saved.
Then, step S25 is executed to determine whether the hardware input data check value a2 matches the reference input data check value a1, and if so, the input data input to the chip under test is the same as the input data input to the code module, and step S26 is executed. If the result of the determination in the step S25 is negative, indicating that the input data input to the chip to be tested is not the same as the input data input to the code module, executing step S29, sending a prompt message indicating that the input data is incorrect, so as to notify the tester that the data input to the chip to be tested is incorrect, and requiring the tester to clarify and re-verify the data input to the chip to be tested, that is, executing step S30, inputting correct data to the chip to be tested by the tester, and returning to execute step S21.
Therefore, when the chip is subjected to regression verification, the comparison between the input data input to the chip to be tested and the input data input to the code model is also not needed, namely, the data of each pixel point of the image serving as the input data is not needed to be compared one by one, the comparison calculation amount is greatly reduced, and the chip verification time is reduced. In addition, due to the fact that the correctness of the input data is judged, the tester can know that the reason that the verification fails is caused by the input data error, and therefore the reason that the tester analyzes the verification failure of the chip to be tested is reduced, and the verification efficiency of the chip is improved.
Step S26 determines whether the hardware output data check value B2 is consistent with the reference output data check value B1, if so, step S27 is executed to confirm that the chip to be tested passes the verification, otherwise, step S28 is executed to confirm that the chip to be tested does not pass the verification. Since the step S26 does not need to compare the hardware output data with the reference output data of the code model, that is, the data of each pixel point of the image of the hardware output data does not need to be compared with the data of each pixel point of the image of the reference output data one by one, the comparison calculation amount is greatly reduced, and thus the time for chip verification is reduced.
Therefore, no matter whether the chip to be tested is subjected to primary verification or regression verification, the verification values are only used for comparison, the data of each pixel point of the image do not need to be compared, the workload of comparison calculation is greatly reduced, the time required by chip verification can be greatly reduced, and the efficiency of chip verification can be greatly improved.
The embodiment of the computer device comprises:
the computer device of this embodiment is a chip test and verification platform for verifying a chip, and the computer device includes a processor and a memory, where the memory stores a computer program that can be run on the processor, and the processor implements each step of the chip test and verification method when executing the computer program.
For example, a computer program may be partitioned into one or more modules that are stored in a memory and executed by a processor to implement the modules of the present invention. One or more of the modules may be a series of computer program instruction segments capable of performing certain functions, which are used to describe the execution of the computer program in the terminal device.
The Processor may be a Central Processing Unit (CPU), or may be other general-purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, a discrete hardware component, or the like. The general-purpose processor may be a microprocessor or the processor may be any conventional processor or the like, the processor being the control center of the terminal device and connecting the various parts of the entire terminal device using various interfaces and lines.
The memory may be used to store computer programs and/or modules, and the processor may implement various functions of the terminal device by running or executing the computer programs and/or modules stored in the memory and invoking data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the cellular phone, and the like. In addition, the memory may include high speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.
A computer-readable storage medium:
the computer program stored in the computer device may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, all or part of the flow in the method according to the above embodiments may be implemented by a computer program, which may be stored in a computer readable storage medium and used by a processor to implement the steps of the chip test verification method.
Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, recording medium, U.S. disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution media, and the like. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, in accordance with legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunications signals.
Finally, it should be emphasized that the present invention is not limited to the above-described embodiments, such as variations of the verification algorithm and the specific verification manner of the verification circuit, or variations of the number of the verification circuits provided, and such variations should also be included in the protection scope of the present invention.
Claims (10)
1. The chip test verification method comprises the following steps:
inputting input data to a chip to be tested, and operating the input data by the chip to be tested to form hardware output data;
the method is characterized in that:
carrying out check calculation on the hardware output data to obtain a hardware output data check value;
acquiring a reference output data check value, wherein the reference output data check value is obtained by performing check calculation on reference output data formed by the operation of the code model on the input data;
and confirming whether the chip to be tested passes the verification according to the consistency of the reference output data verification value and the hardware output data verification value.
2. The chip test verification method according to claim 1, wherein:
when the chip to be tested is verified for the first time, the obtaining of the reference output data check value comprises the following steps:
inputting the input data into the code model, and operating the input data by the code model to form reference output data;
performing check calculation on the reference output data to obtain a check value of the reference output data;
the method further comprises the following steps: and storing the reference output data check value to a preset folder.
3. The chip test verification method of claim 2, wherein:
when the chip to be tested is subjected to regression verification, the step of obtaining the check value of the reference output data comprises the following steps:
and acquiring the reference output data check value from the preset folder.
4. The chip test verification method according to any one of claims 1 to 3, further comprising:
performing verification calculation on input data input to the chip to be tested to obtain a hardware input data verification value;
acquiring a reference input data check value, wherein the reference input data check value is obtained by performing check calculation on input data input to the code model;
before the consistency of the reference output data check value and the hardware output data check value is judged, executing:
and confirming the consistency of the reference input data check value and the hardware input data check value.
5. The chip test verification method of claim 4, wherein:
confirming consistency of the baseline input data check value with the hardware input data check value comprises:
and if the standard input data check value is confirmed to be inconsistent with the hardware input data check value, sending prompt information of input data errors.
6. The chip test verification method according to claim 5, wherein:
after sending out the prompt message of the input data error, executing the following steps: and sending prompt information for re-verification after input data is clarified.
7. The chip test verification method of claim 4, wherein:
when the chip to be tested is verified for the first time, the obtaining of the reference input data check value comprises the following steps:
performing verification calculation on input data input into the code model to obtain a reference input data verification value;
and storing the reference input data check value to a preset folder.
8. The chip test verification method of claim 7, further comprising:
when the chip to be tested is subjected to regression verification, the step of obtaining the check value of the reference input data comprises the following steps:
and acquiring the reference input data check value from the preset folder.
9. Computer arrangement, characterized in that it comprises a processor and a memory, said memory storing a computer program that, when executed by the processor, carries out the steps of the chip test verification method according to any one of claims 1 to 8.
10. A computer-readable storage medium having stored thereon a computer program, characterized in that: the computer program, when executed by a processor, implements the steps of the chip test verification method according to any one of claims 1 to 8.
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